Formal Datapath Verification for ML Accelerators

Formal Datapath Verification for ML Accelerators
by Bernard Murphy on 01-04-2023 at 10:00 am

Datapath complexity min

Formal methods for digital verification have advanced enormously over the last couple of decades, mostly in support of verification in control and data transport logic. The popular view had been that datapath logic was not amenable to such techniques. Control/transport proofs depend on property verification; if a proof is … Read More


Siemens Aspires to AI in PCB Design

Siemens Aspires to AI in PCB Design
by Bernard Murphy on 12-28-2022 at 6:00 am

PCB min

This. AI in PCB design is not a new idea. Other PCB software companies also make that claim. But when a mainstream systems technology company like Siemens talks about the subject, that is noteworthy. They already have an adaptive user interface (UI) for their mechanical modeling suite and to assist in low-code development for application… Read More


Validating NoC Security. Innovation in Verification

Validating NoC Security. Innovation in Verification
by Bernard Murphy on 12-21-2022 at 6:00 am

Innovation New

Network on Chip (NoC) connectivity is ubiquitous in SoCs, therefore should be an attractive attack vector. Is it possible to prove robustness against a broad and configurable range of threats? Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and… Read More


Re-configuring RISC-V Post-Silicon

Re-configuring RISC-V Post-Silicon
by Bernard Murphy on 12-07-2022 at 6:00 am

Post Silicon RISC V extensions min

How do you reconfigure system characteristics? The answer to that question is well established – through software. Make the underlying hardware general enough and use platform software to update behaviors and tweak hardware configuration registers. This simple fact drove the explosion of embedded processors everywhere … Read More


Ant Colony Optimization. Innovation in Verification

Ant Colony Optimization. Innovation in Verification
by Bernard Murphy on 11-28-2022 at 6:00 am

Innovation New

Looking for better ways to search a huge state space in model checking, Ant Colony Optimization (ACO) is one possible approach. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always,… Read More


Configurable Processors. The Why and How

Configurable Processors. The Why and How
by Bernard Murphy on 11-16-2022 at 6:00 am

ARC Configurability min

Configurable processors are hot now, in no small part thanks to RISC-V. Which is an ISA rather than a processor, but let’s not quibble. Arm followed with configurability in Cortex-X. Both were considerably preceded (a couple of decades) by Synopsys ARC® RISC CPUs and CEVA DSPs. Each stressed configurability as a differentiator… Read More


MIPI in the Car – Transport From Sensors to Compute

MIPI in the Car – Transport From Sensors to Compute
by Bernard Murphy on 11-09-2022 at 6:00 am

NXP Camera subsystem min

I’ve written on and off about sensors, ML inference of the output of those sensors and the application of both in modern cars. Neither ADAS nor autonomous/semi-autonomous driving would be possible without these. But until now I have never covered the transport between sensors and the compute that safely turns what they produce… Read More


Slashing Power in Wearables. The Next Step

Slashing Power in Wearables. The Next Step
by Bernard Murphy on 11-02-2022 at 6:00 am

Fitness bamd and phone min

In wearables and hearables, low power is king. Earbuds for example still only manage a half-day active use before we need to recharge. Half a day falls short of truly convenient for most of us – a full day would be much better, allowing for overnight recharge. Physics limits battery sizes so system designers must look to SoC architectures… Read More


Post-Silicon Consistency Checking. Innovation in Verification

Post-Silicon Consistency Checking. Innovation in Verification
by Bernard Murphy on 10-26-2022 at 6:00 am

Innovation New

Many multi-thread consistency problems emerge only in post-silicon testing. Maybe we should take advantage of that fact. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always,… Read More


WEBINAR: Flash Memory as a Root of Trust

WEBINAR: Flash Memory as a Root of Trust
by Bernard Murphy on 10-09-2022 at 4:00 pm

secure flash

It should not come as a surprise that the vast majority of IoT devices are insecure. As an indication, one survey estimates that 98% of IoT traffic is unencrypted. It’s not hard to understand why. Many such devices are cost-sensitive, designing security into a product is hard, buyers aren’t prepared to pay a premium for security … Read More