I wrote recently about Siemens EDA’s philosophy on designing quality in from the outset, rather than trying to verify it in. The first step is moving up the level of abstraction for design. They mentioned the advantages of HLS in this respect and I refined that to “for DSP-centric applications”. A Stanford group recently presented… Read More
Author: Bernard Murphy
LIDAR-based SLAM, What’s New in Autonomous Navigation
SLAM – simultaneous localization and mapping – is already a well-established technology in robotics. This generally starts with visual SLAM, using object recognition to detect landmarks and obstacles. VSLAM alone uses a 2D view of a 3D environment, challenging accuracy; improvements depend on complementary sensing inputs… Read More
Coding Guidelines for Datapath Verification
It has been an article of faith that you can’t use formal tools to validate datapath logic (math components). Formal is for control logic, not datapath, we now realize. We understood the reason – wide inputs (32-bit, 64-bit or more) fed through a multiplier deliver eye-watering state space sizes. State space explosions also happen… Read More
Refined Fault Localization through Learning. Innovation in Verification
This is another look at refining the accuracy of fault localization. Once a bug has been detected, such techniques aim to pin down the most likely code locations for a root cause. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue… Read More
Why Traceability Now? Blame Custom SoC Demand
In the SoC world, we can’t believe our good luck. Every product maker now wants bespoke silicon solutions with the most advanced AI, communications, SLAM, etc. Which is fantastic for business, but this level of demand also drags us into a new level of accountability, especially in requirements traceability. Time was that only … Read More
Why Software Rules AI Success at the Edge
It is an unavoidable fact that machine learning (ML) hardware architectures are evolving rapidly. Initially most visible in datacenters (many hyperscalars have built their own AI chips), the trend is now red-hot in inference engines for the edge, each spinning new ground-breaking methods. Markets demand these advances to … Read More
Tensilica Edge Advances at Linley
The Linley spring conference this year had a significant focus on AI at the edge, with all that implies. Low power/energy is a key consideration, though increasing performance demands for some applications are making this more challenging. David Bell (Product Marketing at Tensilica, Cadence) presented the Tensilica NNE110… Read More
ML-Based Coverage Refinement. Innovation in Verification
We’re always looking for ways to leverage machine-learning (ML) in coverage refinement. Here is an intriguing approach proposed by Google Research. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research… Read More
Assembly Automation. Repair or Replace?
It is difficult to imagine an SoC development team not using some form of automation to assemble their SoCs; the sheer complexity of the assembly task for modern designs is already far beyond hand-crafted top-level RTLs. An increasing number of groups have already opted for solutions based on the IP-XACT integration standard.… Read More
Python in Verification. Veriest MeetUp
Veriest held a recent meetup on a topic that has always made me curious – use of Python in verification. The event, moderated by Dusica Glisic (technical marketing manager at Veriest), started with an intro from Moshe Zalcberg (CEO of Veriest) and talks by Avidan Efody (Apple verification) and Tamás Kállay (Team leader, Veriest).… Read More
More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay