A little thinking outside the box this time. Microsoft is adding automation to their (and LinkedIn) code reviews; maybe we should consider this option also? Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series… Read More
Author: Bernard Murphy
Automated Code Review. Innovation in Verification
Xcelium Safety Certification Rounds Out Cadence Safety Solution
While fully autonomous driving may now be a distant dream, ADAS continues to be a very active industry driver as much for its safety advantages as for other features. Today in the hierarchy of SAE levels, SAE 2+ may represent the most active area of development rather than levels 3 through 5. This range of options still requires a human… Read More
Convergence Between EDA and MCAD and Industrial Software
Cadence hosted a panel at DAC on how EDA, MCAD and industrial software have come together, a topic I always find interesting. Many years ago, I worked on a NAVAIR contract bid team, an eye-opener for a young engineer who thought that innovation started and ended with electronic design. I remember CATIA (3D modeling) being a component… Read More
Back to Basics – Designing Out PPA Risk
I wrote earlier about managing service-level risk in SoC design, since the minimum service level a system can guarantee under realistic traffic is critical to OEM guarantees of dependable system performance. An ABS design which might get bogged down in traffic under only 0.1% of scenarios is of no use to anyone. That said, meeting… Read More
Sondrel Extends ASIC Turnkey Design to Supply Services From Europe to US
It’s no secret that system companies are driving a lot of new silicon. Google, AWS, Tesla and others have well-established design teams delivering differentiated servers, AI engines and other technologies. I’m sure NVIDIA suspects sub rosa projects are already underway in many of these hyperscalers to design out their GPUs.… Read More
Vision Transformers Challenge Accelerator Architectures
For what seems like a long time in the fast-moving world of AI, CNNs and their relatives have driven AI engine architectures at the edge. While the nature of neural net algorithms has evolved significantly, they are all assumed to be efficiently handled on a heterogenous platform processing through the layers of a DNN: an NPU for … Read More
Better Randomizing Constrained Random. Innovation in Verification
Constrained random methods in simulation are universally popular, still can the method be improved? Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.… Read More
Managing Service Level Risk in SoC Design
Discussion on design metrics tends to revolve around power, performance, safety, and security. All of these are important, but there is an additional performance objective a product must meet defined by a minimum service level agreement (SLA). A printer display may work fine most of the time yet will intermittently corrupt the… Read More
Democratizing the Ultimate Audio Experience
I enjoy talking with CEVA because they work on such interesting consumer products (among other product lines). My most recent discussion was with Seth Sternberg (Sensors and Audio software at CEVA), on spatial or 3D audio. The first steps to a somewhat immersive audio experience were stereo and surround sound, placing sound sources… Read More
Arm 2023 Mobile Solutions Continue Gaming Focus
Arm recently announced an update for mobile under the Arm Total Compute Solutions (TCS) label, led by Chris Bergey (Sr. VP/GM for the Client line of business). You’ll remember that Chris headed the infrastructure line of business impressively through the Neoverse brand, as demonstrated by Arm-based servers appearing in multiple… Read More
Intel’s Pearl Harbor Moment