Scaling Data Center Infrastructure for the Terabit Era

Earlier this month, SemiWiki wrote about Synopsys’s complete 1.6T Ethernet IP solution to drive AI and Hyperscale Data Center chips. A technology’s success is all about when, where and how it gets adopted within the ecosystem. In the high-speed ethernet ecosystem, the swift adoption of 1.6T Ethernet relies on key roles and coordinated actions. Technology developers, such as semiconductor companies and IP providers, drive innovation in ethernet technologies, while standardization bodies like IEEE set crucial standards for interoperability. Collaboration among industry players ensures seamless integration of components, and interoperability testing validates compatibility. Infrastructure upgrades are essential to support higher speeds, requiring investments in hardware and networking components.

IEEE hasn’t yet ratified a standard based on 224G SerDes for 1.6Terabit Ethernet. High-speed ethernet is more than just a SerDes, a PCS and a PMA spec. There a lot of different pieces to ratifying an ethernet standard. Will the 1.6T Ethernet get standardized soon? How will the standard get rolled out into the industry? How does the technology evolve to handle latency requirements, and deliver the massive throughput demands and still keep the power at manageable levels? How do SoC designers prepare to support 1.6T ethernet? And what would data center technology look like ten years from now?

The above are the questions that a thought leadership webinar sponsored by Synopsys explored.

The session was hosted by Karl Freund, founder and principal analyst at Cambrian-AI Research. The panelists included John Swanson, HPC IP product line manager, Synopsys; Kent Lusted, principal engineer Ethernet PHY standards advisor, Intel; Steve Alleston, director of business development, OpenLight Photonics; John Calvin, senior wireline IP planner, KeySight Technologies. Those involved in planning for, implementing and supporting high-speed ethernet solutions would find the webinar very informative.

The following is a synthesis of the key points from the webinar.

At the heart of the matter lies the standardization process. While IEEE has yet to ratify a standard based on 224G SerDes for 1.6T Ethernet, the urgency for adoption is palpable. With the rise of artificial intelligence (AI) and machine learning (ML) applications driving the demand for enhanced data processing capabilities, the industry cannot afford to wait. The first wave of adoption is expected to emanate from data centers housing AI processors, where the need for massive data training and learning capabilities is paramount. Subsequently, switch providers like Broadcom and Marvel are poised to facilitate the second wave of adoption by furnishing the infrastructure necessary to support the burgeoning demands.

Amidst this backdrop, standardization bodies such as IEEE play a pivotal role in shaping the future of ethernet technology. IEEE P802.3dj draft specifications are instrumental in defining the parameters for 1.6T Ethernet, encompassing a myriad of physical layer types ranging from backplanes to single-mode fiber optics. However, the ecosystem of ethernet extends beyond IEEE, encompassing various industry bodies that develop specifications for different applications such as InfiniBand and Fibre Channel. Collaboration among these entities is imperative to ensure a robust ecosystem that meets the diverse needs of end-users and operators.

The proliferation of AI and ML applications has accelerated the pace of standardization efforts, compelling bodies like IEEE and OIF to expedite the development of specifications. While the quality of standards necessitates thorough review, the industry’s pressing needs mandate a balance between quality and expediency. This urgency is underscored by the advent of captive interfaces, where AI players who own both ends of the network are forging ahead with proprietary solutions to meet their immediate requirements, necessitating subsequent convergence with industry standards.

As part of this technology evolution, power efficiency emerges as a paramount concern. As the transition to 1.6T Ethernet entails a doubling of power consumption, innovative solutions are imperative to mitigate energy demands. Strategies such as co-packaged optics and silicon photonics hold promise in reducing power consumption while optimizing performance. However, achieving optimal solutions necessitates exploring a landscape of competing architectures and approaches.

As industry players gear up for the advent of 1.6T Ethernet, the role of system-on-chip (SoC) designers becomes pivotal. Despite facing monumental challenges, early access to IP facilitates progress amidst evolving standards. Moreover, power efficiency emerges as a cornerstone of data center evolution, with advancements in signaling efficiency poised to redefine the power landscape. As the march towards 1.6T Ethernet continues, collaboration, innovation, and a keen focus on efficiency will pave the way for a new era of connectivity.

Looking out ten years ahead, the data center promises a paradigm shift towards optical connectivity and enhanced power efficiency. With optics poised to play an increasingly central role, the industry must adapt to a landscape where latency and power consumption are paramount concerns.

Also Read:

TSMC and Synopsys Bring Breakthrough NVIDIA Computational Lithography Platform to Production

Synopsys SNUG Silicon Valley Conference 2024: Powering Innovation in the Era of Pervasive Intelligence

2024 DVCon US Panel: Overcoming the challenges of multi-die systems verification