DAC 2026: Certus Semiconductor Brings Two New I/O Libraries to GlobalFoundries 12nm

Certus Semiconductor, a trusted leader in custom I/O and ESD solutions, will exhibit at Booth 839 during DAC 2026, July 27–29 in Long Beach. This year, Certus is announcing two new developments in GlobalFoundries 12LP and 12LP+ Processes: one I/O library built for commercial SoC and ASIC design teams, and one library purpose-built for radiation-hardened ASIC and FPGA applications in space and defense. Both are progressing to tapeout this year on Global’s 12nm processes.

GH12 I/O Library: A Full-Featured Commercial I/O Library

The Certus GH12 library combines Certus’ prior experience on Global Foundries 12LP and 12LP+ nodes, designed to cover the full range of requirements that real chip designs demand. It goes well beyond a basic GPIO cell, spanning standard and mixed-supply bidirectional I/O, failsafe operation with native I2C capability, a security-focused tamper-detection cell with integrated high-impedance sensing, and analog I/O for digital-domain applications. A complete set of power, supply, and pad ring infrastructure cells means design teams can close out a full pad ring without piecing together solutions from multiple sources.  The Library also support “SLEEP” states and various Power-down Modes.

GH12 operates at 0.8V core and 1.8V/3.3V I/O, meets 2kV HBM ESD with latch-up resistance, covers the full -40°C to 125°C industrial range, and requires no special ESD implants beyond the base GF12 process. It arrives integration-ready with the full deliverable suite: GDS, layout abstracts, CDL and extracted netlists, Verilog, IBIS, LEF, and complete documentation.

GF12 and GG12 Radiation-Hardened I/O Libraries with both standard multi-voltage GPIO and FPGA I/O feature sets.

For programs that demand more, Certus is also delivering a dedicated radiation-hardened-by-design I/O library for both Standard 1.8V to 3.3V GPIO Applications as well as FPGA applications on Global 12LP and Global 12LP+, targeting space and defense programs where I/O reliability under radiation is non-negotiable. The library ports Certus’s proven high-performance and high-voltage I/O architectures to Global’s 12nm processes, applying radiation hardening design techniques. It pairs high-speed differential signaling with wide-range high-voltage I/O’s into a single design, includes integrated on-chip supply regulation, and is built to the same ESD-robust, wide-temperature standards as Certus’s commercial 12LP/LP+ work. The result is an I/O solution that integrates cleanly and protects reliably in the harshest operating environments.

GF12 I/O, Done Right

Global’s 12LP and 12LP+ have become a node of choice for FPGAs, ASICs, and SoCs that need performance, efficiency, and a long-lived foundry ecosystem. Certus brings 16+ years of custom I/O development to Global’s 12nm nodes.

Find us at DAC 2026, Booth 839. July 27–29, Long Beach.

Contact Certus for more information

Also Read:

Modern Trends in I/O and ESD Design at TSMC OIP

EP177: The Certus Approach to Meeting the Challenges of I/O and ESD with Stephen Fairbanks

The Opportunity Costs of using foundry I/O vs. high-performance custom I/O Libraries