Launching high technology product on the semiconductor market after your competitors is not necessarily a weakness. NetSpeed has developed NocStudio, a front end optimization design tool helping architects to create SoC architecture bridging the gap with the back end, floor planning and place and route. Created about 20 years after Sonics and 8 years after Arteris, NetSpeed has capitalized on the positive (Sonics and even more Arteris have evangelized the semiconductor industry about how important NoC integration could be for design optimization and to avoid routing congestion) and learn from competitor’s weaknesses, the most crucial being the need for a NoC to support cache-coherency in modern multi-core designs.
Approaching design teams involved into System-on-Chip (SoC) like Application Processors for smartphones and the numerous SoC developed to support Multimedia, Network Processing, Servers, Computing and so on, NetSpeed has realized that their main competitor is internal design team! NetSpeed evaluates that about 80% of the SoC integrates internally developed solutions like proprietary buses, crossbars, and fabrics.
NocStudio is a graphical tool helping automate an SoC design and generating Gemini NoC, for chips that have cache coherent processor cores (CPUs, GPUs, or DSPs), or Orion NoC for chips that don’t need cache coherence. Gemini supports up to 64 processor clusters and up to 200 other components that may be I/O coherent. Gemini enables a massively parallel chip design with up to 256 CPUs.
Figure 1. NetSpeed’s Gemini network-on-chip.
NocStudio final output includes performance statistics, the RTL files required to synthesize the NoC, a C++ functional model, and verification test benches. By speeding the design process and reducing risks, NetSpeed’s tool helps cutting costs and shortening the time to market. With NetSpeed’s On-Chip Network IP topology that connects all the IP blocks in a preliminary floor plan that optimizes the design for performance, power efficiency, die area, low latency, and deterministic quality of service (QoS).
In addition, NocStudio is a correct-by-construction design tool that prevents fatal errors such as protocol- and network-level deadlocks (To learn more about why this front-end design tool is “correct by construction” and how the tool has been designed, just read this post). NocStudio provides a software layer helping SoC architect providing configurability in a coherent system at no risk. In fact, customer who desires to configure a complex system requires that they either know all of the details needed to configure it correctly, or that there is some method of ensuring that whatever they do specify will behave correctly.
Figure 2. Designing a NoC with NocStudio.
Architects can drag and drop all the desired IP blocks into NocStudio’s main window. With each addition or modification, NocStudio automatically displays a script in the lower window that defines the IP blocks for the synthesis compiler. The other approach is to manually write or edit the script that defines the IP blocks by using the command-line interface in the lower window.
To optimize traffic among IP blocks that may have different latency, bandwidth, or protocol requirements, NocStudio can vary the data-path widths from 8 to 1,024 bits and create up to 8 heterogeneous physical networks and 32 virtual networks. (Virtual networks appear as separate NoCs but use the same wires.) Because Orion and Gemini are intended mainly for ARM-based SoCs, they connect directly to IP blocks that support AMBA 4 (an AMBA 5 version is in development) and AXI protocols. NocStudio’s final output includes performance, power, and area statistics; the RTL files required to synthesize the NoC; a C++ functional model; and verification test benches
Figure 3. Optimizing Orion.
On the figure 3 we can see the chip optimization on a real life example, step by step, placement, layers, routing and channels optimization allows generating a SoC dissipating 60% less power than with AMBA AXI interconnects.
NocStudio is a front end optimization design tool and we think that such tools will become unavoidable for today’s SoC designs, like was software compiler and RTL synthesis before: the Time-To-Market pressure linked with the incredible race for always higher complexity (100’s of million gates, dozens of CPU/GPU/DSP cores) offered by the latest technology node are now pushing to change design methodology. It’s no more acceptable to discover deadlocks at Tape Out (and if you are even more unlucky, afterTO), as new iteration generated by this architecture issue is not only costly, but may jeopardize the SoC success and lead to miserable ROI, just because the TTM window has been missed.
Sooner or later, the industry will embrace front-end design tools that inevitably will look very much like NocStudio. Architects who need a scalable, high-performance, correct-by-construction SoC interconnect should evaluate NetSpeed’s technology, especially if the design requires cache coherence.
I encourage you to read the white paper “Automating Front-End SoC Design With NetSpeed’s On-Chip Network IP” By Tom R. Halfhill from the Linley Group.
From Eric Esteve from IPNEST
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