PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common motherboard interface for personal computers’ graphics cards, hard drives, SSDs, Wi-Fi and Ethernet hardware connections. PCIe has numerous improvements over the older standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER), and native hot-swap functionality. More recent revisions of the PCIe standard provide hardware support for I/O virtualization.
Defined by its number of lanes, the PCI Express electrical interface is also used in a variety of other standards, most notably the laptop expansion card interface ExpressCard and computer storage interfaces SATA Express, U.2 (SFF-8639) and M.2.
Format specifications are maintained and developed by the PCI-SIG (PCI Special Interest Group), a group of more than 900 companies that also maintain the conventional PCI specifications.
Conceptually, the PCI Express bus is a high-speed serial replacement of the older PCI/PCI-X bus. One of the key differences between the PCI Express bus and the older PCI is the bus topology; PCI uses a shared parallel bus architecture, in which the PCI host and all devices share a common set of address, data and control lines. In contrast, PCI Express is based on point-to-point topology, with separate serial links connecting every device to the root complex (host). Because of its shared bus topology, access to the older PCI bus is arbitrated (in the case of multiple masters), and limited to one master at a time, in a single direction. Furthermore, the older PCI clocking scheme limits the bus clock to the slowest peripheral on the bus (regardless of the devices involved in the bus transaction). In contrast, a PCI Express bus link supports full-duplex communication between any two endpoints, with no inherent limitation on concurrent access across multiple endpoints.
In terms of bus protocol, PCI Express communication is encapsulated in packets. The work of packetizing and de-packetizing data and status-message traffic is handled by the transaction layer of the PCI Express port (described later). Radical differences in electrical signaling and bus protocol require the use of a different mechanical form factor and expansion connectors (and thus, new motherboards and new adapter boards); PCI slots and PCI Express slots are not interchangeable. At the software level, PCI Express preserves backward compatibility with PCI; legacy PCI system software can detect and configure newer PCI Express devices without explicit support for the PCI Express standard, though new PCI Express features are inaccessible.
The PCI Express link between two devices can vary in size from one to 32 lanes. In a multi-lane link, the packet data is striped across lanes, and peak data throughput scales with the overall link width. The lane count is automatically negotiated during device initialization, and can be restricted by either endpoint. For example, a single-lane PCI Express (x1) card can be inserted into a multi-lane slot (x4, x8, etc.), and the initialization cycle auto-negotiates the highest mutually supported lane count. The link can dynamically down-configure itself to use fewer lanes, providing a failure tolerance in case bad or unreliable lanes are present. The PCI Express standard defines link widths of x1, x4, x8, x16, and x32. This allows the PCI Express bus to serve both cost-sensitive applications where high throughput is not needed, and performance-critical applications such as 3D graphics, networking (10 Gigabit Ethernet or multiport Gigabit Ethernet), and enterprise storage (SAS or Fibre Channel). Slots and connectors are only defined for a subset of these widths, with link widths in between using the next larger physical slot size.
As a point of reference, a PCI-X (133 MHz 64-bit) device and a PCI Express 1.0 device using four lanes (x4) have roughly the same peak single-direction transfer rate of 1064 MB/s. The PCI Express bus has the potential to perform better than the PCI-X bus in cases where multiple devices are transferring data simultaneously, or if communication with the PCI Express peripheral is bidirectional.
A PCI Express link between two devices consists of one or more lanes, which are dual simplex channels using two differential signaling pairs. PCI Express devices communicate via a logical connection called an interconnect or link. A link is a point-to-point communication channel between two PCI Express ports allowing both of them to send and receive ordinary PCI requests (configuration, I/O or memory read/write) and interrupts (INTx, MSI or MSI-X). At the physical level, a link is composed of one or more lanes. Low-speed peripherals (such as an 802.11 Wi-Fi card) use a single-lane (x1) link, while a graphics adapter typically uses a much wider and therefore faster 16-lane (x16) link.
A lane is composed of two differential signaling pairs, with one pair for receiving data and the other for transmitting. Thus, each lane is composed of four wires or signal traces. Conceptually, each lane is used as a full-duplex byte stream, transporting data packets in eight-bit “byte” format simultaneously in both directions between endpoints of a link. Physical PCI Express links may contain from one to 32 lanes, more precisely 1, 2, 4, 8, 12, 16 or 32 lanes. Lane counts are written with an “x” prefix (for example, “x8” represents an eight-lane card or slot), with x16 being the largest size in common use. Lane sizes are also referred to via the terms “width” or “by” e.g., an eight-lane slot could be referred to as a “by 8” or as “8 lanes wide.”
The bonded serial bus architecture was chosen over the traditional parallel bus because of inherent limitations of the latter, including half-duplex operation, excess signal count, and inherently lower bandwidth due to timing skew. Timing skew results from separate electrical signals within a parallel interface traveling through conductors of different lengths, on potentially different printed circuit board (PCB) layers, and at possibly different signal velocities. Despite being transmitted simultaneously as a single word, signals on a parallel interface have different travel duration and arrive at their destinations at different times. When the interface clock period is shorter than the largest time difference between signal arrivals, recovery of the transmitted word is no longer possible. Since timing skew over a parallel bus can amount to a few nanoseconds, the resulting bandwidth limitation is in the range of hundreds of megahertz.
A serial interface does not exhibit timing skew because there is only one differential signal in each direction within each lane, and there is no external clock signal since clocking information is embedded within the serial signal itself. As such, typical bandwidth limitations on serial signals are in the multi-gigahertz range. PCI Express is one example of the general trend toward replacing parallel buses with serial interconnects; other examples include Serial ATA (SATA), USB, Serial Attached SCSI (SAS), FireWire (IEEE 1394), and RapidIO. In digital video, examples in common use are DVI, HDMI and DisplayPort.
Multichannel serial design increases flexibility with its ability to allocate fewer lanes for slower devices.
Synopsys’ complete DesignWare IP solution for PCI Express (PCIe) 5.0 operating at 32GT/s data rates enables real-time data connectivity with low-latency and high-performance for cloud computing, storage, and AI SoCs.
The low-power, compact IP has been used in dozens of PCIe 5.0 designs with successful tape outs and demonstrated proven interoperability with a range of products in the industry, making it the industry’s lowest-risk solution supporting the key features of the PCIe 5.0 Revision 1.0 and PIPE 5.x specifications, including SerDes architecture and 64-bit PIPE. Synopsys, the industry’s leading IP provider for PCIe, is an active member of the PCI-SIG standards organization, actively contributing to the development and adoption of the PCIe specification. overall, the DesignWare IP for PCI Express has been silicon validated in over 1800 designs with multiple hardware platforms, PHYs and PCIe verification suites, thereby reducing risk and improving time-to-market.
Controller IP for PCI Express 5.0
The silicon-proven controller IP offers flexible datapath support from 32-bit to 512-bit with lane widths ranging from x1 to x16, providing maximum throughput required for data intensive applications. Synopsys’ PCIe 5.0 controller offers industry’s first production-proven 512-bit architecture, providing flexible options to optimize latency and timing closure for SoCs. For best latency performance, the Synopsys controller has demonstrated 1GHz timing closure in real customer applications. The controller IP can be user-configured to support Dual Mode, Endpoint, Root Port, and Switch applications in your choice of datapath widths, PIPE interface widths, and operating frequencies, helping to optimize for size, power, latency, and throughput, and include a rich feature set with extensive ECN support. Advanced RAS features including data protection, extensive debug capabilities, error injection and statistical monitoring helps designers successfully debug and resolve PCI Express linkup issues.
PHY IP for PCI Express 5.0
The PHY IP with leading power, performance, and area is available in a range of advanced FinFET process nodes for a wide range of foundries. It is a multi-protocol PHY that supports a continuous data rate operation from 1.25Gb/s to 32Gb/s. Delivering exceptional signal integrity and jitter performance that exceeds the PCIe standards electrical specifications, the PHY meets the needs of high-speed chip-to-chip, board-to-board, and backplane interfaces. In addition, the DesignWare IP for PCIe 5.0 supports the new Compute Express LINK (CXL) and CCIX v1.1 specifications, allowing more than 36dB channel loss across PVT variations for long reach applications.
Verification IP for PCI Express 5.0
Synopsys VC Verification IP (VIP) for the PCI Express provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve accelerated verification closure of PCIe 5.0 designs. It accelerates testbench development, providing easy-to-use APIs for generating PCIe traffic.
PCIe Express Wikipedia