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Semiconductor Expert Forum

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Cadence spinout at DAC

Cadence spinout at DAC
by Daniel Payne on 06-17-2011 at 5:37 pm
Categories: Uncategorized
2 Comments

Intro
I remember when Celestry was acquired by Cadence because that gave them a hierarchical Fast SPICE simulator to compete with HSIM. In 2007 part of Celestry spun out from Cadence and became Proplus, which now offers a SPICE simulator called NanoDesigner.

Notes
Proplus – US company, founded in 1995 (Used to be Celestry, acquired by Cadence, spun out in 2007)
– R&D in Beijing and Silicon Valley
– NanoDesigner (4 years old): SPICE tool, not Fast SPICEo Compete with: Spectre, FInesim, HSPICE
o Accuracy is the goals
o Statistical SPICE (Monte Carlo technique)
o Customers: Not disclosed
o Pricing: Not disclosed
– IR/EM Verificationo Partnership with Grid Simulation Tech
o Customers: Not yet
Summary
I hadn’t heard of Proplus before last week, so I’ve added it to the list of all SPICE tools on our wiki page.

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RLCK reduction tool at DAC

RLCK reduction tool at DAC
by Daniel Payne on 06-17-2011 at 5:23 pm
Categories: Uncategorized

Intro
Most EDA parasitic extraction tools have built-in RC reduction with no user control however at DAC I learned how Edxact offers a stand-along RLCK reduction tool for IC designers that want more control over what happens to their extracted netlists.


Daniel Borgraeve (on right)

Notes
Edxact
– Started seven years ago
– Fifteen people in the company
– Based in France
– Jivaro: RLCK reduction (RLCC) with user control of results
o Many algorithms to choose from
o Used by Aglient in their GoldenGate tool (RF Simulator)
o Used by Intel
o About 25 customers world wide (Asia, Japan, Korea, US)
o Part of TSMC AMS Reference flow 2.0
o Pricing starts at $100K per license per year

– Comanche:
o Read parasitic
o Create R values point to point, calculate delays
o CAD developers can compare two netlists (Golden versus some extraction tool)
o Parasitic analysis platform
o Used by: AMD, ST Ericsson
o Pricing starts at $100K per license per year
– Partners
o Altos (Library Characterization, used Jivaro)
o Cadence (Integrated into Virtuoso)
o SpringSoft (Integrated into Laker, can annotate parasitic into Laker)
o Mentor (read DSPF, Eldo formats)
o Synopsps (support Star RC and HSPICE syntax)
o TSMC – part of AMS Reference flow
– Runs on: Solaris, Linux, Mac

Summary
If you want more control while reducing RCLK netlists then consider looking at Edxact tools.

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Ciranova Update at DAC

Ciranova Update at DAC
by Daniel Payne on 06-17-2011 at 4:55 pm
Categories: Uncategorized

Intro
Ciranova offers you an alternative for analog layout automation besides Cadence Virtuoso. Mark Nadim provided me an update at DAC last Wednesday.

Notes
New in 2011
– New GUI with schematic, layout and constraints
o Cross probing between all three windows
– Schematic for constraint entry
o Can start with a blank schematic, enter new design
o Read any native OA schematic
o See all the MOS instances in a tree, define layout constraints very quickly
o Drag and drop constraints
o Cross probe between MOS list and Schematic view
o Hierarchy supported
– Helix First Look
o Schematic and Analog constraints in, layout out
o Find in netlist common bulks, get placed together
o Easy way to create initial layout constraints, does auto grouping of layout
– New customers: Marvel
– 28nm migration is important, Helix is an easier way to conform to new design rules
o Auto placement helps on minimum rules
o Read design rules for density and Helix can push transistors apart to reach the rules
– Create many alternative layouts, Extract a netlist, use Calibre parasitics, create fully extracted netlist ready for Berkeley AFS
– Users: Initially the Circuit Designer starts, then handed off to the Layout Designer for completion
– Routing Example: pattern based constraints used, then autoroute between all the rows and columns of placed Devices
– New way to create layout constraints, based on patterns or Python scripts (mostly CAD or Circuit Designers create scripts)

Summary
Ciranova Helix is a tool that can create analog layout using PyCells very rapidly by a Circuit Designer. Demanding IC designers from the largest semiconductor companies in the world use these tools.

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EDA Interoperability at DAC

EDA Interoperability at DAC
by Daniel Payne on 06-17-2011 at 4:42 pm
Categories: EDA, Synopsys

Intro
My Wednesday breakfast at DAC last week was at the Interoperability event sponsored by Synopsys. The Synopsys moderator was so jovial that he reminded me of Jerry Lewis, I was relieved when the guests gave us an update.

Notes
Interconnect Modeling- Open Source Interconnect Technology Format (ITF)o Used by Star RC

– Modeling parasitic of interconnect
– Interconnect Modeling Technical Advisory Board founded, meet twice per year

o Program of IEEE-ISTO
o Andy Brotman, VP Design Infrastructure at GF

IMTAB – foundry perspective
Design starts are slowing in number for each new node (although each new node has more devices)
Need to avoid risks, ensure 1st silicon success
Mistakes are more costly (NRE)
Parasitic variation increases at 20nm, more analysis required
Layout effects need to be simulated earlier
Best in class extraction tools are a must
Standard interconnect tech file used (Star RC, F3D, …)
New layout effects: Orientation dependent width bias

o Rich Laubhan, Engineer and Manager of Signal Integrity at LSI Corporation

User perspective (Used Star RC for 13 years now)
LSI products: HDD controllers, SSD controllers, RAID adapters, networking
Producing 65nm, 40nm, 28nm chips
Many signoff PVT/RC corners
• No real single corner to simulate
Many modes to simulate: functional, scan, BIST, TDF
High speed designs: 500MHz to 2GHz clocks
Can have 200 clock domains
Hierarchical designs with 20M instances
Plot of transistor feature size and number of metal layers (12 layers now)
ITRS plot: total metal interconnect on a chip over time, more resistive effects
No standard test structures to measure R L C values
We use Charge based capacitance measurement (CBCM)
More wires, higher resistance, metal fill effects: designer challenges
LSI Design Flow: Tech File and Design input to Parasitic Extraction, output a SPICE Or SPEF file
• Tech file: cross section, dielectrics, vias, R L C values
Tech File Complexity: IC Cross section with 12 metal layers, dielectrics
• Longer qualification time to meet accuracy goals
• Variation in process causes variation in R L C values
ITF Open source – provides a proven format with support from 130nm to 20nm
ITF Extensions proposed
• Quick process to get ratified
• Layout dependent effects
• TSV
• 28nm and 20nm effects
Desire to use fewer EDA tool formats to keep costs lower
• Changed extraction tools three times for last three technology nodes
Challenges
• Agreement on test structures
• Accurate results

Tenzing Norgay Award
– Surpass common levels of interoperability
– Contribute to overall industry advancement
– Provide a new view of the future
– 2011 Winner: Shreink Mehta
o Work on UPF, SystemVerilog
o Sun SPARC
o OVI and VHDL
o SPIRIT

IPL & Custom Design
– IPL Constraint 1.0, first standard for interoperable analog design constraints
– OPDK and iPDK are cooperating
– Vincent Varo, Process Design Kit Manager, STMicroelectronicso Desire to reduce effort in PDK development, create one PDK not many, use across all EDA tools
o Device Library, DRC, LVS, PEX, SPICE
o Standardized input to PDK development process from all foundries desired
 Standard DRM, Device Specification format
o Challenge: How to validate an automatically created PDK?
o Mulitple methods to create a single iPDK
o Parasitic Extraction technolog file
 IMTAB, or Si2 OPEX WG
o Desire to be EDA Tool independent
o Next steps
 Automate the PDK validation process
 Design re-use and portability
 AMS design portability
 Designs that are DRC and LVS clean by construction

– Ori Galzur, VP VLSI Design Center, TowerJazzo Largest foundry for speciality technologies
o Total of 4 foundries: Newport Beach, Japan, Israel, China
o Approaching $1B in revenues
o Power, BiCMOS, SiGe, RF CMOS, Image Sensor, Mixed-Signal CMOS, eNVM
 1um to .13um
o Specialty PDK for high voltage process
 Automatic device scaling based upon the voltage levels that you need
 ESD rules added to PCELL
 From schematics a designer gets to choose from a GUI all of the device parameters
o Average PDK has over 120 devices
o Each device can be used in: Standard, Shallow NBL, Deep epi
o All devices are voltage scalable, optimized
o Supporting multiple tool sets takes too much engineering effort
o Want one PDK to focus engineering on other value add efforts
o Choose the best foundry, best EDA tools, not locked into a vendor-specific PDK

Summary
– Demand that your Foundry and EDA vendors support iPDK

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One Trillion Transistor IC Layout at DAC

One Trillion Transistor IC Layout at DAC
by Daniel Payne on 06-17-2011 at 4:20 pm
Categories: Uncategorized

Intro
Micro Magic was the only company at DAC that showed an IC layout editor with 1 Trillion transistors loaded in it, wow.


Karen Mangum

Notes
I chatted with Katherine Hays, a 12 year veteran of Micro Magic about what was new at DAC this year.

Max-3D – Can handle stacked wafers with TSV
– Gary Smith’s list of must-see for 3D
– New for 2011: 3D Floor planner
o Mostly a manual process to do TSV on two or more stacked dies
o 3D Floorplanner automatically finds all thos places
o Autoplace 3D vias (placed on edges in this demo because of density of SRAM on top of processor)
o Demo with 3 stacked die, also autoplace 3D vias
o Tezzaron – customer using Max 3D, designing 3D stacked wafer designs. Doing a 7 stacked chip design.
o 3D DRC – Magma has a tool, you can launch Magma inside of Max-3D and view the results interactively
o Pricing:?

OA – we can read and write it

Large designs – Virtuoso cannot move or work on the largest designs, so it’s time to consider using Max or Max-3D

Max – demo with 1 trillion MOS devices at DAC this year
– Tezzaron read in 100GB GDS II layout database into Max

Customers – Most will not be mentioned because of corporate policy.

Summary
We all know that the big three EDA companies have IC layout editors (Cadence, Synopsys, Mentor) but this lesser known EDA company has capacity and 3D features that I don’t see anywhere else.

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Berkeley Design Automation at DAC

Berkeley Design Automation at DAC
by Daniel Payne on 06-17-2011 at 4:01 pm
Categories: Uncategorized

Intro
Simon Young, Product Marketing manager at BDA gave me an update at DAC last week on their circuit simulator, Analog Fast SPICE (AFS).

Notes

Quarterly release: 2011 Q2 now

Speed Improvements: Still 5 to 10X speed improvement over other SPICE tools

Multi-Threading – 2 to 4 X improvement using 4 to 8 cores.

Device Noise – three ways to compute noise: Transient, PSS/pnoise, Oscillator
– Comparing transient noise with PSS they agree with each one to one (Cannot do that in Spectre, they are different values)

Customers – About 120 logos this year

Distributors – Canada, India and Israel added in past year

Competitors – Spectre, FineSIM, Eldo, HSPICE

Customers – high speed IO design, , PLL/DLL clock synthesis and recovery, data convertors, delta-sigma modulators, full-circuit RFCMOS ICs, memories.

Capacity – 10M elements

Summary
BDA coined the product category Analog Fast SPICE to denote a circuit simulator that is SPICE accurate with a 5X to 10X speed improvement over traditional SPICE algorithms. The other EDA vendors claim to have caught up to BDA’s tool, however you’ll just have to benchmark it on your own circuits to determine the speed, accuracy and capacity claims.

I continue to see BDA in growth mode by adding new staff, so their products must be selling well around the world.

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GlobalFoundries Production-Ready @ 28nm in Multiple Locations!

GlobalFoundries Production-Ready @ 28nm in Multiple Locations!
by Daniel Nenni on 06-15-2011 at 11:02 am
Categories: Foundries, GlobalFoundries

GLOBALFOUNDRIES showed off its 28nm design ecosystem at #48DAC last week in San Diego. The company featured a full design ecosystem for its 28nm High-k Metal Gate (HKMG) technology, including silicon-validated flows, process design kits (PDKs), design-for-manufacturing (DFM), and intellectual property (IP) in partnership with industry leaders. 28nm is the second node of HKMG production for GFI with 32nm AMD Llano dice already in the field. CPU’s and GPU’s are the most difficult designs to manufacture and Llano is both.

In case you missed it, here is a reprint of a 28nm HKMG overview from GFI just prior to #48DAC:

High-K/Metal Gate (HKMG) is one of the most significant innovations in CMOS fabrication since the development of silicon VLSI. The 28nm technology is designed for the next generation of mobile smart devices demanding faster GHz processing speeds, lower standby power and longer battery life. To meet these demands, the 32/28nm HKMG solution is a “Gate-First” approach that shares the process flow, design flexibility, design elements and benefits of all previous nodes based upon poly SiON gates. This solution is far superior to present alternatives in scalability (performance, power, die size, design compatibility), cost (a typical foundry customer will save tens of millions of dollars over the course of a 28nm vs. 40nm product portfolio lifecycle) and manufacturability

GLOBALFOUNDRIES’ 28nm-SLP technology is the low-power CMOS offering delivered on a bulk-silicon substrate for mobile applications. Relative to other 28nm technologies, it achieves its lower cost platform by substantially reducing process complexity and mask counts. It offers design flexibility with multi-channel length capability and the ultimate in small die size. Available options include multiple SRAM bit cells for high density and high performance.

Since this process downsizes the footprint and power utilization, it optimizes energy efficiency, which translates into significantly longer battery run times and fewer recharge cycles; the benchmark of wireless devices moving forward. The gate-first HKMG process utilizes a functional voltage below 0.8V, scaling 28nm performance and power proportionately against 40nm-LP poly SiON. Overall performance gains include a 49% higher frequency capability, a 44% reduction in energy utilization per switch and >25% reduction in leakage power per circuit (see Figure 1). The 28nm- SLP, Gate-First process also supports standard overdrive practices providing additional performance and flexibility gains for a broader application base (wireless AND wired).

A significant benefit of 28nm-SLP technology is that it provides hefty analog “headroom” (Vcc-Vt) and low noise performance relative to the offerings of other foundries. Gate-First enables a reduction in design complexity by preserving design architecture and layout style, thereby leveraging design investments with IP reuse. This design compatibility helps reduce the overall risks of adopting 28nm.

The Super-Low Vt option provides a performance boost over traditional Vts at a given process node, opening the door for greater than 2GHz performance. The resulting performance boost with a minimal increase in power makes this option attractive to applications with specific thermal requirements that still require the largest performance envelope.

Conclusions
The 28nm low-power technology presents tremendous value over the 40nm process, for the industry. It achieves substantially smaller die size than competing foundry offerings. Reduced risk is a hallmark of this low-power technology. It facilitates proven high-volume manufacturing at multiple Common Platform Alliance locations globally as well as a fully enabled design ecosystem with IP and tools and proven design flows, while sustaining the industry design style, flexibility and infrastructure utilized at 40nm and all previous technology nodes. This available technology provides superior performance and analog headroom for wider design margin and lower manufacturing cost.

The GFI Concurrent Newsletter is HERE.

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Synopsys IC Validator at DAC

Synopsys IC Validator at DAC
by Daniel Payne on 06-14-2011 at 3:14 pm
Categories: EDA, Synopsys

Intro
At DAC last week I visited the Synopsys demo suite to see what’s new with IC Validator.


Notes
Stelios Diamantidis, PMM
– In-design physical verification
– Sign-off reveals thousands of late stage DRC violations
– 28nm has 1.5K rules, 15K runset sizes
– Metal Fill changes timing
– The DRM can be changed throughout the life of the process

Timing Closure – can be too slow, too many iterations, too time consuming
– A new methodology is needed

IC Validator – verify as you go, early, not at the end of routing
– Run during: Floorplan, P/G, Placement, CTS, final route

In-Design PV: Metal Fill
– Foundry runset used by IC Compiler
– Evaluate timing of critical nets, timing aware metal fill
– Automate ECO process, identify shorts, push route out, comply to DRC rules
– Example of timing driven metal fill evaluation
o Renesas: 6X faster TAT using ICV with ICC
o AMD: 30 minutes to complete Metal Fill, 580K nets

In-Design PV: Signoff DRC
– Incremental Checking (analysis by Layer, Area or rule)
– GDS Merge – remove cell boundaries (full mask checking on demand)
– Automatic DRC Repair (highly localized, router driven), router told where to correct violations
– ST: Used the flow to find and fix 340 violations in just 35 minutes
– TI: Up to 100% auto fix rate , Automatic DRC Repair (ADR)

Smart Error Management
– Milkyway Intgration (direct access to properties)
– Error categorization (automatic linking of violations)
– Interactive filtering (querying or sorting of violations)

Chris Grossman – Corporate AE
Demo of IC Validator, live
– Start with IC Compiler, DRC checking shows 20,330 violations
– Stepping through each DRC violation graphically, decide how to fix DRV violations with scripting or manual efforts
– Another way is to use ICV (DRC checking) inside of ICC (P&R)
– Results of DRC checking shows only 3926 violations, not 20,330 at the end of detailed P&R
o Filter the DRC violations: P/G Nets, Clock Nets, Signal Routes, User Routes
o Re-run just one rule at a time, re-run rules in one rectangular area at a time
o You can leave the floorplanning stage knowing that you are DRC clean
o After checking DRC after PG, it’s time to run DRC after Clock Tree Synthesis (CTS)
o Now only 16 DRC violations found (Found a RAM placement too close to a VDD)
o Run MergeGDS to see where this RAM instance has a DRC violation
o After CTS time to run detailed routing, found only 143 DRC violations now

Summary
– Run In-Design PV at each stage of physical design, not at the end of detailed routing
– In-design physical verification saves weeks of time over the old implement then verify approach
– IC Validator: pre-routing checks, routing checking, automatic repair, timing aware repair
o Next release: 1.5X faster DRC runs, 1.5X smaller fill size, 3X less fill memory
o 20nm: double patterning required, native DPT coloring engine, In-Design decomposition checking
o Equation-based DRC
o Debug Productivity: will have a new LVS graphical schematic viewer, LVS equivalent error browser, graphical runset debugger
o Advanced Nodes: fill-to-target (correct by construction), pattern matching (Prevents manufacturing limiting layout patterns)

ICC – Has 60% market share in P&R

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Extreme DA at DAC

Extreme DA at DAC
by Daniel Payne on 06-14-2011 at 3:01 pm
Categories: Uncategorized

Intro
Over the lunch hour on Tuesday at DAC I met with Emre Tuncer, VP – Product Engineering & Applications and heard about extraction and timing analysis.

Notes

GoldX – parasitic extractor. Fast extractor, recently announced, all new technology, early customer adoption. One customer deploying it in 40nm, soon to be 28nm.
– Sold stand alone.
– Fast run times.
– Scalability, more cores better speed.
– Within 2% of a 3D field solvers on average. Mean is 1.5%, sigma is 1%.
– SPF timing differences are within 5ps.
– Cell-based extractor (not transistor level tool, stay tuned for device extraction)
– Extract each block, then stitch SPF files together at the top level
Focus –static timing analysis (Engine is statistical), reduce the turn around time, less pessimistic models (less fixing).
TSMC – Gold Time is endorsed for Reference Flow (Statistical Timer).
Prime Time, why switch ?
– Faster turn around time
– As good or better than SPICE accuracy
– Better reductions than Prime Time, reduce the amount of pessimism

Gold Time – out for awhile now, OCV is important and short turn around times
– Broadcomm
– Qualcomm
– Xilinx
– Not working as closely with Common Platform partners yet, mostly TSMC
– Quick run times using efficiency, MT

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Tanner EDA at DAC

Tanner EDA at DAC
by Daniel Payne on 06-14-2011 at 2:40 pm
Categories: EDA, Tanner EDA

Intro
For 22 years now Tanner EDAhas been in the business pf offering tools for AMS and MEMS designers. I learned what’s new at DAC on Tuesday morning.

Notes
Nicholas Williams – Director of Product Management

Tanner EDA front end: S-Edit integrates with Berkeley Fast Analog Simulator
W-Edit – is the waveform viewer

Who is Tanner – full suite for custom IC design
– 22 years in industry
– AMS focus
– First on Windows (also Linux)
– 20K licenses, 67 Countries

S-Edit – Schematics (Import Mentor and Cadence legacy data)
– Cross probe between schematics and layout
– Checking
– Launch simulation, make measurements

Berkeley Analog Fast Spice (AFS)
– About 5 to 10X faster than SPICE
– 10M element capacity

W-Edit – setup measurements
– Scripting for sophisticated measurements
– Built in measurement functions

Layout editor – L-Edit

SDL – schematic driven layout

HiPer DevGen – layout generators

HiPer Verify – Netlist extraction tool (Takes Calibre or Assura decks as inputs)

HiPer PX – parasitic extraction
Why choose Tanner?
– Economic price
– Installed base
– PDKs

Why not your own Fast SPICE?
Easier to partner with a leader already.

John Zuk

Last year – Hiper DevGen (Dublin based, IC Mask)
– This year added: Resistor arrays for matching, adding mosfet array generators, adding current mirrors
– Focus is on analog blocks

SDL – read in netlist analyze it, find current mirrors, use Hiper Devgen automatically

Interactive DRC – close enough to final rules, then HiPer Verfiy in batch to complete the layout verification

Open Access – in integration now, L-edit is first, S-edit is next. PC –based we donated technology that they didn’t even have.
– Took more effort than anticipated.
– Working with Si2 to define what OA should be
– iDRC and iLVS are in the future, after L-edit and S-edit, waiting to be embraced
– IPL Constraints – looking at that as well, designer notes, will be part of S-edit
– V16 is due in October and will be the first to support OA

iPDK – Looks more practical than Open PDK
– In V17 this would be supported in 2012, beta by June 2012

Resell BDA tool – 1st line of support,

OEM – parasitic extraction tool (Tuo Delft in Netherlands, HiPer PX extraction)
– Hiper devgen

Tanner version – scaled down version limited by processors and total elements, lighter version, token based
– Worldwide sales agreement
– First copy to be sold very soon

Fiscal Year – 140 new customers in 2011

Greg

3D field solver as an upgrade

V16 – multi user now available

OA – realtime collaboration on the same database

ClioSoft – what is the cost of this?