Intro
I met with CK Lee, founder of Cyber EDA at his booth on Monday evening in San Diego. Last year I learned about their new SPICE circuit simulator named PCSIM, this year the new product is called ADDS-Debugger.

Notes
2010 – Announced a debugger

2011 ADDS Debugger – trace at the transistor level your design
– Signal tracing
– Post-layout debug

o Tracing – which signal triggered that net that rose or fall?
o Trace back to a Primary input
o Cross-probe between auto-generated Schematic and the waveforms
o Pricing: $50K per year
– ADDS Wave
o Pricing: $2K per year
– PCSim
o Pricing: $25K per year
o Post-layout simulation speed improved, 3X
o True SPICE simulator, flattened
o Compete with HSPICE, SPectre, ELdo

Customers – Ali (Taiwan)
– Extreme DA

Based: Santa Clara, CA

Employees: 10

Next Year: Double revenues

Sales: Direct mostly, some distributors

Summary
ADDS Debugger reminded me a lot of what Concept Engineering has been offering for several years now in a transistor-level debugger. What makes this different is that you’re inside of a circuit simulation run when you can visualize the netlist as a schematic and see the node voltages and branch currents.

The SPICE circuit simulator market is crowded with many EDA vendors (Synopsys, Mentor, Cadence, Magma, Berkeley, Tanner EDA), so Cyber EDA has to do something special in order to make PCSIM stand out from the crowd (speed, accuracy, capacity, features).

Intro
John and Ralph from Magma gave me an update on QuickCap at DAC on Monday afternoon in their demo suite.

Notes
John Schritz – Sr AE
Ralph Iverson, Ph. D. (wrote QuickCap)

John Schritz
– Digital Signoff, extraction
– QCP: 2.5D RC for full ASIC designs
– QuickCAP NX: 3D field solver
– QCP:

Demo – 1.5 million instance design, 1.59 million nets, fully P&R, three libraries
– QCP: Gate Level (Star RC competitor)
– QuickCapNX: 3D field solver (Raphael competitor)
– QCP TX: Transistor Level (RC XT competitor)
– QCP
o 10X faster than Star RC
o 20X faster with multi-corner extraction
o Accuracy: +-2% of QuickCap NX
o TSMC qualified at 28nm
o Inputs: LEF, DEF, GDS II
o Scaling: can add multiple corners using only 20% run time, can be distributed across more boxes
o Capacity: 50M instance designs, memory efficiency
o Accuracy (vs Star RC)
o Example: TSMC 40nm, 38K nets
o 1 corner at 5 hrs, 12 corners at 8.4 hours (27X faster than Star RC), using 3.3GHZ CPU, 148GB and 12 CPUs
o One license per four cores (after that add a multi-core to add up to 32 cores)
o 16 Synopsys licenses for a runtime of 60 minutes, vs 2 licenses in 34 minutes
o ½ the run time, ¾ the HW, 1/8 the licenses (compared to Synopsys with 80% market share)
o 3D on demand (add QuickCap NX), name the nets you want best accuracy on
– Tekton – a STA tool
o Reads SPEFS
o Fast STA in minutes
o Concurrent MM/MC
o Accurate with SPICE integration
– Old flow
o Implement, output a GDS II
o Extract, output SPEF
o STA
– New Flow
o Implement
o QCP and Tekton
– QuickCap NX: Industry Golden 3D Field Solver
o Same run time independent on
o Three methods:
 Finite Element (Slowest)
 Boundary Integral (Slow, what Mentor 3D XACT uses)
 QuickCap (Fastest)
o Field-solver accuracy (within 1% of Silicon)
o Good for library characterization, custom, analog
o Flow Inputs: ITF or iRCS from foundary, GDS II layout
o Industry standard solver at IDMs, Foundries
o Edge effects
o Qualified by TSMC
– QCP TX – transistor level extraction
o Millions of transistor capacity
o To be released in 6 months
o For: Custom design, memory, AMS
o CCI – Calibre Connectivity Interface, stress parameters, well proximity
– QCP Demo
o 18 million nets extracted per hour on 8 threads

Summary
Star RC (Synopsys) has plenty of competition from Magma, Mentor and Cadence for IC extraction. I also learned more about 3D Field Solvers on Tuesday at the Pavilion Panel session.

At DAC I spent time in the Magma FineSIM demo suite on Monday morning.

Greg Curtis – Product Director, Custom Design Business Unit

– Talus for Digital Design
– FineSim does: SPICE, FastSPICE, Characterization
– Flows Demoed at DAC: High Performance Core, SOC, ASIC/ASSP, AMS, Memory
– What’s New in FineSim?o RF
o TCL circuit checks
– ADC design trendso Parasitics dominate performance now
o Sensitivity to noise and cross talk
o Operating at low power
o Requires more SPICE, more corners, more analysis
– Cell phone trendso 10+ radios per phone
o Maximum battery life
– FineSim SPICEo Multi-cpu and multi-machine capability
o Standard netlist inputs (HPSICE, ELdo, Spectre)
o ER and IR drop analysis
o Co-simulate with Verilog and VHDL
o New:
 Tcl based circuit checks (interactive simulation)• Customized check that you write to check currents, voltages, timing
• Set breakpoints
• Demo: find all outputs above 2.6V
• Demo: At 5th rising edge, wait 25ns, capture signals, check sum of currents, trigger if >50uA used
• Could write Tcl code to calculate the jitter of a PLL real time during simulation
• Technology could traverse a netlist similar to Calibre PERC, but not there yet
 RF Analysis (Harmonic Balance, Periodic AC Analysis, Periodic Noise, Periodic Transfer, Oscillator Phase Noise)• Multi-CPU capability
• Due in November 2011
• Beta in September 2011
• A new option to FineSim SPICE
• Demo of a 9 stage ring oscillatoro One CPU run first, 25 seconds
o Four CPUs run next, 12 seconds
o FineWave used to show the waveform results
o AC wave, phase noise plot shown
 EM/IR Analysis• Titan is being used for EM/IR Analysis
• Demo of NAND gates in a layout and schematic
• Titan uses the Analog Simulation Environment (AVE)
• EM/IR analysis results viewed on top of the layout using color codes, layout zoomed in when clicking on a specific EM/IR result
• Capacity is a few million MOS devices
o 1.5X Faster than Berkeley (PLL)
o 1.4X faster than Cadence APS (Sigma Delta Modulator)
o 5X faster than Eldo
– FineSim PROo Multi-rate engine, hierarchical processing (but not hierarchical simulation)
o Same features as FineSim HSPICE
o Capacity example had only 4.6M devices
o 7.9X to 16X faster than NanoSim, Hsim,XA (under 2M MOS devices)
Improvements:
– 2011.04 release versus 2010.08o 1CPU, 7.5% less memory. 1.23X run time improvement
Foundry Support
– TSMC, GlobalFoundries, TowerJazz, Lfoundry

Customer Usage:
– 12 of top 20 Semiconductor companies using FineSIM
– Analog Bits, 10X speed up wit FineSim
– ESNUG user: 3X to 10X over HSPICE

Anand Ganesan – Senior Product Engineer (demonstrations)

Summary
FineSIM catches up to HSPICE, Eldo and Spectre in simulating RF circuits.

The Tcl Circuit Check looks similar to the technology in Mentor’s Calibre PERC. Let’s see if they create a product to detect ESD best practices like PERC does.

Everybody knows that digital designers run on pizza and soda, what one might describe as poor food and weak drinks. At DAC in San Diego I discovered a restaurant that gave away the secret to analog design. And you thought it was a good layout editor and a good circuit simulator. But it turns out that the secret to analog is good food and strong drinks.

San Diego Arrival
It’s another picture perfect day in San Diego as I arrived and checked into the Hyatt. The view from the 40th floor looked magnificent, with the Convention Center just a few minutes away in the distance:

Registration

Check in at DAC is quite automated and it took only a minute to receive my official badge with an Independent Media sticker.

EDAC Party
Tonight is the kick-off event first at 6PM sponsored by EDAC and it’s the annual networking event of the year for us in EDA.

Here I met dozens of former co-workers and EDA clients.

Kathryn Kranen (CEO of Jasper) tried valiantly to address the crowd however the din of networking was just too great. Next year I would try just projecting the key messages on a wall, and let them cycle through instead of live speeches.

Gary Smith
Next up is the 7PM event from Gary Smith EDA. I’m really hoping that these two events are in different rooms so that we may actually get to hear over the roar of networking in the back of the room.

We enjoyed a separate meeting room at Gary Smith’s DAC event on Sunday night. 4G signal coverage was not available with my CLEAR device, so no tweeting this year. Others nearby had zero cell-phone signal as well.

Mary Olsson – 3D packaging. Qualcomm is a big user of TSV and 3D packaging.

Current State of Technology
– TSV: not really cheaper, faster or smaller
– Whatever happened with Multi Chip Modules (MCM)?
– 3 fabs are ready at 200nm now, 300 mm ready in 5 years (too much stress and cracking)
– Today: Mostly memory stacking, wafer stacked SOC, image sensors

3D TSV
– Mostly research and University oriented still
– Bleeding Edge Drivers: Intel, Samsung, Qualcomm, TI, STM, Altera
– Xilinx, Nokia, Nvidia, Broadcom, Cisco
– Tessera, Tezzaron, eSilicon

Standard Drivers : GSA, JEDEC, Si2 Open3D

TSMC Revenue by Technology – 1st quarter numbers, 65% of revenue for 90nm to 40nm nodes, mostly standard packages
– 35% of revenue from above 135nm nodes and larger

Top IDMs and Foundries: Where is their capacity?
– Sweet spot is between 45nm and 60nm
– Intel/Samsung vs everybody else
– Qualcomm driving the bleeding edge of 3D packaging technology

TSMC Foundry Drivers
– 48% communications
– 23% consumer
– 18% industrial
– 11% industrial

PCs – shipped 379M units in 2010

iPad (Tablets) – 136m units in 1Q2011

2015 Time frame – next big push from emerging nations to start consuming personal electronics

What is true 3D/TSV?
– Today we see 2.5 and 3D TMV (stacked die for memory, SOC, SiP, Flip Chip, PoP, Cu pillar bump, many via types

AMKOR photos of molded via, package on package techniques

EDA – Sigrity (Orbit10 Planner), Micro Magic (Max 3D), Apache (RedHawk, Sentinel)

What to look for – OSATs, eSilicon, Tessera, Tezzaron

RF challenges

3D Summary

Read the GSA Guide (Herb Reiter)

Follow the money – OSATs spend money on copper wire bonders, new test equipment

Watch those hiring – Intel, Qualcomm

Gary Smith

EDA 2Q 2011 Forecaast
$4896 2011
$5325 2012
$5671 2013
$5885 2014
$6612 2015

The Semiconductor Infrastructure
– The semi cycle: VC funding, EDA, embedded sw, compute power, process r&d, semi equipment, foundry, packaging
EDA – tools to enable design (at a cost that allows operating at a profit)

Costs – Design companies cost more than EDA tools (embarrassed by low price of EDA tools)

Cost of SOC Design – Keep the cost of a new SOC below $25M will attract VCs again.
– Costs above $50M hurts even IDMs

ITRS Cost Chart for 2010

Is EDA affordable?

Design Teams – 100 to 200 engineers
– For 104 million gates (should be about 30 HW design engineers, costing $18.7m)
– 160 SW engineers cost $56M, total of $75M

Cost Curves for HW Design Teams (Needs to be kept under $25M)

Ideal Number of Blocks: 5
– Most designs have 25 to 35 blocks (more blocks slows design process down)

What is Block Size?
– 100 million gate (90 million gates on platform, 10 million left to design)
– Number of engineers per block 6 engineers

EDA Tools Handle gates?
– 4 million minimum, 20 million needed

At 22nm – need 88m gates capacity
At 16nm – need 177m gates
At 11nm – need 354m gates

R&D Engineers – do you know how design uses the EDA tools?

How to Follow Moores Law?
– Productivity tools, keep close to design engineers
– Get involved in sw productivity

EDA History
– Cadence as technology leader 1990 to 1997
– 2004 to 2007 Fister’s Folly as
– 2003 SNPS is #1 technology after Avant! Acquisition
– 2008 and 2009 SNPS as #1 tech leader
o Mentor and Magma still close in technology
o Who handles 22nm design? Large or small companies?

Summary
The mood at DAC this year is optimistic, there’s talk of hiring and people are eager for the Keynote address on Monday and the flurry of events planned. I’ll be blogging each day as I visit EDA vendors that offer transistor-level tools like: SPICE, DRC, LVS, 3d extraction, Custom IC layout tools, and more. On Tuesday I’ll be at the Panel Session on “3D Extraction: Coming to a Design Near You?“