Attendance at DAC is up across the board. Not surprisingly, with San Francisco being so close to silicon valley, the biggest increase was in people coming to see the exhibits.
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DAC Attendance up
Schematic, IC Layout, Clock and Timing Closure from ICScape
Before this DAC I had never even heard of ICScape, so on Monday and Wednesday I visited their booth to find out their story.
Steve Yang, Ph.D. (Co-founder and President), Ravi Ravikumar (Marketing)
ICScape was founded in 2005 in Santa Clara by Steve Yang (Circuit Design engineer for microprocessor, Synopsys) and Jason Xing (Sun Research Labs for EDA, Ph.D in Magnetics and Computer Science). Continue reading “Schematic, IC Layout, Clock and Timing Closure from ICScape”
Fast Monte Carlo and Analog Fast SPICE
Britto Vincent of ProPlus Design Solutions met with me at DAC on Monday morning to talk about Design For Yield (DFY) and Analog Fast SPICE.
In 2011 ProPlus announced DFY tools where the technology came from IBM, it provides fast Monte Carlo results up to 3 sigma, then added NanoSpice for faster simulation results. Similar in approach to Solido but with our own SPICE tool. High sigma analysis is useful in memory designs. Statistical simulation with yield analysis is accomplished using NanoYield. We had a joint presentation with IBM on Tuesday at DAC, IBM did a paper on Sunday too.
History of where ProPlus cam from – Started out as BTA, then Celestry, Cadence acquired Ultrasim, 2006 spun out from Cadence. We’ve been doing device modeling since 1991 (BTA).
In the Lab we can perform noise analysis.
Our own SPICE tool is called NanoSpice (like FineSim Pro). The simulator is both hierarchical and parallel. You can simulate a DRAM with up to 550M elements, or an SRAM with up to 65M elements.
The customers of NanoSpice cannot be mentioned yet, although we have a memory IDM and a southern CA client.
Device Modeling is done with the BSIMProPlus tool, and it is used by foundries and IDMs to create new models. This has been our core business.
NanoSpice is our Analog Fast SPICE circuit simulator and it can accept Spectre, HSPICE and Eldo format. The output is with FSDB so you can use a standard wave form viewer from companies like SpringSoft (Novas). Foundry qualification is in process now for NanoSpice.
For high sigma analysis our approach has been qualified with IBM (implied qualification with Common Platform).
We have offices in Japan, Shanghai, San Jose, Beijing and Taiwan.
NanoSpice is about 5X to 10X faster than HSPICE, Spectre, FineSim SPICE. Not a FastSPICE simulator and it’s similar to the BDA simulator. We are faster than Cadence APS. Co-simulation not supported yet, just pure SPICE netlist. We do support Verilog A.
We have about 100 people now and are privately funded.
12 months from now we expect more customer adoption in DFY and SPICE simulation.
How many languages an Engineer should speak?
I speak VHDL and SystemC, others speak Verilog and SystemVerilog … what do you speak?
Before getting into the core of the topic let me give you some round figures, engineers love numbers. Julian Lonsdale “European Sales Manager at Aldec” informed me at the Xfest Munich last month that Aldec carried out a survey to evaluate the usage of VHDL and Verilog among engineers in the States and Europe and the summary of the results is as follow:
Continue reading “How many languages an Engineer should speak?”
President Obama at DAC 2012
Okay, President Obama didn’t actually stop at DAC but he did do a drive by. I happened to be stepping out for some much needed fresh air and there goes his speeding motorcade. It was quite a sight actually, with all of the motorcycles, SUVs, a SWAT vehicle and even a paramedic rig (my son the Fireman drives one of those). The president was in town for dinner with donors at $5,000 per plate. And here I am in the DAC press room eating free food in plastic containers. The exciting life of an internationally recognized industry blogger.
This year DAC was extra special as my beautiful wife joined me for the fun and frolic including VIP tickets to the Denali party. Chatting with Wally Rhines is always fun in addition to the Who’s Who of the semiconductor ecosystem. A great time was had by all, believe it. Lots of interesting stuff is going on which I will blog about later.
Looking at the SemiWiki analytics 30 days prior to DAC I knew there would be a great turnout. The SemiWiki pre DAC blogs did very well with 36,150 people reading them, compared to last year’s 14,375 people. My guess was that attendance this year would be +20% over the last San Francisco DAC. (UPDATE: Conference attendees were up to 1901, up 9% on last year. But exhibits only passes were way up to 2783, an increase of 39%. Even booth staff was up 11% to 2704.). If attendance is up SemiWiki will take full credit due to the excellent coverage we provided. If not then never mind. The SemiWiki bloggers will post 20+ post DAC 2012 blogs in the coming days so stay tuned!
Next year DAC 2013 is in Austin Texas. My lovely wife and I will definitely attend as we have never been to Austin! My brother who works for Applied Materials lives there so we have a sub agenda as well. As you will see by the numbers below there is quite a market for EDA and IP in Texas. My prediction is that the SemiWiki DAC 2013 blog numbers are significantly higher next year.
Austin Activities:
Warehouse and Sixth Street Entertainment Districts– Four blocks of Fourth and Fifth Streets comprise the Warehouse District. The buildings have been renovated from warehouses to trendy, distinctive hot spots. Austin’s Sixth Street is widely known for its unique blend of dance clubs, live music venues, restaurants and bars.
SoCo– One of the hippest Austin hangouts is SoCo, a colorful stretch of Congress Avenue lined with funky shops, trendy dining spots, unique accommodations, art galleries and music venues. On the first Thursday of each month, (June 6, 2013) merchants keep their doors open until 10 p.m., playing host to an array of events and activities.
South of the Congress Avenue Bridge
Music Scene
Ever wonder why Austin is known as the Live Music Capital of the World®? The slogan became official in 1991, after it was discovered that Austin had more live music venues per capita than anywhere else in the nation. Today, Austin, TX hosts nearly 200 venues and is home to thousands of musicians. Which means you can catch a show any day of the week, at almost any time.
Major Employers of Design Engineers in Austin
[TABLE] style=”width: 400px”
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- 3M Co. (1000)
- Advanced Micro Devices (2933)
- Agere,Inc.
- Alereon
- Analog Devices
- Aperian
- Apple (3000)
- Applied Materials (2250)
- Applied Micro
- Applied Science Fiction
- ASI (Advanced System Integration)
- BAE Systems (675)
- Cirrus Logic
- Cisco Systems (800)
- Cypress
- DuPont Photomasks Inc.
- Flextronics (1875)
- Freescale Semiconductor (5000)
- Hewlett-Packard (550)
- IBM Corp. (6239)
- Image Microsystems (500)
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- Intel Corp. (1000)
- Motorola
- National Instruments (2200)
- Oracle (515)
- Photronics
- PulsewaveRF
- Qualcomm
- Rocket Chips
- Samsung (1100)
- SGI
- Silicon Group Inc., The
- Silicon Hills Design Inc.
- Silicon Laboratories (500)
- SMSC
- Spansion (900)
- Stellar Micro Devices
- TI (Dallas)
- Tokyo Electron America Inc.
- Vitesse Semiconductor
- WindRiver Systems
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DAC has drawn attendees from the following companies located
in the Austin area for over 50 years[TABLE] style=”width: 400px”
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- Advanced Micro Devices (AMD)
- Agilent Technologies
- Applied Micro
- ARM
- ASSET InterTech
- Biotroniik/MSEI
- Broadcom
- Callidus Systems
- Catalyte IC Design
- Centaur Technology
- Cyclic Design
- DSM Silicon Solutions, LLC
- Fabtech
- Freescale
- Fujitsu Network Communications
- Futurewei Technologies
- HDL Dynamics
- Hewlett Packard
- HighIP Design Company
- Huawei
- IBM
- Intel
- InternetCAD.com, Inc.
- L-3 Communications MID
- LFoundry GmbH
- Logic Refinery, Inc.
- Low Power Design
- LSI
- Marvell
- Matricus, Inc.
- Maxim Integrated Product
- Microtune
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- Mimasic
- Motorola
- NASA
- National Instruments
- Nokia Inc
- Omnibase Logic
- ON Semiconductor
- Oracle
- PDF Solutions
- Perception Software
- Qualcomm
- Raytheon
- Samsung
- Saratoga Data Systems
- Signet Design Solutions, Inc.
- Silicon Laboratories
- SiliconAid Solutions
- SiliconXpress, Inc
- SMSC
- Solid Oak Technologies
- ST Microelectronic
- Standard Microsystems
- SystematIC Design
- TelNet Management
- Texas Instruments
- The Aerospace Corp.
- Triune Systems
- Verilab
- Vitesse
- Wipro Technologies
- XtremeESL Corporation
- Zarlink Semiconductor
- Zoran
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Partitioning Panel
I moderated a panel on partitioning today and I have to say that I learned some things. The panelists were Jonathan DeMent from IBM, Santosh Santosh from NVIDIA and Hao Nham of eSilicon. Considering the different types of designs being done their approach to partitioning and the reasons for doing so were very similar.
When you first think of partitioning a design, you think of the technical reasons for doing so. Tools today have a sweet spot of around 500K instances. Larger than that and the run times get prohibitively long and so the iteration from an update to RTL to completed physical design becomes too long. Plus designs naturally partition in a certain way depending on the bus structure, the floorplan and other aspects of the SoC itself.
What I hadn’t thought of was that the human aspects of the design team are just as important. The most obvious is geographical location. If you have a design team in, say, Bangalore then you want to give them ownership of some comprehensible part of the design. And for the technical reasons you can’t just take a large block and chop it in two since the constraints etc that are needed to put it all back together later don’t exist and aren’t well understood and the communication needed to close the design would be completely excessive.
Another major factor in partitioning is how stable that part of the design is. If you are putting a standard piece of IP onto the chip, such as a USB controller, then it isn’t going to change much and you can put it in a partition with other stable blocks and get that part of the design completed early. On the other hand, if you have part of a design that is in flux, you want to put it in its own partition so you are not constantly having to redo a large unchanging portion because it was mistakenly grouped with something volatile. Unstable partitions need more added uncommitted gates whereas stable parts can be squeezed down more.
The challenge to getting this right is that what is optimum for the chip area (do as flat as possible) is not optimal for the tools and the schedule (keep to the sweet spot) and especially may be suboptimal for the human dimension. Everyone seemed to have rules of thumb for doing this and EDA tools (such as floorplanning) only address the technical dimension.
Collaboration at 28nm, 20nm and 14nm
Wednesday morning I attended a panel discussion with: ARM, IBM, Cadence, GLOBALFOUNDRIES and Samsung.
The panelists all sang the same song of collaboration between EDA, IP and Foundry to enable 28nm, 20nm and even 14nm.
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Physical IP Not From ARM or Synopsys
ARM and Synopsys are well-known physical IP companies however at DAC today I met with a lesser-known company named DXCORR that has some unique offerings for cache, multi-port memory and standard cell kicker libraries. I met with:
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Belle Wei Receives Marie Pistilli Award and is Interviewed
Today at DAC Belle Wei received the Marie Pistilli Award, presented to her by Patrick Groeneveld the DAC chair (and flowers from DAC via Chi-Foon Chan, now co-ceo of Synopsys). She was then interviewed by Daya Nadamuni.
Her father was a military general in China and in 1949 in the revolution her family fled to Taiwan where she was born. She went to all-girl middle-school and high-school and girls were encouraged to excel in all subjects. Her family moved to the US around the time she graduated high school. Then she went to Berkeley for a physics degree, followed by a masters at Harvard in engineering. She came back to the bay area and worked for a couple of years before deciding she wanted to study more so she returned to Berkeley for a PhD in electrical engineering and, in particular, semiconductors.
When she joined San Jose state she was the first female faculty in the school of engineering in its 40 year history. She was even asked if she would be able to spend enough time at work or would she feel she needed to take care of her family (I think it was illegal to ask that even then). She says it has changed now and the environment is a lot more nurturing. However, she did admit that she had her baby before going to San Jose State and never had a second one.
She started a program to bring middle and high school students into contact with engineers. She got motivated to do this since she knew that although in Taiwan 24% of students study some branch of engineering (and 30% in China), in the US it is only 4.4%. So they expose young people to engineering curriculum early on. She is proud that of the 3000 students who have been through the program, 25% are women and 41% are Hispanic.
Last week it was announced that Dr Wei will be leaving San Jose State and is going to Chico State to be the Provost and the VP for Academic Affairs. Belle feels that although the top-tier schools that she attended (Berkeley, Harvard etc) get the brand-names, that schools like San Jose State and Chico State make the real different since they process so many more people in aggregate. This isn’t the place for the signalling theory of education, that the main advantage of going to a place like Harvard is to be able to say you went there, nothing to do with what they teach you, whereas at a school like San Jose State it is the other way round.
Of the 4000 or so colleges in the US, almost none of them are headed by engineers. And our political leadership, unlike those of other countries, are also notable for the lack of engineers and scientists (and, of course, the large number of lawyers).
Belle also started a program sending students overseas. With globalization there is a lot of action outside silicon valley. They have sent over 200 students in the last 8 years (fully sponsored by local companies) to Taiwan, China and India. When there they get to see the dynamism of their host country and absorb some of its culture. This is perhaps even more important in a school like Chico which is not as diverse as silicon valley where every other person you meet was born overseas.
DAC 2012 – Sunday Night Kick Off
I arrived to a sunny San Francisco this afternoon, checked into my hotel then visited Moscone Center to pick up my Independent Media credentials. On the walk over I passed by Yerba Buena Gardens.
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