DAC2025 SemiWiki 800x100

Synopsys Geared for Next Era’s Opportunity and Growth

Synopsys Geared for Next Era’s Opportunity and Growth
by Kalar Rajendiran on 01-11-2024 at 6:00 am

SassineGhazi

As semiconductor industry folks know, Synopsys is a behemoth of a company. At $5.84B in FY2023 revenue (FY Nov-Oct), approximately 20,000 employees and a market cap of about $74B, it leads the silicon-to-systems design solutions space within the industry. From humble beginnings in 1986 as a disruptive startup, the company has grown into a skyscraper of success, revolutionizing the industry through continual innovations and expanding its value to all stakeholders. Naturally, it is big news when Synopsys changes CEO after 37 years of stewardship by the founding CEO Aart de Geus. Aart and the Synopsys Board have entrusted the company with Sassine Ghazi to lead it successfully through the next era and beyond.

Prior to his CEO role, Sassine was President and COO, responsible for leading all business units, sales and customer success, strategic alliances, marketing and communications at Synopsys. On his first day as CEO of Synopsys, Sassine communicated his enthusiasm for the unprecedented opportunity ahead, in a memo to stakeholders. Those who read the memo would fall into two broad categories. Those within the first category are the ones who implicitly trust in the astute choice of Sassine as CEO. And those within the other category are the ones who would additionally want to explore the skyscraper’s foundation and understand its structural strength for the next era’s journey.

As Sassine’s memo stated, a paradigm shift is clearly underway to deliver on the era of pervasive intelligence and interconnectedness. Riding paradigm shifts to growth is nothing new to Synopsys.

Let’s first look at how Synopsys has successfully ridden past paradigm shifts to bring more value to the industry and grow the company. We will also look at additional innovations that the company is continually investing in to help it ride the next paradigm shift that is upon the industry. Together, this review should help highlight the foundational and structural strength of the company to scale efficiently and deliver ambitious and sustainable growth.

Leveraging Paradigm Shifts is Innate to Synopsys

The following are some major shifts that Synopsys has capitalized on to grow  the company and its value to stakeholders.

“HDL Design” paradigm shift

When gates level description and netlists were the mainstream approach for designing chips, Synopsys pioneered the HDL design approach through synthesis solutions. Synopsys disrupted the market with the first timing-driven logic synthesizer and soon after established itself as a formidable player in the design synthesis segment. From that beachhead, the company expanded its innovative solutions space to address more aspects of a chip design process. Fast-forward and Synopsys quickly grew to be a comprehensive EDA solutions company.

“IP-based Design” paradigm shift

As non-modular design approach started giving way to IP-based and modular design approach, the company started investing in IP DesignWare library. The library started with basic IP but soon expanded to include higher-level IP such as processor cores, security IP, interconnects and more. Soon after, Synopsys became a significant player in the third-party IP market segment. The company becomes an EDA+IP company from its prior classification as just an EDA company.

“Network is the Computer” paradigm shift

The famous tag line “Network is the Computer” is attributed to Sun Microsystems and reflected its vision of network-centric computing paradigm, emphasizing the importance of interconnected systems and network infrastructure. In this vision, the network is the critical component, enabling collaboration, data sharing, and distributed processing. Synopsys capitalized on this paradigm shift by innovating and delivering an extensive portfolio of interconnect IP solutions. The company also delivered security and software testing solutions and became known as the Silicon to Software company.

“Multi-die Systems” paradigm shift

As Moore’s law benefits started to slow down, system performance demands started increasing in leaps and bounds. It became clear that Multi-die systems are essential to address the system demands of modern day applications. Synopsys quickly capitalized on this shift by delivering innovative solutions such as its Fusion Design Platform™ which includes the 3DIC compiler.

Synopsys’ Silicon-to-Systems Approach

As reviewed above, the company has grown from its early roots as a design synthesis company into a silicon-to-systems design solutions company. The silicon-to-systems approach in semiconductor design represents a comprehensive and integrated methodology that encompasses the entire spectrum of designing electronic systems. It addresses everything starting from fundamental building blocks of silicon devices to complete system-level integration and unified design verification through the ZeBu Server 5 solution.

Next Paradigm Shift

In the realm of Artificial Intelligence (AI), an “AI network” encompasses various meanings depending on the context in which it is used. It commonly refers to neural networks for tasks like image recognition and machine learning. Alternatively, in the context of distributed computing, AI networks may denote cloud-based systems utilizing extensive computational resources for training and deploying AI models. The term can also extend to AI-powered networks in applications, such as social networks employing algorithms for content recommendation. Additionally, it may refer to collaborative AI networks where interconnected systems work together towards common objectives or in the domain of cybersecurity, where AI is applied for threat detection and network security enhancements. The multifaceted nature of “AI network” underscores its diverse applications across various technological domains.

I’d like to coin the tag line “AI Network is the Consumer” to denote the paradigm shift that the industry is facing now. The AI Network is the consumer, so to speak, driving new architectures, design methodologies, IP and silicon proliferation. The semiconductor industry is expected to double in market value to one trillion dollars or more by the end of the decade. A significant portion of this projected growth is being attributed to this paradigm shift.

Synopsys.ai

Synopsys is increasing its investments to address its silicon-to-systems approach with heightened focus on pioneering AI in chip design. Synopsys.ai is the company’s overarching AI initiative and most recently, the company launched Synopsys.ai Copilot. – you can read about both in this SemiWiki post.

Summary

Synopsys revolutionized the process of designing semiconductors and will continue to do so. This is part of the action-oriented company culture that Aart has inculcated into the company DNA. Sassine radiates this culture with several innovative solutions having been launched under his prior leadership roles. I can vouch for Sassine’s passion for collaboration and innovation based on a couple of dinner conversations with him on various topics in technology and innovation.

Looking forward to Sassine leading Synopsys to capitalize on the next paradigm shift, deliver innovative solutions, enhance value to all stakeholders and grow the company.

Also Read:

Automated Constraints Promotion Methodology for IP to Complex SoC Designs

UCIe InterOp Testchip Unleashes Growth of Open Chiplet Ecosystem

Synopsys.ai Ups the AI Ante with Copilot


An Accellera Functional Safety Update

An Accellera Functional Safety Update
by Bernard Murphy on 01-10-2024 at 10:00 am

Fusa interoperability min

In May of 2021 Accellera released a first white paper on the challenges they hope to address with their functional safety standard, together with the scope and goals they set for themselves. One major goal in this effort has been exchange and integration of functional safety data between different tools and flow and particularly between different layers of the supply chain, e.g. between IP, EDA and semiconductor suppliers. Another strongly related goal has between to ensure traceability of functional safety data for purposes of correctness, completeness, and consistency validation. More recently Accellera released a second white paper, informally describing their progress towards these goals.

Recap – why do we need a new standard?

The well-known ISO 26262 and IEC 61508 standards describe what needs to be accomplished to meet a defined level of safety but without much description of how it should be accomplished. This proves to require a significant effort in supply chains when building safe products depends critically on collaboration between different vendors in the supply chain.

The most obvious deficiency is the lack of a standard for exchanging FMEDA data (failure modes, effects, and diagnostic analysis). This data is central to understanding what failure modes have been considered and what level of coverage analysis and safety mitigations ensure against those failures. All of these are central to what an IP supplier promises, EDA tools measure, a semiconductor supplier commits to their customers and the Tier1/OEM need for their own safety analysis.

Lack of interoperability between these levels has forced supply chain players to depend on trust and natural language documentation to ensure compliance with expected requirements. Clearly a machine-interpretable standard would be superior for automated analysis. Alessandra Nardi, chair of the Accellera functional safety working group, tells me that the initial push to get a standard ratified has started with IP and semi vendors but she is expecting in time to get more feedback from Tier1s and OEM (particularly I would guess as they are also getting closer to semi design).

Goals for the second white paper

According to Alessandra, this white paper describes the approach the working group has taken to develop the data model, which becomes the foundation for the Accellera functional safety standard. This begins with formalizing the process of performing an FMEDA as a first step towards common understanding among the participants. In the second step they describe the resulting data model, reflecting the requirements of building an FMEDA. The final step will be to derive a language from the data model. This last step is currently only in sample draft in the annexes of the white paper and remains open for further development among the working group.

From my perspective the white paper is a necessarily lengthy but quite exhaustive description of requirements, between intra-layer interoperability (between different functions say in semiconductor design development) and inter-layer considerations (for example between IP and semiconductor layers). They describe in some detail the flow in developing an FMEDA and how failure modes, safety mechanisms and technology elements are mapped and connected in a representative design.

How close is this standard to release?

As mentioned above, the functional safety language is still in development though the white paper offers a sample language to illustrate how a tool or user might interact with the model. Alessandra sees the next steps as validating the data model with a wider audience (I assume, since this is now a public white paper) and finalizing the language into a language reference manual (LRM). She hopes to see that out some time in 2024.

You can read the detailed white paper HERE.


Analog Bits Enables the Migration to 3nm and Beyond

Analog Bits Enables the Migration to 3nm and Beyond
by Mike Gianfagna on 01-10-2024 at 6:00 am

Analog Bits Enables the Migration to 3nm and Beyond

The world is abuzz with 3nm and 2nm technology availability. These processes offer the opportunity to pack far more on a single die than ever before. The complex digital systems contemplated will bring new AI algorithms to life and much more. But there is another side of the technology migration story.  With all that digital processing comes the need for things like I/Os, sensing, power management and high-speed comms. These are functions delivered by analog IP, and all that must be available on advanced nodes to realize the true monolithic integration opportunity. Analog IP often doesn’t work well at advanced nodes, however. This is a story of how one company isn’t just solving the problem. It is expanding the options at 3nm and beyond to create new paths for new ideas. Read on to see how Analog Bits enables the migration to 3nm and beyond.

The March to 3nm

Analog Bits has a huge catalog of IP that enables all kinds of systems. Billions of units shipped across 1,000+ deliveries since 1995 – an impressive statistic.  The company has a long track record of developing critical analog IP across all the top foundries. A little less than two years ago the company was purchased by SEMIFIVE, but the focus and direction of Analog Bits remained the same. You can get more of the backstory on SemiWiki here.

The Analog Bits IP portfolio spans clocking, sensors, I/Os, and SerDes. In the sensor area, on-die LDOs help with power efficiency and power management, a vexing problem for advanced designs. Here is a top-level summary of the portfolio, there is a lot more detail available here.

Clocking

  • PCIe clock PHY IP
  • High performance C2C PLL
  • Digital Core Power PLL
  • Wide-range, low power PLL
  • Ultra low jitter LC PLL
  • Sub-micro watt IOT class PLL
  • High reliability radiation tolerant PLL

Sensors

  • Digital Core Power
  • Bandgap Generator
  • System Power Detector
  • PVT Sensor
  • Power on Reset with Brown-Out Detect
    • Power Glitch Detector
    • ADC
    • LDO

I/Os

  • Differential clock TX/RX
  • PCIe – HCSL clock drivers
  • C2C IO’s Single Ended IO
  • Low noise/power crystal oscillators
  • Lowest Power OSC pads for IoT
  • FPGA class multi-programmable IO
  • Voltage tolerant IO buffers
  • DDR IO’s

Multi-Rate, Multi-Protocol SERDES

  • Lowest power (4pj/bit @ Gen3 & 6pj/bit @ Gen4)
  • Low latency – 3/4 UI between parallel and serial Tx/Rx
  • Smallest area – 0.1 sq.mm (Gen3) & 0.26 sq.mm (Gen4)
  • Programmable for different channel environments

Of course, all this IP must be available on 3nm to facilitate the move to that node, and Analog Bits has a strong story here. The figure below drives home the point. Analog Bits is a critical enabler for 3nm designs.

Analog Bits Foundry Coverage

What’s Next

There is plenty more in the works at Analog Bits beyond 3nm. That detail will be part of future posts. There is one rather key point worth mentioning now, however.  Back in 2021, the company announced a novel new, patented IP architecture called Pinless Technology. To minimize power distribution overhead, IP was developed that worked off the core voltage of the chip. This means there is no longer a need to route a different voltage to internal IP since the core voltage is everywhere.

While this style of IP is very useful in 3nm, it takes on a different value at the next node. As we move below 3nm to gate-all-around architectures there will be only one gate oxide thickness available to support the core voltage of the chip. Other oxide thicknesses to support higher voltages are simply no longer available.

In this scenario, the Pinless Technology invented by Analog Bits will become even more critical to migrate below 3nm as all of the pinless IP will work directly from the core voltage. I can’t wait to see how the impact of this innovation shapes the future. And that’s how Analog Bits enables the migration to 3nm and beyond.


IEDM: What Comes After Silicon?

IEDM: What Comes After Silicon?
by Daniel Nenni on 01-09-2024 at 10:00 am

Screen Shot 2024 01 05 at 8.50.58 AM

The annual International Electron Devices Meeting (IEDM) took place last month. One of the presentations on the short course was by Matthew Metz of Intel titled New Materials Systems for Moore’s Law Continuation. In essence this was a look at some of the possibilities for what comes after silicon runs out of steam.

Matthew started with a look at how the transistor has changed the world and, in particular, the materials innovations that have driven Intel’s own process roadmap over the decades. Back at 90nm we had strained silicon, followed by HiK metal gate. Intel was the first to market with FinFET (although back then it called it TriGate). At Intel 4, EUV lithography was first introduced.

As you probably know, Intel is doing technology development of 5 processes in 4 years, which is obviously aggressive, but apparently is all still on track. Intel 20A will be the first process with gate-all-around (GAA) which Intel calls ribbonFET. Intel also has an aggressive advanced packaging roadmap, but I’m going to skip that since the focus of the talk was what are we going to put on the wafers in the future, not how we will put them together.

Intel is not alone in going for gate-all-around. Over the last couple of years at conferences like IEDM, all the major manufacturers and research organizations have published some version of nanosheet gate-all-around results. See the cross sections above.

The next big innovation planned is complementary FET or CFET, with n-transistors over p-transistors. In fact this was almost the theme of this year’s IEDM with many people announcing various innovations in the manufacture of CFET to get a 1.5X to 2X area scaling.

Another innovation that Intel is pursuing (along with everyone else) is backside power delivery network (backside PDN) along with what Intel calls PowerVia. These technologies allow for signals and power to be separated and no longer interfere with each other as has historically been the case, when all the interconnect was on the front side (well, the only side until recently).

The biggest challenge is the power wall. It is very difficult to get more than 100W per square centimeter of cooling. There are various possibilities as to how to improve things:

  1. Conventional MOSFET enhancements
  2. Strained silicon germanium (SiGe) nanoribbons
  3. Ge or InGaAs nanoribbons
  4. Tunnel FETs
  5. Dirac FETs (graphene and 2D)
  6. Negative capacitance NCFET
  7. In-memory compute with FerroTunnel Junction or FerroFET

There are a lot of attractions to doing 2D materials instead of sticking with 3D. But there are major challenges with finding good materials. I’m sure you’ve heard of carbon nanotubes (CNT) but despite the attraction there has been no real advance in the challenge of manufacturing these reliably for ten years. Graphene is 2D but has no bandgap making building switches a challenge. Phosphorene is volatile at high temperature making manufacturing a complete transistor impossible.

The most attractive solution seems to be development of transition metal dichalcogenides or TMD. I confess that this was the first time I’d heard of these, at least under this name. It is one of the more promising approaches using 2D materials. TMD are a single monolayer giving good gate-control so lower power. They have better mobility than silicon, so good performance. Also, a large bandgap so limited source-drain tunneling.

Matthew went into quite a lot of detail about the challenges and promises of manufacturing TMD 2-layer transistors, in particular growing 2D single layer transistors, and how to contact them. For contants to the n-transistor the most attractive materials seem to be antimony (Sb) and Bismuth (Bi). For the p-transistor, ruthenium (Ru).

The last section was a look at scaling down power requirements and advanced switching, in particular the magneto-electric spin-orbital (MESO) devices. Switching can be done at around 0.1V with corresponding power reduction.

Matthew’s conclusion is that work going on at Intel with TMD shows promise for continued CMOS scaling, and MESO devices have a lot of promise for drastic power reduction. But this is comparatively early research and there is a lot of work still to be done to make either of these technologies a practical reality.

Also Read:

2024 Big Race is TSMC N2 and Intel 18A

IEDM Buzz – Intel Previews New Vertical Transistor Scaling Innovation

Intel Ushers a New Era of Advanced Packaging with Glass Substrates


IEDM 2023 – Modeling 300mm Wafer Fab Carbon Emissions

IEDM 2023 – Modeling 300mm Wafer Fab Carbon Emissions
by Scotten Jones on 01-09-2024 at 6:00 am

Figure 1

For the first time ever, IEDM held a sustainability session at the 2023 conference. I was one of the authors who presented an invited paper, the following is a summary of my presentation.

Call to Action

From the United Nations [1]:

“Climate Change is the defining issue of our time, and we are at a defining moment.”

“Without drastic action today, adapting to these impacts in the future will be more difficult and costly.”

There are some basic well-established scientific links:

  • The concentration of Greenhouse Gases (GHGs) in the earth’s atmosphere is directly linked to the average global temperature on Earth.
  • The concentration has been rising steadily, and mean global temperatures along with it, since the time of the Industrial Revolution.
Two Part Problem

We view reducing GHG emissions as a two-part problem:

  1. Design future processes and technologies to reduce carbon emissions.
  2. But… we also need to reduce carbon emissions from existing facilities and processes.

Detailed modeling of carbon emissions is needed to understand both future process challenges and how to address existing processes/facilities.

Carbon Model

The Carbon Model described here is based on the former IC Knowledge Strategic Cost and Price Model that has been widely used in the industry since 2010. The Strategic Model is well vetted at this point. TechInsights acquired IC Knowledge in November 2022.

The Strategic Model – models 3D NAND, DRAM and Logic with coverage of the earliest processes on 300mm out to future processes. Currently the model covers 167 – 300mm fabs and 220 company specific process flows.

The model calculates detailed equipment sets with electric, water and natural gas requirements. Detailed materials consumptions by material type are also calculated.

The model is fab based! This is a key point when it comes to calibration and validation. There is a variety of GHG emissions data available, in some cases by company fab site, in some cases by country for a company, and in some cases for the whole company. The ability to model the fabs that make up a site, or all the fabs a company has in a country, or all the fabs a company has enables calibration and validation.

The Carbon Model is currently 300mm only although we are investigating adding additional wafer sizes. According to SEMI – 300mm represents roughly 70% of the worldwide millions of squares inches of silicon shipped in 2023.

The Carbon Model covers: GLOBALFOUNDRIES, Intel, Kioxia, Micron Technology, SK Hynix, Samsung, TSMC, and YMTC. These eight companies represent approximately 77% of worldwide 300mm wafer fab capacity [2]. We are investigating expanding the model coverage to all 300mm fabs.

In terms of GHG emissions the Carbon Model covers scope 1 emissions from on-site combustion of fossil fuels and process chemicals, and scope 2 emissions from purchased electricity (in a few cases electricity is generated on-site becoming a scope 1 emission).

Electricity Modeling

Some semiconductor companies are claiming they have no scope 2 electric emissions because they are using “100% renewable energy”. There are two problems with this.

  1. Renewable energy includes burning biomass that while considered renewable is not carbon free. This is not a significant part of electricity production in the countries we are interested in at this time, but back in 2015 Ireland produce >12% of their electric supply from burning peat [3].
  2. The far larger problem is that according to Greenpeace, in 2021, 84% of “Renewable Energy” in the semiconductor industry was from Renewable Energy Certificates (RECs) [4]. RECs are financial instruments that represent existing renewable energy projects. The purchase of RECs does not add any new renewable energy to the grid. For this reason, RECs are one of the least impactful forms of renewable energy procurement.

It is the modeling policy of TechInsights to not consider RECs and to model carbon emissions based on the carbon intensity of the electric supply. This is estimated by country except for US based fabs where we estimate it by state. We do account for carbon free electricity if generated on-site or through a purchase power agreement if we can identify it. That is an area of ongoing research for us.

The past, present and projected carbon intensity by country we use in our modeling is illustrated in figure 1.

Figure 1. Carbon Intensity of Electricity by Country.

The solid lines are from Our World in Data and the dotted line projections are by applying an IEA projection by region that is no longer available on their web site.

In order to apply the carbon intensity, we need to first estimate the amount of electricity used by the fab. Because the Carbon Model does detailed equipment set modeling, we begin by applying electric usage by piece of equipment [5],[6],[7],[8]. EUV equipment gets particular attention due to the large effect dose has on throughput and therefore electric usage. Facility electric usage is estimated based on process and facility characteristics. Figure 2 illustrates electricity usage by logic node.

Figure 2. Electricity Usage by Logic Node.

In figure 2 the grey bars are facility electric usage, the blue bars are equipment electric usage not including EUV, the orange bars are 0.33NA EUV systems and the yellow-orange bars are 0.55NA (high NA) EUV system electric usage. The dotted line is the percentage of electric usage that is due to equipment.

There are three interesting aspects of the figure I want to highlight:

  1. The logic nodes in figure 2 are based on TSMC. At 7nm TSMC introduced an optical based process (7nm) and then an EUV based process (7nm+). Even though EUV equipment uses considerably more electricity than DUV systems, EUV replaces complex multi-patterning steps with a single exposure and results in a net reduction in electricity usage.
  2. At the 14A node we compared 0.33NA EUV that will require EUV multipatterning to 14A+ with High NA EUV eliminating multi-patterning and once again there is a net reduction in electricity usage.
  3. The dotted line shows that from 130nm to 40nm the equipment represented approximately 43% of total electric usage consistent with a SEMATECH study. Prior to EUV entering usage we found equipment represented 40% to 50% and then once EUV entered use equipment represent between 50% and 55% of total electricity consumption.

We have compared our modeled electricity usage to electric usage data for two companies – companywide (GF and SK Hynix), TSMC for Taiwan, and Intel for 4 sites and the match is excellent except for Intel Oregon where we believe we are underestimating the site activity level. Intel Oregon is a development site and we have recently received new data that is consistent with more activity there than we used in these calculations. Overall, it gives us confidence in the calculation.

Combustion

On site combustion of fossil fuels is for five applications:

  1. On-site electric generation (a few fabs do this with natural gas).
  2. Facility heat.
  3. Preheat water prior to reverse osmosis. Reverse osmosis is a key step in ultrapure water generation and the percentage of good water compared to reject water from reverse osmosis is higher if the water is warm.
  4. Some abatement systems – natural gas is used in some systems to burn perfluorinated compounds to destroy them.
  5. Heat and reheat, of makeup air. Wafer fabs have exhaust air to remove chemical fumes from equipment and air must be brought in from outside the facility to “make up” for the exhaust air. During cold weather the air must be heated to room temperature and humidified for static control and photoresist performance. During hot weather the makeup air is cooled below room temperature to dehumidify the air and then reheated to room temperature.
Process Chemicals

Figure 3 illustrates the flow of process gases through the process equipment and into the atmosphere with the conversion to equivalent carbon values.

Figure 3. Process Chemical Emissions.

From figure 3:

  • Process chemicals enter the process chamber where some percentages are utilized either by being broken apart in an etch reaction or becoming part of a film in a deposition reaction. The initial input volume multiplied by 1-utilization is the amount of process chemicals in the exhaust.
  • The process chamber exhaust may enter an abatement system where some portion of the process chemical is either broken down into non greenhouse gas chemicals or is absorbed into some medium. The chemicals exiting the abatement system is the input from the chamber exhaust multiplied by 1-abatement.
  • Finally, the Global Warming Potential (GWP) is applied to convert the process chemical to carbon dioxide equivalents. Basically, the lifetime of the chemical and how much heat the chemical reflects back are combined to compare the effect of one gram of the chemical to one gram of carbon dioxide.

Figure 4 presents, utilization, abatement and GWP values for the chemicals of interest for wafer fabs.

Figure 4. Process Chemical Emissions Factors.

 The utilization and abatement factors in figure 4 primarily come from the IPCC 2019 Refinement [9]. The GWP values are primarily from the IPCC AR5 [10].

The overall impact column in figure 4 is the 1-utilization values multiplied by the 1-abatement values multiplied by the GWP. This gives an overall picture of the impact of a chemical. Chemicals that have high overall impact are generally ones with high GWP values, however N2O has a relatively high impact despite a relatively low GWP. Most N2O is used for low temperature oxide-based film deposition with very low utilization [8] and the abatement is also relatively low.

Interestingly although the IPCC abatement values are generally over ninety percent, in the United States large greenhouse gas emitters must report their abatement efficiencies to the EPA and reported abatement values are much lower. Figure 5 illustrates reported abatement efficiencies for fabs sites in the US covered in the carbon model.

Figure 5. Reported Abatement Values for US Based Leading Edge 300mm Fabs.

It should be noted that the EPA reporting rules can result in reported abatement values that are less than actual abatement, but I would also note that when we model these fabs using the reported abatement values we get emissions consistent with what they report for emissions, so I don’t think the abatement values are very far off. I would also note I believe that abatement values are higher for fabs in some other countries and worldwide for the fabs covered in the carbon model I believe the average abatement is around 70%.

Model Validation

As was discussed in the Carbon Model section, the ability to model individual fabs can be used to compare the model calculated emissions to actual reported emissions.

In figure 6 EPA site emissions data from 4 sites representing 3 companies and 15 total fabs was added together and compared to modeled data for those same fabs.

Figure 6. Model Validation based on EPA Data for US Sites.

 As can be seen from figure 6, the match by category is excellent. It should be noted that the match for the 4 sites in total is better than the match by individuals site.

The sites in figure 6 represent logic processes from 28nm down to 4nm.

In figure 7 the model is validated against total GHG emission by site, country or company.

Figure 7. Model Validation Against Company Reports.

In figure 7, Micron Singapore represents 3D NAND Fabs, Micron Japan and Taiwan are DRAM fabs, TSMC Taiwan is logic fabs, SK Hynix Company is 3D NAND and DRAM fabs, and Kioxia Yokkaichi is 3D NAND. The reported data in this plot comes from company ESG reports.

Once again, the match is excellent.

Model Results

Logic transistor density continues to increase although at a slower rate in the past, this is achieved by increasingly complex processes in terms of number of process steps and mask layers. 3D NAND bit density is increasing driven by increasing layers counts resulting in taller memory stack requiring more deposition and etching chemicals. DRAM bit density is also increasing although once again more slowly than in the past driven by increasing process steps and mask layers.

Figure 8 presents modeled emissions for logic, 3D NAND, and DRAM by “node”.

Figure 8. Modeled Emissions.

In figure 8, the logic emissions are presented for TSMC type logic processes run in Taiwan with 2023 Taiwan electric carbon footprint and 70% abatement efficiency. The 3D NAND and DRAM values presented are for Samsung processes run in South Korea with 2023 South Korea electric carbon footprint and 70% abatement.

For logic the biggest contributor is scope 2 electric carbon emissions, it should be noted that Taiwan has the highest carbon footprint electricity of any country where leading edge 300mm fabs are located. For 3D NAND the growing layer count/stack height drives increasing scope 1 process chemical and scope 2 electric usage. For DRAM scope 2 electric emissions are the largest source of carbon emissions until a projected 3D DRAM process is introduced. The 3D DRAM process has a very tall memory stack requiring a lot of deposition and etch chemical usage.

There are multiple opportunities to dramatically reduce carbon emissions:

  • Scope 2 electric emissions can be reduced by switching to low carbon emissions electricity sources such as wind, nuclear, hydro, or solar.
  • Abatement systems with up to 99% abatement efficiency are available [11].
  • Lower carbon emission process chemistries can be substituted for existing higher emission chemistries. At the VLSI Technology conference this year Tokyo Electron disclosed a cryogenic etcher that can etch 3D NAND stacks with non GHG chemistries and higher etch rates. Also, chamber cleaning is typically done with SF6 or NF3 acting as fluorine delivery vehicles. Both gases have high GHG GWP values. In place of SF6 and NF3, F2 with a GWP of 0 or COF2 with a GWP of 1 can be substituted. It should be noted that even though these gases have 0 or 1 for a GWP they can combine with other species in the chamber to produce a high GWP molecule.

Figure 9 presents emissions in 2030 based on three scenarios each for a 10A logic process, a 1,000 layer 3D NAND process and a 80 layer 3D DRAM process.

Figure 9. Carbon Footprint 2030.

In each case the 2023 value is assuming 2023 electricity carbon footprint and 70% abatement with current process chemistries. The 2023 – likely scenario is based on the projected 2030 electricity carbon footprints from figure 1, 90% abatement and a new memory etch system/chemistry. Finally, 2030 – possible is based on 24g CO2 equivalent per kilowatt hour electricity (solar is 48, Hydro 24, wind and nuclear are 12 [5]).

Conclusion

The TechInsights Carbon model has been developed based on the former IC Knowledge Strategic Cost and Price Model. The carbon model enables detailed comparison of 300mm fabrication for leading-edge companies. Electric sources, combustion, and process chemicals with utilization, abatement, and GWP are all modeled. The carbon model includes extensive company specific data. The carbon model is currently available from TechInsights.

References

[1] https://www.un.org/en/global-issues/climate-change

[2] TechInsights 300mm Watch Database.

[3] https://www.seai.ie/data-and-insights/seai-statistics/key-statistics/electricity/

[4] Invisible Emissions: A forecast of tech supply chain emissions and electricity consumption by 2030,” Greenpeace.

[5] Bardon, et.al., “DTCO including Sustainability: Power-Performance-Area-Cost-Environmental score (PPACE) Analysis for Logic Technologies,” IEDM (2020).

[6] ASML 2022 annual report, page 83.

[7] Smeets, et.al., “0.33 NA EUV systems for High Volume Manufacturing,” SPIE (2022)

[8] TechInsights

[9] https://www.ipcc-nggip.iges.or.jp/public/2019rf/pdf/3_Volume3/19R_V3_Ch06_Electronics.pdf

[10] https://www.ipcc.ch/report/ar5/wg1/

[11] https://www.ebara.co.jp/en/products/details/FDS.html

Also Read:

SPIE 2023 Buzz – Siemens Aims to Break Down Innovation Barriers by Extending Design Technology Co-Optimization

Seven Silicon Catalyst Companies to Exhibit at CES, the Most Powerful Tech Event in the World

RISC-V Summit Buzz – Launchpad Showcase Highlights Smaller Company Innovation


Podcast EP202: A Tour of the Q3 2023 Electronic Design Market Data Report with Wally Rhines

Podcast EP202: A Tour of the Q3 2023 Electronic Design Market Data Report with Wally Rhines
by Daniel Nenni on 01-08-2024 at 10:00 am

Dan is joined by Wally Rhines for a discussion of the Q3 2023 Electronic Design Market Data report that was just released. SEMI and the Electronic System Design Alliance collect data from almost all of the EDA companies in the world and compile it by product category and region where the sales occurred. It’s the most reliable data for the EDA and IP industry and provides insight into what design tools and IP are in highest demand around the world.

In this broad and informative discussion, Wally details the results for the third quarter of 2023 for EDA and IP. It was a stellar quarter with industry revenue increasing 25.2% to $4,702.4 million from $3,756.3 million in the third quarter of 2022, Wally explained that this was the highest overall growth since Q4 1998. During the discussion, Wally does point out one area of the business that is slowing and one area of the world that delivered record-breaking growth.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


Keysight EDA Connect World Tour

Keysight EDA Connect World Tour
by Daniel Payne on 01-08-2024 at 6:00 am

RF System Explorer min

Video webinars are a main staple to learn what’s new about EDA tools and methodologies, but there’s nothing quite like meeting in person, where you can ask questions and gauge the expertise of the presenters. I was delighted to learn that Keysight is planning a literal world tour to update EDA customers and prospects on what they have to offer for IC groups doing high-speed, high-frequency and high-power designs. Technical experts from Keysight will be visiting over 20 cities starting January 16th in Paris, then finishing in Boston by May 16th, and there will even be customer presentations that vary by each region.

At the Keysight EDA Connect World Tour, you will hear about the exciting innovations and challenges in four industry mega-trends:

  • 5G/6G – Topics include how to meet the demand for higher accuracy, sensitivity, and bandwidth for 5G NR, and how to keep up with emerging new standards with 5G NTN (Non-Terrestrial Networks), 6G networks, and security.
  • Aerospace & Defense – Learn about the latest developments in satellite communications and how to manage interference for electronic warfare and radar systems.
  • Semiconductor – Amid supply chain disruptions and engineering shortage, the sessions will explore opportunities in new materials, silicon photonics, 3D IC, and co-packaged optics.
  • Consumer & Automotive – The sessions will cover new memory and interface standards like DDR5, PCIe 5.0, and HBM4. design for high-power, chiplets, miniaturization.

No matter your role in the IC world — from design engineer to R&D team leader — this World Tour has something valuable for you. The technical presentations focus on four key areas:

  • RF circuit designers working on MMICs for applications such as 5G/6G, automotive radars, Wi-Fi, and WiGig.
  • Digital designers who design and simulate the layout and performance of PCBs.
  • RF system designers creating RF transceiver systems in commercial wireless, A&D, and radar applications.
  • Device modeling engineers creating robust RF and GaN device models.

RF System Explorer with Spectrasys diagnostics, for advanced RF line-up capabilities

Some of the presentation topics include AI-driven design, chiplets, and 3D integration plus live product demonstrations of the newest features in the Keysight EDA tools. Locations and dates are listed below:

  • US: San Diego – Feb 7, Santa Clara – Feb 28-29, Austin – Apr 10, Dallas – Apr 11, Denver, Apr 25, Colorado Springs – Apr 24, Boston – May 6
  • Europe: Kista – invite only, Paris – Jan 16, Nijmegen – Jan 18, Toulouse – Jan 22, Catania – invite only, Rome – Jan 24
  • Asia Pacific: Penang – Mar 20, Singapore – Mar 22, Seoul – Mar 26, Tokyo – Apr
  • Greater China: Hsinchu – Mar 7, Beijing – Mar 19, Xi’an – Mar 21

Summary

Engineers on teams that are creating high-speed, high-frequency and high-power designs should consider attending one of these world tour cities to hear from Keysight and their customers with specific case studies. The in-person format will help get your questions answered by experts and bring you up to speed quickly. If you cannot attend in person, then there will be pre-recorded webinars that can be viewed later in the year.

The world tour is free, however you must be registered to ensure that there’s enough space.

For more details and online registration visit the Keysight EDA Connect World Tour site.

Related Blogs

Podcast EP201: A Retrospective of Semiconductor Innovation with Dr. Mukta Farooq, and Advice for Future Innovators

Podcast EP201: A Retrospective of Semiconductor Innovation with Dr. Mukta Farooq, and Advice for Future Innovators
by Daniel Nenni on 01-05-2024 at 10:00 am

Dan is joined by 2023 recipient of the J.J. Ebers award, Dr. Mukta Farooq. This is the highest technical award from the IEEE Electron Devices Society and Mukta is the first woman to earn this prestigious award.

Throughout her career Dr. Farooq has been a trailblazer. She was the first female to earn a Bachelors of Science in Metallurgical Engineering from the Indian Institute of Technology in Bombay. She earned her Masters at Northwestern University, followed by her PhD from Rensselaer Polytechnic Institute.

She joined IBM in 1988 where she is still working to advance the leading nodes of semiconductor technology. She is a world-recognized expert in heterogeneous integration of devices, copper TSV, 3D die-stacking, back end of line materials development, electronic packaging, and chip-package interaction, with an impressive 236 granted US patents.

Dan explores Mukta’s storied career of innovation for heterogeneous device integration. She details her early work and the motivation and strategies that drove her on a path less travelled as a woman in advanced semiconductor technology. The substantial innovations occurring at IBM are also discussed, along with a view of what’s next.

Mukta shares some excellent advice on how to follow your dreams as an innovator that will be quite valuable for all.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


Navigating the AI Horizon: Trends and Challenges in 2024

Navigating the AI Horizon: Trends and Challenges in 2024
by Ahmed Banafa on 01-05-2024 at 6:00 am

Navigating the AI Horizon Trends and Challenges in 2024

Stepping into the year 2024, the landscape of artificial intelligence (AI) continues to evolve at an unprecedented pace, presenting both exciting opportunities and formidable challenges. In this era of technological advancement, we find ourselves at the intersection of innovation and responsibility, where emerging trends in AI are reshaping industries and influencing the way we live and work.

As we explore the future of AI, several compelling trends come to the forefront, each poised to leave a significant impact on technology and society. These trends include the promises of Quantum AI, the infusion of AI into creative processes, the transformation of work through augmented capabilities, the evolution of multi-modal AI, and the increasing emphasis on ethical considerations.

Emerging Trends:
  • Quantum AI: Quantum computing promises to solve problems intractable for classical computers, enabling the development of more powerful and efficient AI models. Potential applications include drug discovery, materials science, and climate modeling. Requires significant hardware and software advancements.
  • AI-Enhanced Creativity: AI algorithms will assist humans in creative endeavors like art, design, and writing. Tools will generate new ideas, personalize experiences, and create unique artistic expressions. Raises concerns about artistic originality and ownership.
  • Augmented Working: AI will automate repetitive tasks, freeing humans for higher-order thinking and collaboration. Tools will support project management, decision-making, and communication. Requires careful planning to minimize job displacement and ensure a smooth transition.
  • Next-Generation Multi-Modal AI: AI models will understand and process diverse data modalities like text, images, and audio. This will lead to more natural and intuitive human-computer interactions. Requires advances in data fusion, representation learning, and multi-modal architectures.
  • Ethical Considerations: Increasing focus on ethical considerations like data privacy, algorithmic bias, and potential misuse. Development of guidelines and regulations for responsible AI development and deployment. Transparency and accountability are crucial for building trust in AI.
Challenges and Risks:
  • Data Bias and Fairness: AI models can amplify existing biases in data, leading to discriminatory outcomes. Techniques need to be developed for ensuring fairness and accountability in AI systems. Requires diverse training data and robust bias detection algorithms.
  • Explainability and Transparency: Understanding how AI models make decisions is often difficult, hindering trust and accountability. Methods need to be developed for explaining AI decisions in a human-understandable way. Interpretable AI models and explainable AI frameworks are crucial.
  • Job displacement: Automation by AI can lead to widespread job displacement, particularly in routine tasks. Strategies for retraining and reskilling workers are essential. Investing in education and lifelong learning programs is crucial.
  • Security and Privacy: AI systems are vulnerable to attacks that can compromise data privacy and security. Robust security measures need to be developed to protect against malicious use of AI. Secure hardware and software, along with cybersecurity awareness, are essential.
  • Global AI Governance: As AI adoption accelerates globally, coordinated efforts are needed for responsible development. International standards and regulations need to be established for ethical AI governance. Collaboration between governments, industry leaders, and researchers is key.
Navigating the Future:
  • Investing in AI education and training: Equipping individuals with the skills and knowledge needed to understand, develop, and utilize AI responsibly. Educational programs and training initiatives should be accessible to all.
  • Prioritizing ethical AI development: Establishing clear ethical guidelines and best practices for AI development and deployment. Ensuring transparency, accountability, and fairness in AI systems. Building public trust through responsible AI development.
  • Fostering collaboration: Addressing the challenges of AI requires collaboration between researchers, policymakers, industry leaders, and the public. Open dialogue and information sharing are essential. Fostering an inclusive and collaborative AI ecosystem is crucial.
  • Promoting open-source AI: Open-source platforms can accelerate AI progress and ensure transparency and accessibility. Sharing knowledge and resources can benefit the entire AI community. Building open-source AI repositories and tools is important.
  • Investing in AI research: Continued research and development are essential for pushing the boundaries of AI and unlocking its full potential. Funding for basic and applied AI research is crucial. Supporting diverse research teams and promoting international collaboration is important.

By embracing emerging trends and addressing potential challenges, we can leverage AI for a better future. Building a responsible, ethical, and inclusive AI ecosystem is essential for ensuring that this powerful technology benefits all. As we navigate the AI horizon, let us strive to create a future where AI empowers humanity and builds a more equitable and sustainable world for all.

Ahmed Banafa’s books

Covering: AI, IoT, Blockchain and Quantum Computing

Also Read:

AI and Machine Unlearning: Navigating the Forgotten Path

The Era of Flying Cars is Coming Soon

AI and the Future of Work


2024 Outlook with Matt Burns of Samtec

2024 Outlook with Matt Burns of Samtec
by Daniel Nenni on 01-04-2024 at 6:00 am

Matt Burns Samtec

Matt develops go-to-market strategies for Samtec’s Silicon to Silicon solutions. Over the course of 20+ years, he has been a leader in design, technical sales and marketing in the telecommunications, medical and electronic components industries. It has been an honor working with Matt and his team for the last 3 years and I value his input, absolutely.

Tell us a little bit about yourself and your company.

Samtec designs and manufactures high-performance interconnect solutions including copper connectors and cable assemblies, RF connectors and cable assemblies, and a growing portfolio of embedded optical transceivers. Currently, I lead a highly experienced team of marketing and technical professionals evangelizing Samtec’s high-performance interconnect solutions and services.

What was the most exciting high point of 2023 for your company?

You’d think that would be an easy question to answer, but I think that we survived 2023 was the highlight. I find joy when we can provide our customers and partners the right interconnect solution for their specific challenge. AI HW system architectures are evolving quickly. I am sure SemiWiki.com readers see that at the chiplet, substrate or package level. At Samtec, we see that at the system level. Density, higher speeds and flexible, scalable interconnects are a must. In 2023, we were able to deliver new solutions for several application-specific AI implementations. As we move in to 2024, we are challenged to develop new solutions for the next gen of AI systems. We can’t wait!

What was the biggest challenge your company faced in 2023?

Surviving. There were a lot of headwinds in 2023. Supply chains obviously normalized post-pandemic. Inflation seems to be coming under control. Global conflicts seem to be on the rise, so that can disrupt business cycles. There are many more.

How is your company’s work addressing this biggest challenge?

Samtec is very flexible and nimble. We can respond to challenges, whatever they may be, pretty quickly. Our focus is always on the customer. It’s a culture deeply ingrained in our ethos of find a solution to challenges our customers and partners face. As we continually execute to answer those challenges, long term relationships and trust are formed. Obviously, we are not immune to business cycles. However, our laser focus on serving the customer over the long term is always a winning strategy.

What do you think the biggest growth area for 2024 will be, and why?

I can’t predict the future, but I wouldn’t be surprised if AI from the data center to the intelligent edge continues to provide new opportunities. The release of ChatGPT was obviously an inflection point. LLMs and related AI applications are going to grow in complexity. The need for more computing is not going to slow down. New AI chipsets are emerging. Linking those chipsets is what we do best.

How is your company’s work addressing this growth?

It’s all about getting data from Point A to Point B as quickly and as reliably as possible. We are introducing our expanded 224 Gbps PAM4 product portfolio at the upcoming DesignCon 2024 trade show. Our 112 Gbps PAM4 solutions are still being designed into new products. We see new applications for our embedded optical transceivers, even in the data center. Our expanding 18-110 GHz RF cable, cable assembly and connector portfolio target semiconductor development and test applications as well.

What conferences did you attend in 2023 and how was the traffic?

Coming out of the pandemic, I was curious to see if engineers really wanted to live in a virtual or digital world most of the time. I was blown away at how many attendees we saw at our trade shows and conference around the world. North America and EMEA lead the way in 2022. We started seeing the same trends with growing attendance in APAC events in 2H23. Engineers want to see new technology. They want to interact with the thought leaders and technologists that make it happen. Trade shows and conferences are essential for this. So we added a few events to our trade show schedule in 2023. Key annual events for Samtec include DesignCon, OFC, embedded world, the global PCI-SIG DevCons, IMS, ECOC, OCP, SuperComputing, and the AI Hardware and Edge AI Summits among others.

Will you attend conferences in 2024? Same or more?

In general, we will be at the same amount of conference or tradeshows in 2024. Going into the new year, we see some US-based shows like the AI Hardware and Edge AI Summit going to Europe. embedded world 2024 is coming to Austin in October 2024. electronica is always a big deal in Munich. We take advantage of those and more.

Additional questions or final comments?

Its always a pleasure talking with the SemiWiki.com team Thank you for your hard work keeping the semiconductor and interconnect industries updated and informed so thoroughly.

Thank you for kicking off this series of interviews Matt. I look forward to seeing you at DesignCon..
Also Read:

Samtec Welcomes You to the Future with Proven 224G PAM4 Interconnect Solutions

Samtec Increases Signal Density Again with Analog Over Array™

Samtec Innovates a New Approach for High-Frequency Analog Signal Propagation