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20nm IC production needs more than a ready Foundry

20nm IC production needs more than a ready Foundry
by Pawan Fangaria on 08-23-2013 at 11:00 am
Categories: Arm, Cadence, EDA, TSMC

I think by now all of us know, or have heard about 20nm process node, its PPA (Power, Performance, Area) advantages and challenges (complexity of high design size and density, heterogeneity, variability, stress, lithography complexities, LDEs and so on). I’m not going to get into the details of these challenges, but will ponder on the flows and methods which can overcome these and can generally be available for a larger design community for mass production of ICs at 20nm; of course, based on the rules and regulations laid down by foundries. If anyone wants to refer to details of these challenges, she/he can refer to an earlier paper published by Cadencehere.

Sometime in Jun/July this year, it was reported by TSMCthat their risk production of 20nm chips has already started and volume production will start by Dec this year or early next year. It is known that Apple(for its A8 processors), its first customer is already lined up, more may join the queue. It must be noted that in last quarter of 2012 TSMC also announced support of double patterning technology and multi-die integration and corresponding reference flows for 20nm process node.

For proliferation of this technology into mass production by leveraging the sea of design houses, EDA vendors must provide the complete holistic solutions to overcome these challenges rather than point tools. At 20nm, that need becomes more prominent because it changes the paradigm in the context of double patterning complexities, variability and interdependence between design phases and manufacturing. The designers can no longer wait to fix problems until layout sign-off, everything has to be done in parallel at each stage.


[Challenges and requirements for 20nm IC design]

As we see, tackling these issues in the design is not enough, the design closer needs to happen in time and with desired PPA in order to avail the window of opportunity in the market. Having earlier worked at Cadence, I can firmly say that this is one company which provides a complete end-to-end solution to the overall design flow, with the whole spectrum of EDA tools for all types of designs; custom, digital, mixed-signal and so on. This company has the right expertise, through its long tenure in semiconductor EDA domain, to address designers’ need at all levels. For example, analog design needs more customized approach whereas digital design has very high level of automation.


[Cadence GigaFlex technology – A flexible modelling approach to manage large designs]

Cadence proposes rapid prototyping and rapid verification methodologies to save significant amount of design time. It uses flexible modelling to support required level of abstraction at each stage. For example, the model at design exploration or planning stage does not require details of that used at block implementation level. Further, it uses an innovative “Prevent, Analyze and Optimize” approach which drives both custom and digital platforms to enable faster design convergence at advanced nodes. In-design sign-off is done at each stage such as placement, routing, lithography analysis, timing and signal integrity and so on by utilizing state-of-the-art sign-off quality tool engines. Also correct-by-construction approach is used at the design time by utilizing smart tools such as constraint-driven design, LDE-aware placement, color-aware P&R and in-design verification.


[Clock Concurrent Optimization combines timing-driven CTS with physical optimization]

Clock Concurrent Design Flow is a paradigm shift that makes Clock Tree Synthesis (CTS) timing window-driven rather than skew-driven, and merges it with physical optimization. This provides significant PPA optimization; 30% saving on power and area and 100MHz of chip performance improvement for a GHz design with ARM processors.

To conclude, there are several challenges to fetch the benefits of 20nm technology, but with right tools, methodologies and collaboration across semiconductor ecosystem, they can easily be achieved. There is a detailed whitepaper from Cadence on the methodologies to be used for 20nm designs, “A Call to Action: How 20nm will Change IC Design”. It’s worth looking at, I enjoyed reading it and jotted down a summary of that in this article. The paper also has other references on 20nm technology. Enjoy reading!!

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NoC adoption surge at Chinese chip maker

NoC adoption surge at Chinese chip maker
by Eric Esteve on 08-23-2013 at 9:55 am
Categories: Arteris, IP

The news from Arteris, Inc., announcing that “its interconnect fabric IP has been licensed and deployed in a majority of chips developed by China’s leading semiconductor companies for applications including consumer electronics, smartphones, and tablets,” is holding attention for several reasons. At first, because it’s a clear indication that the Network-on-Chip (NoC) has become an indispensable piece to design a System-on-Chip (SoC), although the commercial NoC is less than ten years old. The second point is that this news highlight Arteris supremacy on the interconnect fabric IP (the other NoC name), despite the desperate effort from one of Arteris competitor to limit this success story, even by using legal battle field instead of trying to develop a better competitive product. We, at Semiwiki, have already blogged several times about the NoC features and the benefits it bring when implemented into a SoC, like to reduce wire congestion and ease intra-chip communication. We also blog about this legal battle, and we have clearly expressed our opinion: trying to compensate a lack of innovation by going to the legal field without good reasons is…#%¤!!&, and even more!

Let’s concentrate on the fact that four of the top five Chinese chip maker addressing consumer, wireless and tablet market segment have integrated a commercial NoC. I remember from discussion I had with Kurt Schuler, VP of Marketing with Arteris, that he told me about the early phase of business development, when Arteris sales force was trying to design-in the NoC five or six years ago to the large SoC chip makers in Europe and USA: at that time, the real competition was with the internally designed solution. Everybody who has ever to fight with the NIH syndrome knows that it is even more difficult to displace an internal design. Quite often, you try to sell a product to the same people who have developed an identical solution, explaining that your product is better, so they just fell stupid. They know that, if you are successful, they may lose their jobs, or at least their credibility… not an easy story.

Which is remarkable with Chinese chip makers is how fast they came up to speed, competing with, by far, older companies able to capitalize on long established R&D teams and associated know-how. These start-ups had to move quickly, so they faster took the right decision: integrate an off-the-shelf product, validated in dozen of SoC design – and in production on billions of IC (we are talking about the consumer and wireless market). This remind me the emergence of GSM based cell phone in Scandinavia. Did you ever ask yourself why the very first GSM cell phone successful manufacturers were Ericsson (Sweden) and Nokia (Finland)? Just because during the long winter the earth is frozen, so implementing a wired phone network is very painful! Developing an Application Processor and managing the intra-chip communication is certainly a great challenge when you start from scratch, a good way to minimize this challenge is simply to implement a commercial NoC!

If you listen to Analyst, they say it differently, but the idea is the same: “We see a very dynamic market in China’s local integrated-circuit (IC) design market, with double digit year-over-year growth projected for 2013,” said Vincent Gu, Principal Analyst, Market Intelligence, with IHS iSuppli. Tools such as Arteris’ network-on-chip interconnect IP fabric enable these design firms to more effectively meet the growing demand for semiconductors in China at a lower cost point.” Based on the IHS iSuppli ranking of the top Chinese fabless semiconductor OEMs in terms of revenue, Arteris counts four of the top five OEMs as customers – Spreadtrum Communications, HiSilicon Technologies, RDA Technologies and Allwinner Technology. Just listen to Arteris’ customer feedback:

“Arteris has provided exceptional support to our teams, giving us the confidence to implement the FlexNoC solution in our critical Smartphone SoC platform,” said Li Shiqin, IC Design Manager at Rockchip.

“The Arteris FlexNoC commercial SoC interconnect fabric IP gives us the performance required by our customers,” said Ding Ran, chief technology officer of Allwinner Technology. “We have seen first-hand how the interconnect IP improves process flow and overall system performance.”

Let say that I completely agree with Charles Janac, saying: “Arteris has achieved significant market share in the China fabless semiconductor market by not only solving our customers’ design challenges, but also by enabling them to quickly adopt best-of-breed technologies and development practices,” said K. Charles Janac, President and CEO of Arteris. “The Arteris interconnect IP fabric technology is one of the most significant SoC cost reduction and productivity innovations of the current decade, based on technology results and market adoption.”

Eric Esteve from IPNEST

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Jasper: Negronis on tap

Jasper: Negronis on tap
by Paul McLellan on 08-22-2013 at 6:26 pm
Categories: EDA

Did you know that Jasper’s Corner Tap in San Francisco serves Negronis on tap? It’s true. They also have Hanky Panky on tap, which is a Negroni with the Campari replaced with Fernet (which everyone pronounces as Frenet despite it being…well…wrong). And here’s another thing you probably didn’t know: San Francisco itself accounts for over 25% of all US consumption of Fernet. My daughter is a bar manager, I learn all kinds of stuff.

Anyway, talking of Jasper (this has to be the worst segue I’ve ever written) I doubt that there will be Negronis on tap at the Jasper User Group meeting but I’m sure that they will have free beer and wine as usual at the cocktail reception on October 22nd. The Jasper User Group (JUG) will be on October 22nd and 23rd. So those will be JUG wines then. It will be in the Cypress Hotel in Cupertino where it has been for the last few years.

I can’t tell you who the keynote is going to be yet because it hasn’t finally been confirmed, but last year it was Intel. Yes, that would be the same Intel that never endorses EDA companies in any way shape or form. If you missed my blog on the history of formal verification at Intel last year then it is still around.

But one of the other presenters could be you. Well, you have to be a Jasper user, of course (or maybe from Intel) but as in previous years, JUG will consist mainly of Jasper’s customers talking about their own experiences rather than a lot of Jasper marketing Powerpoint. Presentations can be from 30 minutes to an hour long.

Topics of interest include:

  • designer-based verification
  • low-power verification
  • security
  • sequential equivalence checking
  • architecture validation
  • SoC integration
  • RTL development
  • property synthesis
  • post-silicon debug
  • verification IP
  • formal property verification

If you are interested in presenting, then contact Rob van Blommestein robvb@jasper-da.com. Proposals are due by September 21st and then the final presentations by October 18th.

New this year there are “birds of a feather” discussions during breakfast hosted by power users at 8.30-9.30am each morning. Session topics are:

  • proof grid
  • property synthesis
  • clock and reset setup and verification
  • IP-XACT
  • low power verification
  • AMBA Proofkit certification
  • Protocol verification
  • security path verification

Details on those Jasper Negronis here. More details about the Jasper User Group are here. Register for the Jasper User Group here.

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Innovation + Thoughtful Management = Productive Expansion

Innovation + Thoughtful Management = Productive Expansion
by Pawan Fangaria on 08-22-2013 at 12:00 pm
Categories: EDA

After looking at various aspects of this company, to sum up, I couldn’t find any better statement than this; thoughtful management here is actually leadership with passion which achieves tangible results. This reflects in the methodology of doing things in this company which has given it a place among top EDA companies in a span of 12+ years; amid so many macroeconomic uncertainties during that time. Of course, the CEO and the top management of the company have spent many more years in this industry and are well known. You must have guessed it right from the picture; I am talking about Atrenta, or better I should say, SPYGLASS!


[Dr. Ajoy K. Bose along with Sushil Gupta and his staff at the Ribbon cutting ceremony at Atrenta, Noida]

On this Monday, 19[SUP]th[/SUP] Aug, I attended the inauguration ceremony of Atrenta’s expanded new facility at Noida and had an opportunity to talk to Dr. Ajoy K. Bose, CEO of Atrenta. Seeing Atrenta’s success in the SoC Realization arena, I had certain queries, or rather some assumptions in my mind; those were cleared during my talk with Ajoy. From this conversation, one can easily make out that the above statement holds true.


[Sushil Gupta, V.P. and MD at Atrenta, Noida lighting the auspicious lamp]

The Conversation –

Q: Your Noida centre has grown to about 200 people, the largest R&D centre in this beautiful, world-class, spacious facility. Of course there would be several reasons to invest in Noida, but tell me one prominent, compelling reason to invest in India, Noida.

This goes back to my initial days in early 1990 when I Joined Cadence and got involved with their India operation which had about 20 people at that time. It was then that I learned about power of Indian engineering. We had a shortage of talent in EDA R&D at that time, and we found that the kind of expertise and competence Indian engineers possessed, their attitude, willingness to learn and do, software development skills, process adherence, quality consciousness etc. were the right fit for us. And that is continuing today. Now the second part – why Noida? That is because of grooming of people around this region into our domain since then and availability of fresh talent.


[Ajoy addressing the staff at a communications meeting]

Q: What are your major product developments in Noida?

At Noida we have our largest development centre; we have almost all of our products being developed here except a few. We have a team in Grenoble, France; they are experts in formal verification and power. Last year we acquired NextOp and they brought us a team in Shanghai that created an assertion-based verification solution. Recently, we have set up a team in Colombo, Sri Lanka too.

Q: Yes, I’d heard about your Sri Lanka initiative. That’s leading by example; I guess no other EDA company is there in Sri Lanka. So, what made you think of Sri Lanka?

There are couple of aspects – I knew some of the best brains and enthusiastic people from Sri Lanka in my career, those people were influencers. Then, the undergraduate courses in universities there are very strong in science and mathematics and the skills required in our kind of industry. And then, proximity of Sri Lanka with India, that plays a vital role in working of the two teams together; the two cultures also assimilate easily.

Q: Now coming towards business side; I see that there are about 350 employees and 200+ customers at Atrenta. So, I guess the employee to customer ratio is quite low?

Yes, but it should not be looked at from that ratio perspective. We have a sufficient number of people to serve our customers well. Field AEs are available where required. The number depends upon the nature of the product. For example, the RTL physical product requires more AEs than we do in other SpyGlass products. And then it depends on size of the business, and the state of maturity of the product too. It’s a time varying phenomenon; we have a flexible organization which is optimized as required.

Q: My other query is related to employees; I see that 75% of work population is in R&D. How do you compare this with the rest of the industry?

Yes, we are high on R&D. We invest in developing new products. We have about 10 products developed in-house and we have been successful in doing that.

Q: So, how do you see the revenue per employee?

We are quite profitable there; R&D costs are very much optimized. We are flexible here. Mature products need less new R&D while new product development requires more initial investment.

Q: That’s quite impressive business leadership. On the technical side, I see that your organization has 49 patents (23 granted, 26 pending). Are all of these productized well? What is the average lead time?

Yes, we have all of these innovations integrated into products; we consciously invest in that. Often, it takes about a year or even two to conceptualize an idea along with some partner customers and then the usual product life cycle takes place. So, it takes about 4 to 5 years to make a full-blown product.

Q: I see that your concentration is on SoC Realization at the RTL level. There are other companies also offering products in that space. So, what is your POD (Point of Differentiation)?

We provide the most complete coverage at the RTL level. These are not used as point tools, although they are best-in-class in their capabilities. We provide a complete solution; SPYGLASS is a complete sign-off platform at the RTL level.

Q: Considering the overall flow from RTL to GDS, are you also focusing on POP (Point of Parity)?

There we cover all aspects of the complete flow, from micro architecture creation to modelling the physical implementation, but we abstract all that to the RTL level. Our theme is to complete the major job at the RTL level and hence save cost in detailed chip design and manufacturing.

Q: SPYGLASS is one of the top EDA products. You must be putting conscious effort towards branding it?

Yes, in DAC 2012 we initiated a major promotion of this brand and the effort is continuing. People know us more by SPYGLASS than Atrenta!

This was a very nice conversation with Ajoy. To conclude on my views, I believe that this company has all that is needed by a top class, productively expanding company. That is, a strong and flexible organization, business leadership, technology leadership and IP leadership. With presence in 11 countries across the world, Atrenta is the largest privately held EDA Company.

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Web-based Circuit Design and Analysis

Web-based Circuit Design and Analysis
by Daniel Payne on 08-21-2013 at 11:27 am
Categories: EDA

Last month I blogged about CircuitLaband received some two dozen comments, so clearly there is keen interest in using web-based tools for electronic circuit design and using the cloud to save designs plus run simulations. Today I’m reporting on TINACloud, provided by a company called DesignSoft.
Continue reading “Web-based Circuit Design and Analysis”

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Who is One Step Above Colgate and One Below P&G?

Who is One Step Above Colgate and One Below P&G?
by Paul McLellan on 08-21-2013 at 1:13 am
Categories: Dassault Systemes, EDA

So who do you think is #31 on the list on Forbes list of the most innovative companies in the world? One place above Colgate and one place below Procter and Gamble. Your first thought is probably why am I asking this on a blog covering semiconductors and going on about toothpaste manufacturers. The answer is Dassault Systèmes. Perhaps more to the point they are listed at #3 in the software and programming category, and #10 amongst European companies.


There are not many companies in the semiconductor ecosystem on the list. I don’t know how the entries are handled but the level of innovation required in EDA, IP, foundry and fabless is unbelievable. I think some of the smaller companies get caught by the minimum market cap of $10B. ARM comes in at #5 on the list, and ASML at #77, two places above Apple (and two behind LVMH Moet Hennessy Louis Vuitton, this list makes for strange bedfellows). Just scraping onto the list at #99 is Mediatek. And if you are interested, Salesforce is #1. The complete list is here. It will be also published in the September 2nd edition on dead trees.

Dassault increased sales by 5% last year, a 5-year total return of 16.7% and the mysterious “innovation premium” of 35.5. The innovation premium is a measure of how much investors have bid up the stock price of a company above the value of its existing business based on expectations of future innovative results (new products, services and markets). In addition to a minimum market cap of $10B, members of the list must spend at least 2.5% of revenue on R&D and have seven years of public data.

As Forbes says:Most innovation rankings are popularity contests based on past performance or editorial whims. We set out to create something very different with the World’s Most Innovative Companies list, using the wisdom of the crowd. Our method relies on investors’ ability to identify firms they expect to be innovative now and in the future. Companies are ranked by their innovation premium: the difference between their market capitalization and a net present value of cash flows from existing businesses (based on a proprietary formula from HOLT/Credit Suisse). The difference between them is the bonus given by equity investors on the educated hunch that the company will continue to come up with profitable new growth.


Dassault were 40th on the list last year, so they have climbed 9 places to 31st this year. In the software area, only Salesforce and VMware are ahead of them. Citrix, Intuit and SAP are the other software companies that are behind them in the top 100 innovative companies.

As of May, when Forbes recorded the data, Dassault had a market cap of $14.22B (today it is close to $17B which probably means their innovation premium has risen too). They have just over 10,000 employees and annual sales of $2.68B. They are the leaders in the 3D design marketplace, the standard for both aerospace and automotive design. With the increasing electronic and semiconductor content they are also moving to start to tie that part of the process in with everything else. It probably hasn’t escaped your notice that both the Airbus 380 and the Boeing 787 had electrical issues.

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Test, The Forgotten Step-Child of Semiconductor Design

Test, The Forgotten Step-Child of Semiconductor Design
by Paul McLellan on 08-20-2013 at 7:56 pm
Categories: EDA, Siemens EDA

Somehow, when designing a chip it is synthesis and place & route that gets all the attention. But it is no good taping out perfect layout without also having away to test the silicon. Somehow, test just isn’t as glamorous.

On September 10-12th is the International Test Conference which, as usual, is at the Disneyland Hotel in Anaheim. I actually went to the conference once when I worked for Virtutech. One use for virtual platforms is making it easy to configure “hardware” and then test the software without actually having to go and find all the boards and cables that would be required to assemble that configuration together in the real world. One of our first customers, Ericsson, used our software in just this way, and reckoned it would take a week to get all the hardware in one place to configure each base station. And a few Disney princesses brighten up any business breakfast.

But ITC is not primarily about software testing, although that is one aspect since so many systems have a large software load. ITC is the world’s premier conference dedicated to the electronic test of devices, boards and systems, covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement.

As usual, Mentor has a big presence at ITC. Firstly, they are in booth 211 where you can find out about:

  • Hybrid TK/LBIST which combines both compression and logic BIST solutions
  • Cell-Aware test for automotive standards such as ISO 26262
  • Unique test solutions for ARM processors and embedded memory IP
  • 3D test for DRAM and logic
  • Hierarchical solutions for large design efficiency and core plug-and-play reuse
  • Automated IJTAG support for plug-and-play infrastructure and pattern generation
  • Layout-aware diagnosis solutions for understanding and identifying yield loss from test data

One of the big changes in test where Mentor seems to be taking the lead is making test aware of layout. In the past, IC test has largely used a stuck-at model which has performed amazingly well considering just what a bad representation it is of what typically goes wrong on an IC. By adding cell-aware and layout-aware diagnosis it is possible to get much better results. And by better, in the test world, that means more parts failing…on the tester as opposed to out in the real world. Mentor presented the technology in some detail at Sematech and I blogged about it here. Indeed, Mentor’s cell-aware ATPG was awarded the Semicon West “Best of the West” award, which is really the best of show award.


As a way to tempt you to take a look at this, I’ll recap that AMD did an experiment where they ran their normal manufacturing test for a part, then they took the chips that passed and ran them through Mentor’s cell-aware test. They got another 885 DPM failing. This is a huge number. If the chip ships 10M units, that is nearly 9000 systems that are not going to fail. Not all would necessarily make it out of the factory as failing systems, but it seems likely that some would. Everyone knows that the cost of a failure in the field is orders or magnitude more than detecting the failure earlier when it just means discarding a bad die.

There are also a number of presentations by Mentor’s customers.

  • Toshiba on hybrid ATPG compression and LBIST together sharing test logic
  • OnSemi on cell-aware test results in automotive
  • LSI on cell-aware test results
  • ASSET InterTech will have a demo and presentation in their booth showcasing interoperable IJTAG L/TAG flows

On Sunday, Mentor is running a tutorial on “Mixed-Signal DFT and BIST: Trends, Principles and Solutions.” Rumor has it that lots of people are signed up, so it is clearly a hot topic and likely to sell out.

ITC itself (and the exhibits) are September 10-12th, but there are tutorials on Sunday, and panels on Monday with a welcome reception in the evening.

Want to know more about Mentor at ITC, it is all here. Want to go to ITC, register here.

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iPhone Buyers Are Younger, Richer, And Better Educated Than Samsung Smartphone Buyers!

iPhone Buyers Are Younger, Richer, And Better Educated Than Samsung Smartphone Buyers!
by Daniel Nenni on 08-20-2013 at 5:00 pm
Categories: General

Business Insider does it again, I just love their charts and with this one I agree with the logic 100%. To me this is more about Samsung the company than Samsung products, Samsung really needs to grow up. The negative marketing, the intellectual property thefts, bribery scandals, product dumping, presidential pardons……. Is that what it really takes to be successful in the new world order?


Contrary to Samsung negative marketing, iPhone users are NOT dorks or old people who don’t know any better. The latest data from Consumer Intelligence Research Partners (CIRP) shows it is quite the opposite. According to its survey of smartphone buyers over the last twelve months, iPhone owners in the U.S. are younger, richer, and better educated than the people buying Samsung smartphones. They are much better looking than the average Samsung Galaxy customer too, take me for example!

Seriously, what does it say about a person who does business with a company like Samsung that behaves in such a fashion? Technology over morals? This is a conundrum for me as I shop for my birthday gift, a new 65” plasma TV. Samsung clearly has the best TVs out today in regards to technology and value. Do I take the moral high ground and pay more for an inferior TV? Probably not.

I’m also against mixed smartphone marriages. My entire family has iPhones and iPads and we are living in complete harmony. As I blogged before “Apple v. Samsung: Mixed Phone Marriages End in Divorce?”, I’m just waiting for the studies out of Helsinki that clearly show the majority of divorced families have different brand phones, it’s gonna happen, believe it. And it is not just about personal choice, it is all about communication and working together for the greater good of the family. It’s called family crowdsourcing. There is no way a working adult can master all of the capabilities of today’s smartphone and still have a life. The new software, apps, and hardware come too frequently. My wife and I probably only utilize 25% of our iPhone’s true potential. It would be much less but we have four kids to move us along.

I’m really looking forward to the Apple announcement on September 10[SUP]th[/SUP]. I have an iPhone 5 that I will probably keep and wait for the iPhone 6 but my family has iPhone 4s’s that will be traded in for the iPhone 5C in hopes of longer battery life. We are keeping our iPad2s, they are just perfect for what we use them for today and the battery life is just great.


I’m going to completely ignore the Samsung announcement on September 4[SUP]th[/SUP] which is timed to “take the wind out of Apple’s sails”. Seriously Samsung, grow up, stop stalking Apple and get a life! Just my opinion of course.

lang: en_US

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Why Every Smartphone OEM Want to Use Homemade GPU?

Why Every Smartphone OEM Want to Use Homemade GPU?
by Eric Esteve on 08-20-2013 at 9:17 am
Categories: Ceva, IP

Smartphone shipment explosion and continuous growth is attracting always more OEM and chip makers, this is not really surprising, as the wireless market can be identified as the faster growing, and larger electronic segment ever seen. On such a mass market, the real question is “how to differentiate?” Apple is unique; just trying to mimic an iPhone is certainly not the best way to success. Samsung benefit from an incredible vertical industrial power, starting from SC design and manufacturing (Nand Flash, Application Processor and more) and going up to the development of several dozen of new smartphone models –every year. We have seen that smartphone marketing is way different from the “old” PC marketing: communicating on the CPU MIPS power is not anymore the killer argument, neither the memory amount, OEM have to be creative, and try to hit customer expectations. Power consumption is certainly an important feature, but probably not very sexy as a sale argument, and certainly not immediately visible. What could be immediately seen by a potential customer when looking at various smartphones? Is it the device shape or the design? Yes, but in Semiwiki we talk about semiconductors, barely about design… The image lighting on the screen, and the associated semiconductor function, the Graphic Processing Unit (GPU), is certainly one of the key features immediately seen by the future buyer.

Imagine that all OEM uses the same GPU (integrated as an IP core into the Application Processor), then how will they differentiate? CEVA, the DSP IP core leader supplier, has developed a very interesting piece of S/W, the digital video stabilizer (DVS) software module for the CEVA-MM3000 imaging and vision platforms,bringing advanced imaging capabilities to next generation smartphones and mobile devices. Just take a look at the above picture, you can see various axis, linked to all the motion that any human being can do, even when he is trying to take a picture. Which is a problem in this case, as you would like this human being to stay absolutely unmoving. Unfortunately, this is not possible! Using CEVA DVS will allow correcting this behavior, it will also allow the OEM to differentiate, as DVS function is adaptable and allow various calibrations. You can see the main features of CEVA DVS, 4-axis motion correction, Rolling Shutter correction and scalability on the picture below:

The problem with previously designed DVS functions was the associated power consumption, estimated to be in the range of 1 Watt by CEVA. The company claim 35 mW power consumption associated with the DVS used with MM3000 imaging and vision DSP platform! If you want to check for the effectiveness of CEVA DVS, just take a look at the picture below, showing a comparison with Apple iPhone 5, HTC One X or Samsung Galaxy Note 2. Going to the YouTube link http://youtu.be/7YmXJLe_CZo will give you a better idea of the DVS quality.

Talking about DVS, it can be interesting to explore how it works. DVS is using various pre-optimized kernels:

  • Harris Corner/”GoodFeaturesToTrack”

    • Detecting features for tracking
  • KLT

    • Tracking the Optical features using optical flow
  • RANSAC

    • Estimating the camera motion model
  • Kalman

    • Smoothing the camera motion
  • Affine Transform

    • Correcting the distortions generated from the motion and rolling shutter

DVS also using automated frame management mechanisms. Once again, the important point is that an OEM can integrate in the Application Processor a CPU core (or should I say an ARM set of cores?), an internally designed (or externally sourced) GPU and MM3000 imaging platform and differentiate by using this programmable DVS, allowing an extremely low power consumption: 35 mW for a 1080p and 30 fps when implemented in 28nm. Every OEM wants to differentiate through the GPU? Every OEM can differentiate even more by using DVS and MM3000 from CEVA in conjunction with homemade GPU!

A company like CEVA enjoys more than 200 licensees and 300 licensing agreements signed to date, CEVA’s comprehensive customer base includes most of the world’s leading semiconductor and consumer electronics companies. Broadcom, Icom, Intel, Intersil, Marvell, Mediatek, Mindspeed, Mstar, NEC, NXP, PMC-Sierra, Renesas, Samsung, Sharp, Solomon Systech, Sony, Spreadtrum, ST-Ericsson, Sunplus, Toshiba and VIA Telecom all leverage CEVA’s industry-leading platform solutions and DSP cores.

Eric Esteve from IPNEST

lang: en_US

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No Mention of 14nm at the 2013 Intel Developer Forum?

No Mention of 14nm at the 2013 Intel Developer Forum?
by Daniel Nenni on 08-19-2013 at 5:00 pm
Categories: Foundries, Intel Foundry

Yes, I will be going to IDF again this year, even though it is the same day as the Apple new product announcement. As a born again Apple Fan that is really saying something but Intel has done a great job of motivating the fabless semiconductor ecosystem and I thank them for that.

Unfortunately, noticeably missing from the IDF presentation line-up is 14nm. The semiconductor equipment people continue to tell me that the 14nm move-in has been delayed a quarter or two. I will be investigating this further at IDF for sure, mostly at the 150+ company technology showcase since Intel does not control that information flow.

Also missing from the IDF technical line up are smartphone sessions. Tablets yes but smartphones no, which is telling. As I have mentioned before, making an SoC is a completely different thing than making microprocessors, which is why there has been a 12 month Atom lag in the past. If Intel is to have any chance in mobile that must change and I’m hoping to hear as much at IDF. No mention of Intel TV and wearable devices either. Intel missed the mobile high margin days so let’s hope they make it in time for TV and watches.

The keynotes are very much mobile though:

IDF 2013 represents the beginning of a new era for Intel, and indeed the entire computing industry. With the recent leadership transition now complete, Intel’s new CEO Brian Krzanich and President Renée James are well underway in resetting the course of the company with a clear emphasis on mobile computing leadership. Please join Brian and Renée to hear how this focus on all things mobile will energize the existing ecosystem of Intel hardware and software developers – as well as attract a new wave of developers. There has never been a better time to align with Intel as a company and on the most scalable, widely deployed and successful architecture of all time.

Tuesday, September 10 Mobilizing Intel
Brian Krzanich, Intel CEO, Renee James, Intel President

Wednesday, September 11 Innovate at the Speed of Mobility
Douglas Fisher, Vice President, General Manager, Software and Services Group
Kirk Skaugen, Senior Vice President, General Manager, PC Client Group
Dr. Hermann Eul, Vice President, General Manager, Mobile and Communications Group

Thursday, September 12 Seven billion futures, and you’re one of them
Dr. Genevieve Bell, Intel Fellow, Intel Labs, Director, Interaction and Experience Research

You can get the full IDF 2013 agenda HERE. IDF has been around since 1997 and is a staple technical conference for the PC industry. It will be interesting to see how many familiar faces I see this year as Intel penetrates the fabless semiconductor ecosystem through the foundry business. Last year I saw not one fabless person that I recognized, except for Paul McLellan. Nobody recognized me either, not one autograph or even a nasty look from one of the many Intel shills. This year should be different, absolutely!

Why am I so hard on Intel? Because I think technology monopolies are bad, they stifle innovation and seek to control markets that should not be controlled. It’s a Star Wars thing, may the force be with us!

Also Read: Intel Really is Delaying 14nm….

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