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October 3, 2014August 22, 2024

Key Collaboration to Enable Designs at Advanced Nodes

Key Collaboration to Enable Designs at Advanced Nodes
by Pawan Fangaria on 10-03-2014 at 10:00 pm
Categories: Cadence, EDA, Foundries, GlobalFoundries

In the semiconductor ecosystem, several partners (or better to say stakeholders) join together in the overall value chain to finally output the most coveted chip, err I should say SoC these days. It becomes really interesting when we start analyzing the real value added by each of them, none appears to be less. Well, then to whom can we give the trophy if we have one to offer? Okay, then ask a simple question, what’s it without which the design couldn’t have proceeded in the first place in real physical terms and you get the instant answer – it’s PDK. The Process Design Kits may be lesser known in the world of ESL and RTL, but ask a back-end designer and she will tell you can’t do without PDK no matter how powerful EDA tools you have, and it’s utmost important for your PDK to be of highest quality. But then the EDA tools need to drive into the design what PDK has in the most effective manner.

It was a very pleasant moment when I came across a DACpresentation offered by Maq Mannan of GLOBALFOUNDRIES. Although it was a recorded presentation, it was pleasure listening to Maq; it revived my old memories of Cadence. Maq is a veteran in PDK domain; he founded DSM Technologies (which dealt in PDK development automation systems) in late 1990 – early 2000 which got acquired by Cadenceand that formed the PDK group at Cadence headed by Maq. Now Maq is at GLOBALFOUNDRIES, leading and delivering the best PDKs which are of highest quality, flexible and easy-to-use, enabling GF’s leading edge process technologies into SoC designs.

Starting from say 130nm to 20nm and below, added with FinFETs, the number of design rules have increased tremendously (approximately doubled with each node change), and along with it increased number of operations with each rule in the same or higher proportion; multi-patterning added further major complexities. Designers cannot keep track of rules while working. Keeping these in mind, the PDKs from GF have in-built, easy-to-use methods for designers to carry out their work without any loss of productivity. Recently GF and Samsungpartnered for PDKs at 14nm (14LPP and 14LPE) which can go to both the fabs with same design rules, models, DRM etc. thus improving productivity. The 14LPE V1.0 PDK is already released. As the complexities have increased with rapidly advancing technologies, it’s essential for fabs and EDA vendors to collaborate and leverage their capabilities to keep the tools in sync with technology to drive the designs in best possible manner. GF has built strong collaboration with multiple EDA and IP partners. Let’s look at what’s cooking up between GF and Cadence.

GF has major collaboration with Cadence with most of their customers using Virtuoso and Cadence libraries which is very significant and critical to their success. The area is spread across from digital routers to device models, simulation, extraction and verification to DFM kits, and the entire infrastructure relating to those is covered into PDK.

Cadence introduced IPVS which provides in-memory verification (with real-time DRC on edits) of layout within the Virtuoso layout design environment eliminating time consuming StreamIn/Out which was earlier needed by Standalone PVS. This capability is very significant in boosting designers’ productivity. GF supports PVS decks for virtually all technology nodes. This is a capability close to my heart as I always aspired for it in Virtuoso while I managed the physical design part of Virtuoso at Cadence.

Read one my older article on this – 28nm Layout Needs Signoff Quality at Design Time.

At advanced nodes (28nm and below), layout dependent effects (LDE) becomes significant causing significant deviation in device characteristics from their normal behaviour. Cadence tools along with wide range of support in GF’s PDKs to take these effects into consideration provides a versatile layout aware design flow which enables LDE estimation at schematic, detects LDE problems in layout, checks against constraints provided by circuit designers and verifies using LVS the final extracted layout for both placement as well as interconnect effects.

GF also provides decomposition options which are very critical for customers at advanced nodes, a key requirement for multi-patterning.

The designs can be done in colored layers (M1_E1, M1_E2) which is appropriate for standard cells, colorless layer (M1) appropriate for p-cell design and P&R which can be decomposed later by specific tool in PDK or mixed (hybrid) way. GF offers all three methodologies at 20nm; designs can be done in any of these combinations. For 14nm, they are working with Samsung to align on a single approach.

GF provides complete modeling environment with versatile Spice model library containing MOSFETs (RVT, HVT, LVT, SRAM, EG, ZG) including any special memories and devices and Non_FETS (Resistors, Capacitors, Diodes, Fuse and others). Models for variation (MC, Mismatch, and Analog), aging (Reliability) and stress (DSL, STI, WPE etc.) are accounted for.

It’s a great presentation to go through and know about PDKs and Cadence – GF collaboration in more detail. It’s freely available here. Click the link against “Collaboration Key to Enablement at Advanced Nodes”.

GlobalFoundries and Samsung at ARM

GlobalFoundries and Samsung at ARM
by Paul McLellan on 10-03-2014 at 3:01 pm
Categories: Arm, Foundries, GlobalFoundries

It was back in April that GlobalFoundries and Samsung announced that GF would license Samsung’s 14nm process to run in their Fab8 in upstate New York. Since then there has not really been any news and of course those of us that follow the foundry industry wondered to what extent there was real substance to the agreement or if it was just a feel-good press release. Well, this week a lot of information was presented. It was at ARM TechCon this week. There was a panel with Kelvin Low of Samsung, Shubhankar Basu of GlobalFoundries and Wolfgang Helfricht of ARM. Kelvin went first and emphasized that this is true multisourcing with true 14nm compatibility and it covers both 14LPE (E stands for ‘early’, since it is the early access version of the process) and 14KPP (P stands for ‘plus’, apparently, since I guess ‘late’ wouldn’t sound good). The wafer demand is, of course, largely driven by mobile but also by high-end compute functions in server farms. 14nm helps to bridge the performance gap that exists due to the limited power budgets available. FinFETs are especially good at very low voltages, and lowering the voltage is always good since it is squared in the dynamic power equation. The two processes LPE and LPP have the same design rules for fast migration. LPP has more performance and even lower power. Kelvin claims that the process enables designs that are 10% smaller than “other foundries” (no prizes for guessing who that might be) due to aggressive gate pitch, smallest SRAM and innovative layout. There have been 30 test chip tapeouts since 2012, and multiple product tapeouts completed (the first last year). Shubhanker revealed that fab8 is on-track with 100% physical module spec matching demonstrated. Currently matches fin, gate, eSiGe, eSiP, RMG, MoL. There is steady progress on SRAM yield and volume ramp in 2015. Multiple product and testchips have taped out. PDKs are available. MPW shuttles are available. IP support, reference flows, tech files. Yes, you can do a design. Wolfgang, from the Artisan part of ARM, talked about the availability of standard cell and other libraries. At 14nm there are new sources of variation and ARM have Artisan Signoff Architect. There are also complex EM and IR limitations which are addressed with Artisan Power Grid Architect. There are multiple standard cell libraries:

SC10MCP with 10.5 tracks for 14LPP
SC9MCP with 9 tracks for 14LPP
SC9MC also with 9 tracks and fast availability for 14LPE.

All products support 0.7V, 0.8V and 0.9V operation. There are memories with multi-voltage peripheries. The 14LPP GPIO system is at 1.8V with a single programmable I/O cell, and compatibile with mobile DDR. High volume designs are in progress using these libraries. Serdes performance is in the 25GHz range. So there you have it. This is true multisource manufacturing. It covers 4 of the anticipated 7 fabs that will run a 14nm process (TSMC has the other 3 but it calls the process 16nm), two in Samsung Korea, Samsung Austin and GF in New York, so there is assurance of supply. The IP ecosystem is portable between all the fabs. See also GlobalFoundries Gets a 14nm Process
More articles by Paul McLellan…

October 3, 2014

A de-parallel universe for Windows 10

A de-parallel universe for Windows 10
by Don Dingee on 10-03-2014 at 7:00 am
Categories: Foundries, Intel Foundry, Mobile

It was CES 2011 when Steve Ballmer sweatered up and pitched the coming universe according to Microsoft, where the same Windows base would run on everything – PC, phone, tablet, and game console. Getting from that visionary statement to Windows 10 hasn’t been a smooth ride. Continue reading “A de-parallel universe for Windows 10”

October 2, 2014

ARM ♥ TSMC!

ARM ♥ TSMC!
by Daniel Nenni on 10-02-2014 at 4:00 pm
Categories: Arm, Foundries, IP, TSMC

This week is the 10[SUP]th[/SUP] annual ARM Technical Conference in Silicon Valley. In regards to size, content, and relevance, I believe ARM TechCon is the #1 event for the fabless semiconductor ecosystem for sure. I attended keynotes, sessions, and walked the hallways on Wednesday and Thursday. I wish I could write about everything I learned but I do have NDA issues with my day job and some of the information needs to be verified by other sources before I can post it.

There were Cadence and Synopsys logos all over the place. I saw Aldec, Apache, Ansys, Calypto, Carbon Design, Dorado, Doulos, and Mentor. And not just Mentor, but my favorite EDA CEO Wally Rhines was walking the conference floor as well. You will not find a more “in touch” EDA CEO than Wally. He doesn’t seem to age either so Mentor probably has some cryogenic projects going on up in Wilsonville.

The foundries were well represented by TSMC, GLOBALFOUNDRIES, STMicro, and Samsung. Wait, where was Intel Custom Foundry? Atmel had a very nice IoT exhibit as did Freescale. Xilinx had a great presence as I mentioned HERE. The IP companies were there in force: Arteris, CEVA, Kilopass, Memoir, Rambus, Silicon Image, Sonics, True Circuits, and a few others. All of the EDA and IP companies were announcing support for TSMC 10nm during the conference. Bottom line is that the fabless semiconductor ecosystem gets stronger every year and will continue to do so.

Also Read: TSMC Delivers First FinFET ARM Based SoC!

The big news for me is the ARM/TSMC 10nm roadmap because let’s face it, the majority of the fabless wafers being shipped today include ARM IP. TSMC transformed the semiconductor industry with the pure-play foundry business model and ARM transformed the microprocessor industry with the IP business model so it makes complete sense for these two industry superheroes to team up on 10nm. Notice that the TSMC event was on Monday and Tuesday of this week and ARM TechCon was Wednesday-Friday.

ARM and TSMC Unveil Roadmap for 64-bit ARM-based Processors on 10FinFET Process Technology

“TSMC has continuously been the lead foundry to introduce advanced process technology for ARM-based SoCs,” said Dr. Cliff Hou, TSMC vice president of R&D. “Together with ARM, we proved out in silicon the high performance and low power of the big.LITTLE architecture as implemented in 16FinFET. Given the successful adoption of our previous collaborative efforts, it makes sense that we continue this fruitful partnership with ARM in future 64-bit cores and 10FinFET.”

I talked to Cliff after the TSMC event on Tuesday about the aggressive 10nm schedule (risk production in Q4 2015). Remember, 20nm risk production was in Q4 2013 and 16nm risk production is happening now (Q4 2014). Never before have we seen such a rapid pace of process development. Intel of course shares credit as their “aggressive” marketing tactics motivated the mighty fabless semiconductor ecosystem like never before, ABSOLUTELY!

What’s Behind Carbon System Exchange – How Will it Scale?

What’s Behind Carbon System Exchange – How Will it Scale?
by Pawan Fangaria on 10-01-2014 at 4:00 pm
Categories: EDA

Earlier this year, when I was looking at Carbon’spast year performance which provided record breaking revenue with whopping jump in bookings, one thing was certain that Carbon Performance Analysis Kits (CPAKs) would drive major growth in future, not only for Carbon, but also for the semiconductor industry. It will initiate a new chapter in the semiconductor system design era where a pre-built virtual prototype can be customized with various IPs and interconnect according to a designer’s need and downloaded from the cloud for performance analysis and optimization of a complete SoC; the designer can be up and running the analysis on the virtual prototype within minutes of download. That’s the kind of productivity CPAKs were already providing to their existing users; now Carbon is going a step further by featuring these CPAKs in a new easily searchable web portal and enabling their partners to create and publish their own CPAKs there as well. Carbon System Exchange promises to make it much easier and faster to start getting value from CPAKs.

Before I delve into my conversation with Bill Neifert from Carbon Design Systems, on how this initiative will unleash the huge potential of system design among a larger semiconductor community across the world, let me provide a brief about the Carbon System Exchange portal. It’s a web based platform where designers can find pre-built virtual prototype systems containing IP (MCUs, Processors, Interconnect, etc.) and s/w from several vendors. They can search for the particular combination of components that most closely matches their design needs, download pre-built systems and even request customization of CPAKs. Once downloaded, the CPAKs can be easily modified or extended using Carbon’s SoC Designer Plus virtual prototype together with models from Carbon’s IP Exchangeweb portal, models of their own RTL compiled with Carbon Model Studio or SystemC models of their own creation. Then they can quickly run the system with accuracy and speed and optimize their SoC realistically within various resource constraints under different workloads.

This is a significant step for SoC design community and hence it prompted me to have a nice conversation with Bill on business model and future visibility on how this initiative can make virtual prototyping ubiquitous. Here is the conversation –

Q: Bill, Carbon System Exchange is a nice initiative like IP Exchange earlier. IP Exchange is very popular now with more than 5000 IPs turnover. How do you see the System Exchange scaling?

A: Actually, we came up with the idea for Carbon System Exchange based upon the success of CPAKs on Carbon IP Exchange. Since we first introduced CPAKs at DAC in 2013 we’ve experienced tremendous demand for them with over 1000 downloaded so far. In response, we’ve greatly increased the number of CPAKs that we offer and have numerous combinations of leading IP and software available. Searching for the CPAK that most closely matches your own design was difficult on a portal focused on models however so we decided to roll out a new portal to simplify this search. We’ve been staging this over the past couple of months to prove things out before we announced the portal and have been very pleased by how CPAK traffic is continuing to increase.

Q: Carbon System Exchange needs more commitment from IP and sub-system providers. Although you have good number of customers and partners already joined, what is your assessment of a larger community joining the initiative?

A: The ecosystem of IP, systems and software providers which System Exchange enables is one of the most exciting aspects of the new portal. Historically, all of the CPAKs which Carbon offers have been created exclusively by Carbon. We’ve helped numerous other companies supply virtual prototypes out to their customers but it hasn’t been done in an easily scalable or repeatable way. With System Exchange, we now have the mechanisms in place to easily enable partner companies to offer their own CPAKs and leverage the substantial infrastructure investments and partnerships that Carbon has in place to handle the important things like security, authorization and validation.

With System Exchange, we’re working with companies like Brekerand Kozio to help showcase how their software verification solutions can leverage the speed and accuracy of our virtual prototypes to help make their customers be productive more quickly. These partnerships arise because of the system perspective that is being delivered with CPAKs. Obviously, there is a substantially larger pool of IP, systems and software providers which can be tapped to expand System Exchange and we’re working on that now. We intentionally limited the number of partners in the initial rollout to make sure we got the initial infrastructure tooling done properly. You can expect to see additional announcements as we continue to add partners who want to showcase their system capabilities leveraging the speed and accuracy which we provide.

Q: How about small low cost systems? If you visualize the future growth in IoT space, that will need high volume, low cost systems; can they get benefit out of this System Exchange portal?

A: IoT poses a unique problem in some ways. Virtual prototypes are typically thought of adding value to the large, complex chips driving mobile phones, servers and networking equipment. IoT devices tend to be much simpler but any device which connects to the internet has to worry about a number of complex security and networking issues together with a constant push to reduce power consumption. In addition, since these products are typically going into a consumer marketplace, they’ll likely do so with huge price and time to market pressures. These are many of the same concerns that have traditionally driven innovation in the virtual prototype space and we envision the same thing with IoT. We’ve already seen some good customer traction here and expect even more as the space continues to mature.

Q: This is definitely a unique service idea utilizing the SaaS concept. How did you get such a novel idea, first with IP Exchange and now with System Exchange?

A: Honestly, this is truly an area where necessity was the mother of invention. When we first started generating instrumented models of ARM IP the entire process was manual. We would send a spreadsheet full of model options out to the end user and ask them to specify the configurations that they needed for each model. Almost every single time we did this, we would get back a request for something not supported by the underlying RTL. As you know, sometimes when you choose one option, it changes the availability of other options, etc. We had a tough time representing all of these trade-offs in the spreadsheet and the end user typically didn’t know all of the trade-offs either. This led to a lot of frustration and iteration as we arrived at the correct models for the user. This led us to automate the process using IP Exchange which basically took all of the configuration options and put them into a simple series of questions. Each question impacts the available answers to all the following questions. This way, we only enable the user to create models that are supportable by the underlying RTL. The fantastic side-benefit of this is we greatly reduced the amount of time required to create a model. It’s now less than an hour in most cases from the time the user clicks the “Build” button until the download link appears in their inbox. It also means we can manage these models for them so they can either download them again later or modify the configuration to generate a follow-on model. Since design is an iterative process, it’s not unusual for a single user to create multiple configurations of a single model to analyse the impact on the system. With IP Exchange, the user can do these 24 hours a day, 7 days a week which is important since we have users around the globe.

System Exchange is the natural extension of IP Exchange and reflects a lot of the trends that we’re all seeing in the market. First and foremost, designers don’t want to spend their time creating virtual prototypes; they want to spend their time using virtual prototypes. CPAKs enable this by providing extensible systems and software which often closely match their needs. Our users quickly started pushing us for additional CPAKs though and the sheer numbers of CPAKs available for certain IP blocks started ramping up quickly. For example, as of the end of September, 2014 we have 29 different CPAKs which incorporate the ARMCoreLink CCI-400 interconnect. The chances are good that at least one of those systems comes close to the starting point desired by our end user. Which one though? System Exchange lets them narrow this down quickly to the right system that meets their needs.

In the paragraph above, replace CCI-400 with Linux, or a processor or some other combination of components and you can see how the ability to narrow down the broad range of choices to the system that best meets your needs is an extension of IP Exchange that just makes sense.

Q: Do you see more such portals coming up in future, either by Carbon or other vendors?

A: I think that System Exchange has a huge amount of potential for future expansion so that’s likely where you’ll see us spending our energy on portals in the short to medium term. With the broad array of possibilities available with IP, systems and software providers we could easily see the number of pre-built systems quickly scaling into the hundreds or even thousands.

I don’t know how easy it would be for others to replicate what we’ve done. Carbon has some pretty unique characteristics that enable us to do what we do. We’ve been able to use our model generation capability to forge IP partnerships with the leading IP providers and leverage those partnerships to create systems. We’re unique here in that we don’t compete against any of our IP partners by offering any of our own IP. I think the combination of model generation capability combined with our partnerships makes this type of portal pretty unique. There are definitely other portals out there but only ours gives the users the ability to access virtual prototypes containing the critical link to system accuracty.

This was a great interaction with Bill and a new learning for me. I find this to be a significant step in system design and virtual prototyping for SoCs that improves designer productivity to a large extent and shortens time-to-design, thus easing and strengthening the design flow from system level. Looking at the nice quotes from several of Carbon’s customers and Ecosystem Partners (who already have their IPs on the Carbon System Exchange portal) in the press release, I firmly believe this initiative is going to proliferate in a big way in the semiconductor design community and a game changer in ESL space.

Agile IC Development

Agile IC Development
by Paul McLellan on 10-01-2014 at 7:00 am
Categories: IP, Sonics

If you have been involved in software development you have probably heard of the “waterfall” development methodology. This is the approach whereby a complete specification of the software is developed before a single line of code is written. Nowadays, few people develop software that way since it is too slow. And worse, nobody knows what the specification should be for a product like a video game or even a smartphone operating system. The more modern approach is known as “agile development” in which the basic idea is to get something up and working as soon as possible and then every week or two release a new version with more features. That way there is feedback from users as to what is important and only relatively small amounts of code can be written before a course-correction is made. The waterfall approach risks developing huge amounts of code before finding out that it is a mismatch to what the market needs. The most obvious example of this recently was the Obamacare website which had basically zero contact with users until the day it was released with disastrous consequences.

Agile development fits well with the modern approach to startups which focus on the MVP, minimum viable product. Get something out, start interacting with users, and then pivot as necessary.

But SoC development is still stuck in the waterfall era and is now at a breaking point. SoCs often have over 100 IP blocks from multiple sources, systems have a larger and larger software component, there are increasingly aggressive security and power requirements. But perhaps the biggest issue is that the specification changes all the time, so the idea that you can start from a fixed plan of what is needed and then just implement it is completely wrong. The market requirements are simply not known completely in advance. We need to have an equivalent to agile development in software, namely Agile IC Development.

In Agile IC Development the various stages of SoC design need to be performed more in parallel. Specification, prototype, design, synthesis, physical design, verification etc. Nothing is stable. Whereas waterfall is more vertical and sequential. First specification, then prototype, then design and so on. Ideally we would do everything in parallel but that is not practical: you can’t do physical verification in parallel with synthesis, for example. But the more the line is diagonal rather than top to bottom, the more agile the methodology is.

Today Sonics has launched the Agile IC Methodology along with several partners, or collaborators. I’m not sure what the official word is. The initial phase is to create a LinkedIn group to start the discussion. Sonics is too small to drive it single-handedly but on the other hand they are not so large as to be seen to be trying to set their own agenda and exclude their competitors as would be the case if one of the big 3 was driving it.

The partners in launching this appear in this video to give their perspective (12+ minutes). Along with Sonics, there is Mike Gianfagna of eSilicon, Jim Hogan, Warren Savage of IPextreme, Bernard Murphy of Atrenta, Mac McNamara of AdaptIP, and Neil Johnson of Xteme EDA.

The LinkedIn group is here.

September 30, 2014

Semiconductor double digit growth in 2014 & 2015

Semiconductor double digit growth in 2014 & 2015
by Bill Jewell on 09-30-2014 at 10:00 pm
Categories: Foundries, Semiconductor Intelligence

The global semiconductor market was US$82.2 billion in the second quarter of 2014 according to World Semiconductor Trade Statistics (WSTS). 2Q 2014 was up 4.8% from 1Q 2014 up 10.1% from 2Q 2013. Healthy growth should continue into 3Q 2014. The table below shows initial revenue growth guidance for 2Q 2014, final reported revenue growth for 2Q 2014 and guidance for 3Q 2014 for key semiconductor companies. 2Q 2014 revenue growth versus 1Q 2014 was strong, with 13 of the 15 companies reporting positive growth. The best results were from Mediatek with 18% growth and Texas Instruments with 10% growth. In general 2Q 2014 showed better growth than initially expected. Of the 12 companies which gave 2Q 2014 guidance, 8 exceeded the initial estimate (shown with an upward arrow). The other 4 companies basically met their guidance.

Companies are guiding for continued quarter-to-quarter revenue growth in 3Q 2014. 11 of the 12 companies expect positive growth in 3Q 2014, ranging from 2% to 11%. One-third expect 3Q 2014 growth to be higher than 2Q 2014 and two-thirds expect growth to be lower. However based on most companies beating their guidance in 2Q 2014, the final 3Q 2014 revenue growth will likely exceed current expectations.

What is the outlook for the semiconductor market in 2015? Key semiconductor market drivers are generally expected to show improvement in growth rates in 2015 versus 2014. The International Monetary Fund (IMF) projects 4.0% GDP growth in 2015, up from 3.4% in 2014. Gartner expects combined unit shipments of PCs and tablets to grow 9% in 2015 versus 6% in 2015. Although IDC forecasts smartphone unit growth will slow to 13% in 2015 from 24% in 2014, Gartner expects total mobile phone unit growth to improve to 4.5% in 2015 versus 3.1% in 2014. Our forecast models at Semiconductor Intelligence predict 10% semiconductor market growth in 2014 accelerating slightly to 11% in 2015.

The chart below illustrates various semiconductor market forecasts for 2014 and 2015. The projections for 2014 range from about 7% (WSTS, Gartner, MIC and IC Insights) to about 10% (Mike Cowan, Future Horizons and Semiconductor Intelligence). Based on the latest WSTS data and company guidance, the final 2014 number should be around 10%. The projections for 2015 are much more varied. WSTS and MIC expect 2015 growth around 3%, about half of the 2014 percentage growth. Gartner and Mike Cowan see 2015 at around 5% growth. IC Insights expects 2015 IC growth of 7.5%. Our Semiconductor Intelligence 2015 forecast of 11% is towards the high end. The highest number is from Future Horizons, which expects 2015 growth of “15% or higher”.

If our semiconductor market growth rates of 10% in 2014 and 11% in 2015 are correct, it will market two consecutive years of double digit growth for the first time since 2003 to 2004. However the growth is nowhere near as strong as we have seen in peak growth years such as 37% in 2000, 28% in 2004 and 32% in 2010. Market growth rates in the low double digits are healthy, but not high enough to indicate excessive growth and a potential significant correction. Our preliminary outlook for 2016 is semiconductor market growth in the 5% to 9% range.

September 30, 2014June 14, 2019

IP and Design Management Done Right

IP and Design Management Done Right
by Daniel Payne on 09-30-2014 at 4:30 pm
Categories: EDA, Perforce

At DACin San Francisco this past June I was able to visit and blog about two dozen EDA companies, however there were so many more products and events to see that I couldn’t possibly have enough time to enjoy them all. Fortunately for me there were plenty of videos made of vendor presentations, so this week I got caught up a bit by watching a video about Methodicsand presented at the Cadence theatre. Methodics is focused on automating the tasks of IP and design management for SoC and any chip design.

IP (Intellectual Property) is defined as everything that enables a design, like:

PDKs and Libraries
Memories
Tools and their versions
New Blocks
Derivative Blocks
Internal & External IP (reusable blocks)

IP blocks go through a natural cycle of being acquired, qualified, distributed and integrated in a project. Even when a project is completed, it can then become a new IP for re-use in the next project. Design Management (DM) tools have been around for awhile, like: Perforce, Subversion, CVS, DesignSync, etc. The Methodics approach is to work with any DM vendor, creating a tool flow that manages the entire design process like this:

The specific EDA tool name from Methodics is called project IC, and users can control it several ways: a command line interface, web app, a tight integration within Virtuoso, or integrate yourself using APIs. Within Virtuoso an analog designer can Check-in or Check-out cells by using standard menus, run visual diffs on schematics or layouts, plus use analog verification and regression management:

So within Virtuoso a designer can control analog tests and regressions, then see the status of each test over time.

The modular approach with project IC allows design teams to continue using their favorite DM tools, or add new DM tools like Git or NetApp. IP can be described as a hierarchy of lower-level IP blocks, and you can catalog all of the IP used within your own company to maximize re-use, keep communication updated about the status of all IP blocks, and control the access and permissions of each IP block.

Distributing your specific IP throughout the company worldwide is enabled with the concept of workspaces, where each location has their local repository and it’s all transparent to users.

Defect tracking is linked to each IP block, so you can visually see all bugs for all IP blocks that you are working with. Industry standard bug-tracking tools are used, like: Jira, TeamForge, Trac, Bugzilla. Releasing an IP block is an automated process to allow only good versions to be used. With the analytics and metrics tools you can customize what you dashboard looks like.

The big three reasons that engineers are choosing project IC for their IP and Design Management are:

Open Data
Open Interfaces
Open Architecture

September 30, 2014June 14, 2019

ANSYS Tools Shine at FinFET Nodes!

ANSYS Tools Shine at FinFET Nodes!
by Pawan Fangaria on 09-30-2014 at 4:00 pm
Categories: Ansys, Inc., EDA, FinFET

In the modern semiconductor ecosystem we are seeing rapid advancement in technology breaking past once perceived limits; 28nm, 20nm, 16-14nm, 10nm and we are foreseeing 7nm now. Double and multi-patterning are already being seen along with complex FinFET structures in transistors to gain the ultimate advantages in PPA from these technologies. In order to realize these technologies in actual designs, it’s utmost important that EDA tools move in tandem with such technologies manifesting their complex rules and constraints into the tools and methodologies which can be used to develop designs confirming to these technologies. As we move down the nodes, it becomes increasingly difficult for the tools to adapt to these complex technologies, thus adding a lag between the technology and tools.

I am extremely impressed with ANSYScollaborating with multiple foundries and making their tools compliant with most advanced technologies to date. A few months ago, I had blogged about Intel’sannouncement on the availability of their production proven reference flow for power, electromigration (EM) and reliability signoff using ANSYS simulation solution (using RedHawk, Totem and PathFinder) for Intel’s 14nm Tri-Gate process.

Read Intel & Ansys Enable 14nm Chip Production for more details.

Today, it’s yet another pleasure to write about TSMC’scertification of ANSYS tools solution at advanced nodes and ANSYS’s valuable participation in TSMC OIPwith a detailed presentationby Norman Chang, VP & Sr. Product Strategist at ANSYS. Before I talk about the presentation and how ANSYS tools handle the complexity of advanced node technologies, let me talk about the certification and some of the key points about ANSYS and TSMC partnership.

ANSYS was conferred with “Partner of the Year” award by TSMC. As a result of the intense collaboration between ANSYS and TSMC, ANSYS’s RedHawk and Totem are certified for TSMC 16nm FinFET+ (N16FF+) technology for static and dynamic voltage drop analysis, EM verification and thermal reliability. TSMC 16nm FinFET technology provides much improved PPA over its previous generation. At present, TSMC certified these tools with its V0.9 DRM and SPICE models, and V1.0 certification is on track before this year end. The collaboration is continuing further to enable designs at TSMC 10nm (N10) process technology. With N10 specific tool enhancements implemented, customer can use ANSYS tools to start their designs in TSMC N10 technology. Read the press release for full story.

Coming back to the presentation which was focused on thermal reliability of designs using FinFETs and 3D-IC designs, it provided great visibility on how minutely ANSYS tools handle physical effects at these nodes and the robust process used in the flow from chip to system and system to chip.

With increased gate density in 3D-IC and less open space for thermal distribution, the thermal effect gets enlarged, and that is compounded with higher drive strength devices such as FinFETs at 16nm. This mandates checks for advanced reliability and thermal impact with consideration of chip-package co-design to be accurate at 16nm; these checks are in addition to other checks such as ESD, power/signal EM, leakage, static and dynamic IR and others applicable at older nodes. The TSMC N16FF+ certified RedHawk and Totem elegantly handle complex EM and ESD rules, unique metal architecture and enhanced modeling of vertical resistance, double patterning and dummy devices. The resistance is correlated including middle-end and back-end layers.

The reliability signoff covers a large set of rules checking into Connectivity (Grid Weakness and Static IR), Reliability (EM, ESD and Thermal) and Power Noise (DvD Noise, Low Power and Impact on Timing). For each of these areas, multiple checks are performed; for example, in case of connectivity, cases such as missing vias, power/ground balance, resistance, IR drop, high power density etc. are performed.

As high temperature accelerates EM (which causes gradual displacement of metal atoms due to high current density) limiting allowable current density, the on-chip maximum temperature must be accurately estimated and controlled.

FinFET has typical structure for increased self-heating. Both, smaller gate length and higher Fin height contribute to increase in temperature. Also, narrow fin structure and lower thermal conductivity in the substrate causes trapping of heat. Both, FEOL process for devices and BEOL process for wires and their thermal coupling must be analyzed and accounted to accurately estimate the temperature.

ANSYS self-heat flow using RedHawk and Totem calculates self-heat as well as thermal coupling for instances and wires including thermal profile by taking primary input from design layout (LEF/DEF, GDS), techfile, library and device models, DSPF and foundry input. The Power EM run provides CTM (Chip Thermal Model) and average current information for power/ground wires and the Signal EM run provides rms current information for signal wires which are used in the computation of self-heating and thermal coupling.

Similarly chip thermal interaction on 3D-IC is analyzed by using various other techniques such as FE (Finite Element) modeling of complex 3D-IC structure.
Read Fast & Accurate Thermal Analysis of 3D-ICs for more information.

The complete Chip-Package-System solution for thermal analysis is summarized in the above picture where chip-aware system thermal analysis as well as system-aware chip thermal EM analysis can be performed.

The on-chip thermal-aware EM flow is depicted in the above picture where Sentinel-TI generates the chip thermal profile from the CTM generated by RedHawk and Totem and back-annotates it to EM violations. The MTTF (Mean Time to Failure) can be computed from the available data.

The set of class tools provided by ANSYS are well knit into system-aware-chip and chip-aware-system flows that provide fast and accurate Power Integrity, EM and Thermal Reliability solutions at advanced nodes. Considering extremely low noise and EM margins at these nodes, such solutions at high accuracy levels are must.

Cortex-M7: 6-stage, cached, 400 MHz MCU

Cortex-M7: 6-stage, cached, 400 MHz MCU
by Don Dingee on 09-30-2014 at 7:00 am
Categories: Foundries

“Who needs a 32-bit MCU?” It was a question asked a million times in the press when ARM introduced the Cortex-M family back in 2004. In fairness, that question predates the Internet of Things, with wireless sensor networks, open source code, encryption, and more needs for connected devices. Continue reading “Cortex-M7: 6-stage, cached, 400 MHz MCU”