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Semiconductor Expert Forum

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3 Self-Service Semiconductor Design and Manufacturing Wins!

3 Self-Service Semiconductor Design and Manufacturing Wins!
by Daniel Nenni on 10-12-2015 at 12:00 pm
Categories: eSilicon, Semiconductor Services

As the semiconductor consolidation continues and thousands of semiconductor professionals update their LinkedIn profiles, the march to create new silicon opportunities is increasing at a rapid pace. It is 1980s deja vu all over again when the fabless business model reenergized the semiconductor industry and brought affordable electronics to our homes and hands.

One of the leading enablers for the coming onslaught of wearable, IoT, robotic, autonomous, virtual reality, security, etc… designs is an automated online secure environment that provides a self-service, transparent, accurate, real-time experience from IC design through volume ASIC production. I’m talking about the STAR online design virtualization platform of course. STAR helps you manage complexity and make the right decisions on your ASIC journey from concept to volume production, absolutely.

The eSilicon STAR platform is closing in on 1,000 users (think design starts). These folks have explored many IP and prototyping and production tape-out options, several thousand in all. The 24/7, transparent experience offered by the platform is starting to change the way folks do business. Here are three examples:

A small startup found the eSilicon STAR platform through a Google search last year in late December – during eSilicon’s year-end shutdown. This company ran several MPW prototype scenarios with MPW Explorer over the shutdown period, and made one phone call to eSilicon to get clarification on a technical question. One phone call. A few days after New Year’s, they sent a signed contract. eSilicon closed a deal when no one was at work. This same company got their MPW prototypes and things went well from there with their end customer. They then generated a production tapeout quote with GDSII Explorer, signed the quote and taped out three weeks later. This startup used the data provided by eSilicon’s STAR platform to build their business plan.

Another startup booked an MPW run through MPW Explorer with no verbal communication at all. The entire deal was booked online. Another startup registered for a STAR account and committed an MPW run 90 minutes later. No phone calls. No human interaction at all.

eSilicon recently booked a tapeout deal with a large design services organization. This company had set up a STAR account and generated a quote with GDSII Explorer for their end customer before they ever spoke with anyone at eSilicon.

Self-service semiconductor design and manufacturing is becoming real…

The STAR Navigatortool allows you to quickly search, compare, and evaluate IP online to find the eSilicon memories and I/Os that best meet your chip’s power, performance, or area (PPA) targets and transparently access key data without navigating complex documentation or engaging in time-consuming evaluation processes.

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Tensilica 4th generation DSP IP is a VPU

Tensilica 4th generation DSP IP is a VPU
by Eric Esteve on 10-12-2015 at 7:00 am
Categories: Cadence, IP

You may not know Tensilica DSP IP core, but you probably use Tensilica DSP powered systems in your day to day life. Every year, over 2 billion DSP cores equip IC in thousands of designs supporting IoT, Mobile Phones, Storage/SSD, Networking, Video, Security, Cameras… and more. Why DSP processing, the foundation of all Tensilica processors, is getting such high adoption? Just because DSP processing is more energy and area efficient than CPU or even CPU/GPU processing. If you compare the energy dissipated to process image (in mJoule per frame) when offloading to Host CPU (4 cores), Host CPU (4-cores) + 3-pipe GPU (4-cores) or to a Vision P5 DSP like Tensilica 4[SUP]th[/SUP] generation IP core you notice 30X reduction factor.

Imaging/Vision processing is required in more application every day, like Mobile phone when processing the raw image from the camera, automotive to support the multiples applications linked with Automotive Driver Assistance Systems (ADAS), 4K Ultra-HD or IoT. That why the 4[SUP]th[/SUP] generation of DSP from Tensilica is labeled “Vision P5”. Before looking at the DSP architecture, let’s clarify a point: this DSP is both an Image Signal Processor (ISP) and a Vision Processing Unit (VPU). Directly interfacing with sensors, ISP used to be implemented in hardwired logic (RTL), but the trend is to move to “Soft ISP”. If we take the example of face detection, moving to soft ISP allows dividing by 5X energy consumption. Cadence Imaging/Vision DSP focus on Image post processing and on Image/Video analysis. The slide below helps understanding this focus. Post processing includes 2D/3D noise reduction, image stabilization, Super Resolution, etc. when Image/Video analysis (face detection, people detection and more) is part of Vision Processing.

Cadence Vision P5 DSP core is a deeply pipelined design running up to 1.1 GHz (on 16nm FF technology), being low power thanks to massive clock gating implementation. The core supports 256 ALU ops/cycle due to the vector extensions based architecture: 4 vectors ops per cycle, each being 64-way SIMD. Vector extensions data can be 8-b, 16-b or 32-b. To support vision-based ADAS, drones, and augmented reality, the designer will have to implement an (optional) Vector Floating Point Unit (VFPU). This VFPU can deliver 32 GFLOPS per second for a core running at 1 GHz. This core supports industry widest 1024-bit memory interface and the memory system performance is greatly improved, thanks to scatter/gather data registers. Up to 16X faster random memory access can be achieved for non-uniform access algorithms like image warping, edge tracing, non-rectilinear patch access… Finally, like the others Tensilica DSP IP core, the Vision P5 DSP core allows customers to add their own instruction set.

To support massive computing needs, multiple Vision P5 DSP cores can be implemented. Multi-core support shared memory and message-passing architectures. A five cores implementation can deliver up to 1 Tera-ops (1,000,000,000,000 operations per second !) but which is really amazing is the footprint : 2 sq mm in 16nm FF technology.

Imaging and vision processing is a very fast moving market, OEM are constantly changing optics, sensors, and new algorithms have to be developed to support emerging applications like face detection, face recognition. ADAS is becoming a reality and in the near future we can expect the car manufacturers and their suppliers to imagine many new applications and create new algorithms. They just need highly programmable and flexible engine, scalable thanks to multi-core capability. The 4th generation of Tensilica DSP, the Vision P5, has been developed by Cadence to support such applications.

By Eric Esteve from IPNEST

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Meeting DFM Challenges with Hierarchical Fill Data Insertion

Meeting DFM Challenges with Hierarchical Fill Data Insertion
by Tom Dillinger on 10-11-2015 at 12:00 pm
Categories: EDA, Siemens EDA

To describe the latest methodology for the addition of Design for Manufacturability fill shapes to design layout data, it’s appropriate to borrow a song title from Bob Dylan – The Times They Are A Changin’. The new technical requirements are best summarized as: “The goal is now to add as much fill as possible, which (ideally) looks like the actual design.”

At the recent TSMC Open Innovation Platform symposium, Zhe Lui from HiSilicon and Bill Graupp from Mentor Graphics presented results of their collaboration with TSMC to optimize the fill database for a HiSilicon N16 design. Specifically, Mentor and TSMC enhanced the algorithms in Mentor’s Calibre YieldEnhancer with Smart Fill tool (and the DFM Data Kit runsets), while Mentor and HiSilicon implemented a hierarchical methodology for managing the additional data volume and subsequent design verification runtimes.

Background

The addition of fill data for DFM originated with the Chemical-Mechanical Polishing (CMP) process for improved BEOL metallization planarity. To reduce the extent of metal line “dishing” during polishing, a rule for minimum local metal density measured across a small stepping window was established, and metal fill algorithms were implemented to meet this requirement.

The shapes were typically of a size/spacing to have minimal impact on electrical performance. The shapes were added “at the end, in the top cell” of the design, to meet tapeout criteria. That has all changed…

Current fill data requirements

Fill data must now meet a much more stringent set of lithography requirements – e.g., stepping window density (as before), density gradient limits, multi-patterning decomposition “color assigned” fill data, color-specific density on a layer.

No longer solely a methodology to address BEOL metal thickness uniformity after CMP, fill data is now directly related to:

  • lithographic uniformity of FEOL layers (especially for FinFET processes)
  • induced mechanical stress on devices (affecting their electrical characteristics)
  • etch rate uniformity (from the “loading” of material to be removed)
  • electrical behavior (due to the proximity of fill data to design data)

As a result, the volume of fill data required has exploded – “often greater than 1B shapes/layer, or 3-4X the size of the design database”, according to Mentor and HiSilicon. The full-chip (flat fill) DRC verification resources alone quickly became intractable.

Hierarchical fill

Mentor and HiSilicon developed a hierarchical “fill as you go” methodology, starting with lower-level cells. This necessitated enhancements to the Calibre YieldEnhancer Smart Fill algorithms. Optimizations were required at the perimeter of cells – “no empty space”. Interconnects were “wrapped” with fill data to match multi-patterning color assignments.

HiSilicon described the engineering approach needed to implement hierarchical fill:

  • (lower-level) cell selection
  • addition of blockage layers for subsequent fill steps
  • the flow for layout database management

This new methodology deployed at HiSilicon enabled them to maintain suitable turn-around time in final full-chip verification.

(Although HiSilicon and Mentor didn’t explicitly mention this feature in their presentation, Calibre Smart Fill also includes algorithmic support for ECO fill, a key feature required to keep the verification and analysis iteration time for a last-minute design change in check.)

As Moore’s Law proceeds, the complexity of DFM requirements will certainly continue to grow. This OIP presentation highlights that a foundry + EDA vendor + design company collaboration is extremely beneficial to drive tool and methodology enhancements, to address these complexity challenges. The times they are (definitely) a changin’…

-chipguy

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Applying EDA Concepts Outside Chip Design

Applying EDA Concepts Outside Chip Design
by Bernard Murphy on 10-11-2015 at 7:00 am
Categories: EDA

(I changed the title of this piece as an experiment) Paul McLellan recently wrote on the topic of new ventures crossing the chasm (getting from initial but bounded success to a proven scalable business). That got me to thinking about the EDA market in general. In some ways it has a similar problem, stuck at $5B or so and single-digit growth rates, on the left side of a chasm separating it from an at least conceivably much broader market. EDA isn’t going to get more of the semiconductor pie, so now we look for ways to expand upward into software and embedded systems. That’s one way to grow the market, but are there different, or at least complementary ways to expand? One opportunity may be network architecture design and analysis, an emerging (and therefore potentially fast-growing) domain to which it seems we could adapt EDA techniques and principles.

It doesn’t take a lot of thought to realize that a network looks a lot like a netlist. Of course there are differences. All or most connections are bidirectional, “signals” are a lot more complex than 1’s and 0’s and the nodes are a lot more complex than logic gates. However, if obstacles like that were insuperable we’d still be using Spice to simulate logic, so differences aside, perhaps there are opportunities to apply netlist tool concepts to networks.

This idea is not new, but neither is it fully developed. SIGCOMM, the ACM’s group on data communications held a conference this August in which they devoted half a day to a tutorial on network verification. An extract from the tutorial introduction makes this point: “One can also view a network as a circuit using an EDA (Electronic Design Automation) lens …. If design rule checking is analogous to static checking, what is the analog of synthesis? … These analogies have led networking researchers to frame a new research agenda, made compelling by the ubiquity of cloud services, called Network Verification. They ask: what are the equivalents of compilers/synthesis tools, debuggers, and static checkers for networks?”. If that isn’t a clarion call for EDA innovators searching for a new direction, I don’t know what is.

One example of static analysis checks configurations for potential errors where routers may learn routes that are not usable or conversely fail to learn routes that are usable. More recent efforts aim to formally assess reachability of IP addresses and to define semantics for networks which might provide a foundation for proofs of correctness. Motivated by Software Defined Networks (SDNs) there is work around how to specify requirements at levels above the fairly atomic level in which individual routers are programmed, moving the abstraction up to network policies, so that individual router configurations can be derived automatically from a synthesis / compilation step based on that higher level requirement. There are analogs to ATPG (in this case, automatic test packet generation) and coverage analysis to perform end-to-end testing and performance analysis in network. And there’s more – this seems to be a very fertile area of research.

A very interesting aspect of analysis in this domain is that it can and often will be applied to live networks, rather than networks in the design stage. Application in field deployment was always a holy grail for EDA because it would take you past the very small universe of designers who might use your tool to the potentially much larger universe of field-deployment and maintenance specialists. That is what may make this direction so compelling – to grow from a total market of say 10-20K chip designers to a market of hundreds of thousands or millions of IT/IS and networking engineers.

Of course this won’t be easy, but in a slowly-growing, mature market returning interesting value to investors isn’t easy either. EDA principles will carry over and maybe some techniques too, but a lot of invention and new development will be required. And you have to worry about the small detail of if or when this market will actually take off; you don’t want to get too far ahead of the parade. That said, there are indicators. The ACM tutorial referred to the growth of cloud services. The potentially significant growth of IoT will further compound the complexity of networks above those we understand today and software defined networks seem likely to become more commonplace. In this new reality, wouldn’t you think a need for automated design, optimization and verification tools would become essential? The ACM certainly seems to think so.

More articles by Bernard…

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S2C ships UltraScale empowering SoFPGA

S2C ships UltraScale empowering SoFPGA
by Don Dingee on 10-10-2015 at 7:00 am
Categories: EDA, FPGA, S2C EDA

Most of the discussion around Xilinx UltraScale parts in FPGA-based prototyping modules has been on capacity, and that is certainly a key part of the story. Another use case is developing, one that may be even more important than simply packing a bigger design into a single part without partitioning. The real win with this technology may be system-on-FPGA (SoFPGA).

In the early days of FPGAs, everything was basic rows and columns, without much visibility inside. The good news was this allowed logic blocks to be laid down like tiles. Combinational logic was happy with this approach, and simple sequential logic benefitted from the flexibility. Complexity rose, and generations of more sophisticated FPGAs with improved clocking structures, logic enhancements, and reduced propagation delays raised the bar.

FPGA-based prototyping systems evolved into real prototyping platforms. The prime directive was to reproduce behavior of RTL intended for an ASIC as faithfully as possible in an FPGA. This was easiest if a design fit entirely within a single FPGA, but innovators quickly found creative ways to support larger designs with partitioning and interconnect strategies connecting two, four, or more FPGAs. Debug capability was enhanced, enabling teams to see what was happening inside a design when things were not quite right. Speeds increased, allowing actual software to run, and synthesis times for revisions dropped allowing changes to be made quickly.

That all adds up to a strong value proposition for FPGA-based prototyping of SoCs.

S2C’s announcement of production shipments of single UltraScale VU440 (Single VU) Prodigy Logic Modules represents state-of-the-art in single-module capacity and debug capability. With dual and quad modules on the way soon (available for ordering now), the ability to partition big SoC designs across four UltraScale VU440s is a given.

What sets S2C apart from other FPGA-based prototyping systems is the potential for large-scale system-on-FPGA design, where the deployment system is the FPGA-based platform. Workload-optimized platforms for hardware acceleration of processing and analysis are taking advantage of high-speed FPGA interconnect and advanced DSP capability found in the UltraScale VU440. The Prodigy Cloud Cube from S2C connects up to 16 Single VU Logic Modules today in a massively configurable SoFPGA.

Such a SoFPGA can tackle parallelism on a scale few other architectures can achieve. SoFPGAs also excel in relatively low-volume applications where justifying a SoC would be difficult. Applications like big data processing, broadcast video, image processing, financial trading, and others with unique high performance requirements in select deployment are ripe for this kind of innovation.

In a departure from previous generations, design of SoFPGA systems with advanced FPGAs like UltraScale can now leverage SoC-class IP, as opposed to only brute-force FPGA tactics or basic RTL for synthesis. The biggest development so far is SoFPGAs are now utilizing AXI as the IP interconnect. This has two distinct advantages: it abstracts the hardware interconnect making IP blocks reusable, and it allows managed traffic flow for advanced software design.

Startup Wave Semiconductor is beginning to emerge from stealth mode, and is providing a look at how they are leveraging AXI in large FPGA designs. At the October 14[SUP]th[/SUP] session of the DVClub in Milpitas sponsored by S2C, Wave will present how they are using deep packet inspection to verify AXI traffic. We usually associate DPI with an external networking interface such as Ethernet, but the use of DPI within SoFPGA designs could provide significant advantages in scalability and security.

More details on Single VU production shipments and the upcoming special event are on the S2C site:

S2C Shipping Prodigy Virtex UltraScale and Kintex UltraScale FPGA Prototyping Boards to Customers Worldwide

Wave Semiconductor to Present at S2C-Sponsored DVClub in Silicon Valley on October 14

Again, I’d emphasize that the new S2C Single VU modules are useable in stand-alone configurations, in a more traditional FPGA-based prototyping role. The potential for SoFPGA as a processing platform is fascinating, and we’re excited to see where cloud interconnect, AXI-based IP, and system level approaches like DPI can take applications.

More articles from Don…

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Processors Rule the Day

Processors Rule the Day
by Tom Simon on 10-09-2015 at 7:00 pm
Categories: IP

It used to be that if you went to a processor conference, you could expect to spend hours listening to talks about pipelining, cache schemes and processor architecture. Well, I went to the Linley Processor Conference this week in Santa Clara and found the topics pretty compelling. Processors are in just about everything. It is easier to ask what does not contain a processor. So this conference was, in many ways, about just about everything. Chief among the topics was automotive, mobile, networking, IoT, consumer and enterprise.

The keynote was given by Linley Gwennap, principal analyst and founder of the Linley Group. His talk was titled Processor Technology and Market Trends. He covered general embedded trends, processor IP, networking, IoT and advanced automotive. The presentations over the two days drilled into all of these areas.

In 2014 Intel had the lion’s share of the embedded market. This comes about from them leveraging the PC ecosystem for things like ATM’s, signage and other appliance type applications. Next in market share is Freescale who has a strong lead in the comms sector. Next, each with smaller shares are Broadcom, Cavium, AMD, LSI, Marvell and AppliedMicro.

If you have been following the news, you already recognize many of the above companies from the business pages. There is a wave of consolidation. NXP acquires Freescale, Avago acquires LSI and Broadcom. Look for the ripple effects from these changes.

Consumer, IoT and mobile/wearable all require cost, power and footprint reduction. The most effective way to accomplish this is through integration. There is an increase in SOC complexity. During the conference, many examples of processor based SOC’s had many other functional blocks on board, and also in some cases many processors – each targeted at a specific sub function.

Designing these SOC’s requires a deep understanding of application needs, so they can operate most efficiently. The right processors need to be used, along with specific IP and the software to drive the whole system. Complexity is rising.

Linley sees the benefits of Moore’s law only applying to companies with the money to take advantage of it. The increases in mask costs due to double patterning is contributing to this. 28nm is a hinge node, where for the first time if you go to a smaller node you will pay more per transistor. This is forcing costs sensitive products to stay on 28nm.

There is real movement in the high end embedded space to ARMv8. AMD, AppliedMicro, Cavium, Freescale are already shipping ARMv8 cores. Broadcom and Marvell are in development. This is a big push into the 64bit ARM architecture for applications that need the horsepower.

With smartphones containing 2 to 4 chips with CPU IP, this segment drives the most shipments. However, the fastest growing segment is embedded, growing at 29% in 2014. Most of this is MCU’s. In 2014 CPU IP was used in 15.3 billion chips. Two thirds of which were mobile and embedded.

Heterogeneous processors are now commonly combined onto one chip. This enables each processor type to be optimized for specific tasks. Listening to music might be done with a DSP, email can be handled with a small, slow CPU; but video will be shifted to heavier duty processors that consume more power. Turning off unneeded processors can dramatically increase battery life. This trend is increasing for other reasons. Physically partitioning tasks offers greater security as well.

Automotive applications were a big topic for the entire conference. As cars add safety and convenience systems a large need for processors is developing. Some notable applications include adaptive cruise control, which can maintain a safe following distance to the car ahead. Drowsiness detection and lane detection are two other significant safety systems that will require significant processing power. The big prize of course is the self driving car. Linley expects fully autonomous technology to be available as an adder of less than $10K by 2022.

The talk and the conference showed just how much technology is moving to adapt to our needs. During the conference I realized that the idea I had in my mind about what my first robot would look like was wrong. Of course I imagined something that could ‘see’ its surroundings through sensory input and respond to them. I also imagined that it might have a neural network, and processes information much like a human brain. It would have awareness of its location and be able to move from place to place. What I did not realize is that I would sit inside of it – and that it would probably be a car.

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Five Areas at #53DAC That Require Your Contribution

Five Areas at #53DAC That Require Your Contribution
by Daniel Payne on 10-09-2015 at 12:00 pm
Categories: EDA

The 53rd DAC (Design Automation Conference) is some 8 months away, however to make this conference and exhibit another success requires planning, people and awareness. That’s where you come in, because you can contribute your expertise in five different areas:

[LIST=1]

  • Panels – broad interest, interesting, timely, engaging, informative
  • Special Sessions – track specific, original angle, educational
  • Tutorial – hands-on, immediate value, 1.5- 3 hours in length
  • Workshops – not vendor-specific, two – nine hours, multiple speakers
  • Research Papers– papers on design of circuits, architectures and systems

    I’ve organized a DAC panel session before all about SPICE circuit simulators and it was a blast to select the topic, find speakers, and then come up with interesting questions for each panelist to answer in front of an audience. An open Q&A time is also part of every good panel to allow the attendees a time to ask their own questions or challenge what panelists just talked about.

    If you have ever attended a past DAC and thought about sharing what you’ve learned about our industry with others, then take that bold first step and consider contributing in any of these five areas. The DAC folks on the committee are quite helpful in answering your questions and leading you through the process, so why not give it a try?

    Not only are their five areas for you to contribute in, there are also six different tracks based upon your interests:

    • EDA
    • Embedded Systems and Software
    • Design and IP
    • IoT
    • Automotive
    • Security

    Having six tracks is something relatively new at DAC, and I think that it makes a lot of sense to align with the end-user markets instead of a singular focus on EDA software and algorithms.

    Bloggers from SemiWiki will attend this DAC as in past years and help keep you informed over the next 8 months about what to expect, emerging trends, and which companies look most promising to visit in the exhibit area. When I worked at EDA companies we would focus on showing our best, new features in time for DAC each year, often getting the new code ready just days before DAC started in order to look our strongest against all of the other competitors, so there’s a big benefit to having an annual event like DAC to keep our industry growing and responsive.

    Deadline
    The DAC website is filled with details on how to go about making a contribution, but you have to meet the deadline of November 17th to be considered for this event in Austin, Texas from June 5-9.

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    IMEC and Cadence Disclose 5nm Test Chip

    IMEC and Cadence Disclose 5nm Test Chip
    by Scotten Jones on 10-09-2015 at 7:00 am
    Categories: Cadence, EDA, ESD Alliance, Events

    Recently imec and Cadence disclosed that they had fabricated 5nm test chips. This afternoon Dan Nenni and I had a conference call with Praveen Raghavan, principal engineer at imec, and Vassilios Gerousis, distinguished engineer at Cadence to get more details on what the test chip is and what was learned.

    First off Vassilios really stressed the challenge of designing for 5nm and the need for collaborations like this one between imec and Cadence. Timing optimization and routing are very challenging! The IMEC/Cadence collaboration combines detailed process knowledge with EDA.

    The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers. The chips had a dummy metal 1 layer and via 1, metal 2 (M2), via 2 (V2) and metal 3 (M3) layers. The M2 and M3 layers were really the focus of the work and the metal pitch was scaled down from 32nm to 24nm.

    Three different patterning approaches for M2 and M3 that were evaluated:

    [LIST=1]

  • EUV
  • Hybrid 193i SAQP with EUV cut mask
  • 193i SAQP with 3 color 193i cutting

    The EUV approach used single exposure EUV to form the metal lines. The hybrid approach used argon fluoride immersion (193i) with self-aligned quadruple pattering to form the metal line patterns and then a single EUV exposure to define the metal line cuts. The 193i SAQP approach used argon fluoride immersion (193i) with self-aligned quadruple pattering to form the metal line patterns and then three separate 193i cut masks (3 color cutting) to form the pattern. A litho-etch-litho-etch-litho-etch (LE3) approach was used to pattern V2.

    All three approaches were found to be viable. The Hybrid and 193i approaches both use SAQP to define the metal lines and require more dummy lines than the single exposure EUV approach which should lead to better performance for the EUV single exposure. However, things like Line Edge Roughness (LER) might be worse for EUV and negate the advantage.

    Simulations included fins underneath and the resulting interconnect layers meet the timing needs for 5nm. The metal and barrier layers used were not disclosed. EUV throughput was also not disclosed but Praveen did say that imec is upgrading to an 80 watt source.

    The images above are from an article by Debra Volger of SEMI The Roadmap to 5nm: Convergence of Many Solutions Needed where she quotes An Steegen, SVP of Process Technology, at imec:

    “Imec is enabling the roadmap to 5nm via a multitude of process features in close co-optimization with the design to drive down to the required power performance and cost trade-offs,” Steegen noted. “We are convinced that we have identified building blocks to enable the roadmap from 10 to beyond 5nm. But it’s not a one-solution thing – it’s many things that need to come together.”

    Here are the quotes from the Cadence press release in case you are interested:

    “Our collaboration with Cadence plays an important part in the development of the world’s most advanced geometries including 5nm and below,” said An Steegen, senior vice president of Process Technology at imec. “Together, we developed the necessary technology to enable tapeouts for advanced technology nodes such as this test chip. The Cadence next-generation platform is easy to use, which helps our engineering team stay productive in developing the rule set for advanced nodes.”

    By achieving this milestone, Cadence and imec continue to demonstrate our dedication toward pushing patterning technologies to increasingly smaller nodes,” said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. “With imec technology and the Cadence Innovus Implementation System, we’ve created a working flow that can pave the way for developing innovative next-generation mobile and computer advanced-node designs.”

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    BATTERYGATE: Is Apple’s Samsung made iPhone 6S Core Rotten?

    BATTERYGATE: Is Apple’s Samsung made iPhone 6S Core Rotten?
    by Robert Maire on 10-08-2015 at 4:00 pm
    Categories: Foundries, Samsung Foundry

    By this time, anyone with a pulse in the tech industry knows that Apple has dual sourced the A9 processor for the Iphone 6S, from both Samsung and TSMC. There are even apps to tell whether your 6S has a Samsung or TSMC part in it. People have run performance comparisons and concluded that the processing performance is the same, which is entirely expected as we are sure both parts have the exact same logic design and are clocked at the same speed. Ones and zeros are ones and zeros on anyone’s chips….all things are equal in the digital world….

    Well…people have started to check in on the analog world of power consumption (where there can be a difference) comparing Samsung Iphones to TSMC Iphones, and low and behold the Samsung and TSMC made chips may not be quite so identical. Initial, amateur reports indicate a significant difference with Samsung parts consuming more power….far more..

    Here is an example of one such test result:


    Samsung A9 versus TSMC A9 power consumption tests

    We would remind readers That TSMC has made a very big deal about their power consumption/leakage advantage over other competitive manufacturing processes. TSMC has claimed up to a 20% power advantage in their 16nm process which may jive with these unconfirmed comparison results.

    Any measurabledifference could be a problem for Apple..
    The initial results look like a significant power consumption difference between the Samsung A9 and the TSMC A9, potentially measured in hours rather than minutes. Even if final analysis shows a 10% differential or less it could still pose a problem as Apple could start to see 6S owners returning their Samsung 6S for a “better” TSMC 6S. The bad press could really hurt Apple and its flawless image very badly.

    We think the difference better be less than 5% or problems will start. A 10% differential in power consumption would be bad, a 20% difference could be horrible and so on…costs and losses could mount up for Apple for returns, repairs etc;…. Even if these initial reports prove to be untrue and there is no significant power difference just the rumor mill buzz of two types of 6Ss can cause issues.

    Cottage industry for phone testers…
    There are already different apps that can tell which processor you have in your Iphone. One even reports the results back to a website that keeps score of TSMC versus Samsung parts. We can imagine that cell phone repair shops will charge customers $20 to see if they should return their beloved Iphone because it has a potentially flawed Samsung A9…..

    Faster than you can say class action lawsuit
    Lets start the stopwatch ticking on Oct 7th at noon and see how long before the first law firm brings a class action suit against Apple and their defective Iphone 6S. Will Apple have a recall? How will they handle the PR? It could be a circus of TV people interviewing people at Apple stores as they return their phones….just in time for the holiday season

    Conspiracy theories?
    We can only imagine the first conspiracy theory that Samsung did it on purpose to sabotage Apple’s phone business in favor of their own…..

    Blowback on Apple due to supplier gamesmanship…
    Apple is well known to press suppliers to the breaking point and beyond. Apple went to a new extreme and got very cute by dual sourcing the most critical component in the phone this way playing Samsung and TSMC off against one another. Could this now have blown up in their face? Who tested and vetted both parts at Apple? Where’s the quality control?

    We would question why Apple would even take the risk of using two different parts in the same phone….its just begging for comparison & trouble. Just use one part in the 6S and the other part in the 6S plus so you can’t compare them. Maybe Apple was forced into this position due to availability issues.

    In too much of a rush?
    We had pointed out almost a year ago that we were surprised that Samsung would be able to get the 14nm part out in time for the 6S launch. Early yields were low and Samsung would have to ramp faster then ever before to make it in time. Maybe it was just too fast a ramp and the part and the process was never fully perfected leading to the power issues.?..

    Intel’s schadenfreude…
    If this turns out to be true and a significant issue we will likely be able to hear the laughter in the halls of Intel all the way in New York (Intel had their own mathematically challenged processor many years ago). There has obviously been concern over Samsung and TSMC catching up to Intel….well maybe this could potentially prove at least Sasmung moved too fast and took too many risks versus Intels more cautious slowing of their tick tock cadence.

    Speaking of Intel, we are pleased with the performance of the stock, nicely and steadily up well over 10% since we turned positive on it a few weeks ago…looking better every day

    Leaky faucets and transistors…
    Transistors are like faucets turning on and off the flow of electrons or water, however transistors never fully turn off and tend to “leak” a little. This “leakage” is the primary culprit of power consumption in semiconductor devices.

    Leakage in transistors is due to a multitude of factors, many of which are interrelated. Transistor design is a big one, especially as the industry has recently switched from “planar” to “FinFET” transistors (which Intel pioneered). Materials and the processing of those materials by semiconductor equipment tools is very critical. Many different tools and materials impact leakage current.

    Though the logic design of Samsung and TSMC’s A9 is the same, the manufacturing process “flow” is quite different, using different sets of tools and materials and different steps in different sequences. TSMC has strongly made the claim that their 16nm process is superior to competitive offerings in terms of leakage/power consumption.

    Samsung is 14nm while TSMC is 16nm…
    Smaller is usually better in the semiconductor industry but everyone’s measure is not quite the same. Samsungs A9 uses a “14nm” process which results in a smaller die size (chip size), while TSMC uses a 16nm process that results in a larger chip which is usually associated with higher power consumption, but not this time around, making the potential difference even more intriguing.

    If Samsungs 14nm process proves to be inferior to TSMC’s 16nm process that will be a boon and huge win for TSMC and a huge loss for Samsung on the foundry side (aside from the obvious Apple problems). It could be a huge torpedo in the side of Samsungs Semiconductor business which has been their primary driver of profitability.

    What about the equipment companies?
    We can already hear the equipment companies taking credit for their equipment making the difference at TSMC and Samsung. If its does turn out to be equipment specific it would obviously have huge impact (Cue Art Z and UTEK) . We would imagine this has to be positive for process control companies like KLAC and smaller cousins Hermes, RTEC, NANO and NOVA etc;. Everyone will clamor to find out the root cause.

    This could turn out to be a circus…
    This has all the makings of a potential circus in the industry and in the stocks. Certainly negative to very negative implications for Apple if true. Negative for Samsung and positive for TSMC. Likely positive for some equipment companies but not all. Positive for Intel as it shows their process still reigns supreme.

    There are many , many moving parts and right now we still don’t even have solid proof that an issue even exists or enough information to analyze but we do understand the potential implications and want guard our portfolio against them.

    We will be waiting for more information and definitive tests…..

    Meanwhile…I am going to test our families new Iphone 6S and get in line to return it at the Apple store if it has a Samsung A9 before the rush happens……

    *Disclaimer: So far we have not seen a credible, reliable, scientific source of comparative power consumption testing – sources on the internet appear to show similar results but are unsubstantiated and therefore questionable so far…..

    Robert Maire
    Semiconductor Advisors LLC

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    Cadence Outlines Automotive Solutions at TSMC OIP Event

    Cadence Outlines Automotive Solutions at TSMC OIP Event
    by Tom Simon on 10-08-2015 at 12:00 pm
    Categories: Cadence, EDA, Events, TSMC

    I used to joke that my first car could survive a nuclear war. It was a 1971 Volvo sedan (142) that was EMP proof because it had absolutely no semiconductors in the ignition system, just points, condensers and a coil. If you go back to the Model T in 1915 you will see that the “on-board electronics” were not that different. However, today’s cars have an ever increasing amount of semiconductor content. Let’s just hope there are no EMP’s anytime soon.

    Automotive electronics systems now have enormous requirements for computation, bandwidth and reliability. I attended a talk by Cadence’s Charles Qi at the recent TSMC Open Innovation Platform (OIP) Forum where he outlined the major trends in this area.

    By comparison to current needs, the previous bandwidth requirements were quite low. Cars have used simple networks like CAN, but increasing complexity is leading to the adoption of Ethernet standards specifically adapted to automotive needs and environments. The diagram below highlights the kinds and numbers of systems that are going to be built into cars.

    As you can tell, there is audio, visual and sensor data that needs to be handled. There are strict requirements for timely delivery of certain data in automotive systems. The umbrella term for this is AVB, or Audio Video Bridging. It is broken down into a set of IEEE standards within 802.1BA. These standards address time synchronization, traffic shaping and priority queuing. Below is a diagram that lists the applicable IEEE standards for automotive communication.

    Ethernet offers many advantages. It can run over twisted pair, it can carry power and it is an established standard that will continue to provide legacy support for many years. Charles outlined Cadence’s IP offerings which address the evolving Ethernet communication needs in automotive applications. Here is his slide that summarizes Cadence’s solution.

    Many of the systems in the first diagram require significant processing power. Today’s systems already perform Advanced Driver Assistance (ADAS), and will be pushed even further when self driving cars arrive in earnest. Already radar based features include front collision avoidance braking, adaptive cruise control and rear collision detection. Additionally, there are vision and audio/sound based systems that will require computing power.

    Cadence is positioning its Tensilica IP as a solution for automotive processing. They have a power sipping architecture that can be fine tuned to specific applications; and the development tools work to create custom compilers and libraries for many of the coding needs encountered in developing systems for emerging automotive standards.

    Tensilica also offers customizable DSP cores to further accelerate automotive product development. Their IVP DSP’s are well suited for ADAS development. The IVP DSP offers VLIW and 64 way SIMD. Coming in under 300mW, they offer impressive performance with minimal power draw. One of the most interesting slides was on the problem of pedestrian detection. ADAS systems will need to do this efficiently and reliably, even if the person only shows in as small an area as 64×128 pixels.

    Charles also spoke about ISO26262; we will be hearing a lot more about this in the coming years. It is a comprehensive standard for ensuring functional safety starting at the requirements phase and going through implementation. Unlike phones and fitness computers, automotive electronics play a role in life or death situations. Everything designed for automotive applications will need to comply with ISO26262. Here is a slide from Charles’ talk that gives an overview.

    Well, I am still waiting for my self driving car. However, it is clear that automobiles will be competing on a lot more than looks and horsepower. In the meantime I look forward to the increased safety and possibly easier driving that things like front collision avoidance braking and adaptive cruise control will offer. For more information on Cadence IP for automotive applicationslook here at their website.