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Semiconductors and Conflict Minerals

Semiconductors and Conflict Minerals
by Daniel Payne on 12-21-2015 at 12:00 pm
Categories: Dassault Systemes, EDA

Our semiconductor industry uses many different materials and chemicals in the production of chips, boards and electronic systems. But what should we do if the minerals like tantalum, tin, tungsten and gold are coming from the eastern provinces of the Democratic Republic of the Congo where armed bandits are forcing workers against their will? In the United States there’s a law called Section 1502 of the Dodd-Frank Wall Street Reform and Consumer Protection Act that requires companies to identify where the minerals used in their products came from. Our semiconductor companies need to have a Materials Declaration (MD) and a Conflict Minerals Report (CMR) to be in compliance with directives and industry data reporting standards like:

  • RoHS (Restriction of Hazardous Substances)
  • REACH (Registration, Evaluation, Authorisation and restriction of CHemicals)
  • ELV (automotive End of Live Vehicle requirements)
  • GADSL
  • Battery
  • Packaging
  • WEEE (Wasted Electrical and Electronic Equipment)
  • Dodd-Frank Conflict Minerals
  • IEC-62474
  • Aerospace & Defense DSL


Mike Zepp from Dassault Systemes spoke with me by phone to share his background in plastics R&D, then the automotive industry where he has first-hand experience with what it takes to be compliant and produce a CMR. In 2005 Mike joined Dassault because they had a vision and software to help companies be compliant with these types of regulations and laws.

The specific software from Dassault is called Material Compliance Manager and it lets you assess product materials compliance during product design through integration with engineering BOM management. You can even integrate Material Compliance Manager with your favorite PLM and ERP systems. The basic process follows this sequence for your supply chain of outsourced components:

  • Requesting
  • Receiving
  • Reviewing
  • Approved material compliance
  • Conflict minerals declaration

Mike shared that many electronics companies started out building their own in-house tools to track compliance, but now many have started to considering switching to something off the shelf so that they can focus on their core business competence. Starting with their 2014 SEC filings, the new US law applied to US publicly traded companies, and they must declare that their products don’t contain any conflict minerals, an extensive process where companies have to request data from the OEM all the way down the supply chain, ultimately reaching the smelters of mined ore. Fortunately, the Dassault software manages all of this information throughout the supply chain, ingesting the data, sending out emails, and managing the process.

The Materials Compliance Manager is a browser-based tool that helps any organization create their materials compliance declaration. Companies like Keysight Technologies (ex Agilent) have about 100 people using this software, then thousands of engineers use the results of the tool to confirm that their products are compliant. Other companies that you might of heard about also use the software: AB Sciex (a division of Danaher), GE Healthcare, and Tesla Motors.

I’ve recycled my old consumer electronics devices at the local Staples store, where they gather a variety of scrap electronics and an electronics recycler then decides how to re-use and dispose of all the bits and pieces to protect the environment from hazardous chemicals. Lots of companies need to worry about being compliant: Foundries, Fabless companies, packaging companies, the electronics supply chain.

You can learn a new tool like the Material Compliance Manager in about a week or two to become proficient, and the folks at Dassault can help get your engineers trained. In summary, the key features and benefits of using this approach are:

  • Manage materials to meet environmental compliance
  • Analyze your product’s compliance
  • Security and IP protection
  • Assess impact of new compliance directives
  • Manage supplier material declarations
  • Export of product compliance to customers
  • IMDS integration for auto suppliers
  • Integrate the supply chain for supplier data collection
  • Start supplier material declaration requests
  • Determine engineering BOM materials compliance
  • Maximize reuse of compliant components

Related Blogs

An Easier Way to Reach Design Closure for SoC

How Can Big Data and EDA Tools Help?

Enterprise Design Management Comes of Age

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Why Medical IoT is Set to Take Off!

Why Medical IoT is Set to Take Off!
by Rajeev Rajan on 12-21-2015 at 7:00 am
Categories: Foundries, GlobalFoundries, IoT

In a recent SemiWiki post, “Why Medical IoT Won’t Take Off,” the author raised some very interesting points on why certain IoT applications won’t succeed. But, it’s important that these points are looked at holistically, within context, and compared to other IoT features that are already improving health by increasing the availability and quality of care.

Source:N2M Advisory

On the author’s first point of bridging the gap between the IoT community and the medical community, focusing on the largest healthcare organizations that serve the most number of patients, you will be hard-pressed to find any that don’t have some form of a Digital Health office, with leaders ranging from Chief Digital Officer, Chief Information Officer (CIO), Chief Medical Officer / Chief Medical Information Officer (CMO/CMIO). Their charters are to be abreast of the technological advances in the medical space ranging from Smart Devices, IoT, Healthcare Information Technology (HIT), and Data Management and applying them to care delivery protocols. . Today, there are quite a few healthcare startups being launched by experienced doctors who are very knowledgeable in the medical and technology ecosystem space as well as multiple pilots and publicly announced rollout plans. Similarly, the majority of US government agencies such as the FDA, FCC and FTC are augmenting their staff with cross-domain expertise. Numerous HIT consulting firms are managing the technical implementation, while incorporating the applicable policy and regulatory requirements.

On the regulatory side, the FDA has been making policy revisions over the past few years for communication, smartphones, and Mobile Medical Apps (MMAs) to reduce the regulatory burden; terming this as Smart Regulation.

Today’s IoT technologies typically provide the processing, communicating, sensing, gateway capabilities that enable data collection, security, and battery/power management for long-term operation. These IoT features need to be combined with compelling user experiences to create effective patient-consumer solutions. In a broader context, when applied to the medical field, the promise of IoT is to enable Remote Patient Monitoring (RPM) solutions.

On the point of IoT devices generating a large amount of data, we need to clarify what is the data and which device is generating it. Typically in RPM today, there are two ways medical and IoT operate to collect the patient’s vital signs medical measurement reading: (1) an IoT gateway (example) device gets the reading from a patient’s medical device (e.g. blood pressure monitor, weight scale, blood glucose meter etc.), and (2) a medical device and the IoT gateway are a single device (example) that gets the reading. Afterwards the reading is communicated over a wired or wireless network to the doctor’s office/provider system/3[SUP]rd[/SUP] party healthcare partner/other. The amount of data generated from a typical home-use medical device can vary from a few kilo-byte (KBs) to a few hundred KB’s per reading. Data growth is caused, not by the per measurement readings, but by the patient taking multiple readings over the span of a day and making it available, near real-time, to their doctor’s office. Imagine a patient going to their doctor once or twice a month to have their vital signs taken versus doing it themselves at home twice a day over a month. Of related importance, is the flow of digital measurement readings from the medical/fitness device/wearable sensor to the patient’s Electronic Medical Record (EMR), to aid in Clinical Decision Support (CDS). In the end, it could be a normal reading, or an anomaly or something else, but it has a place in the continuum of the patient’s health and longitudinal medical record especially if it has been triggered by a health event or condition. Connecting the “dots” of data is what IoT medical nodes do best, that can lead to actionable outcomes as a result of analytic systems that marshal and process the data. On the cloud side, this has become easier in recent years with more provider’s adopting EMR systems as well as CDS systems. We are starting to see the shift towards smart IoT edge-nodes, which don’t blindly collect the “dots” but, instead, process data based on rules, triggers, and algorithms and reduce the amount of that data sent to the cloud.

Lastly, the author calls out motivation as a problem intrinsically tied to human psychology. With the IoT lens in mind, it should be understood that it is the patient’s responsibility to manage their healthcare. IoT features, applications and systems attempt to influence healthcare and fitness discipline from reactive to proactive, incorporating them as part of daily routine. Patients with chronic disease conditions such as hypertension, diabetes, and COPD, and who are committed to manage their health, do adhere to take their medications. This will become easier as the onset of multiple wearable sensor smart patches and garments that monitor and collect our vital signs become a part of our day-to-day lives.

Many companies are showing interest in making connected health care devices. Whether it’s a wearable sensor or smart patch which tracks your workout or a garment that monitors and collects a patient’s vital signs, IoT will bring improvements to healthcare. It is not a question of if it will take off, but when. Here is a sign of “Things” to come.

Also Read: Why Medical IoT Won’t Take Off

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Auto Introspection

Auto Introspection
by Bernard Murphy on 12-20-2015 at 4:00 pm
Categories: Automotive, Cadence, EDA

It is an indictment of our irrationality that our cars are now more health-conscious than we are. Increasingly safety-conscious readings of the ISO26262 standard now encourage that safety-critical electronics (anti-lock braking control for example) automatically self-test, not just at power-on but repeatedly as the car is in operation. Any reliability failure will be used to trigger a driver warning that a critical system may be performing below expectations and therefore the car must be taken in for service as soon as possible. We in contrast tend to monitor our health reactively only after something has gone wrong. Ah well – perhaps someday we will be as wise as our cars.

The Cadence Encounter Test family goes a long way to addressing these needs for cars and other safety-critical systems. Good health starts with being born healthy so the auto industry requires a very high standard for DPM (defects per million) in shipped silicon. Cadence has a strong solution in which test is integrated during Genus synthesis: scan of course and scan compression but also LBIST, MBIST and IEEE1500 wrapping to simplify core testing and isolate analog components in test.

In big digital companies, test is a domain staffed by a team of specialists skilled in all the arcane arts of scan, BIST and more. Automotive electronics development teams aren’t so lucky. Historically their content has leaned much more to big A, little D with minimal understanding of requirements for advanced DFT. As the digital content in auto electronics has exploded, their need for ease-of-use in insertion and optimization of test becomes more than a nice-to-have. The Cadence test solution is attracting an enthusiastic following because users are commenting that it is the most push-button flow they have seen. This also becomes incredibly important for non-experts to manage constrained test solutions: minimum number of test pins (even as low as one test pin), low DPM area, small pattern counts and more. All ho-hum to those big digital test teams but critical to these automotive teams feeling their way into DFT in a market setting ultra-high standards.

This handles the healthy neonate checks, but what about post-silicon self-test, the ongoing wellness checks? As I mentioned earlier, power-on self-test is already a requirement for critical systems, but the ISO standard also encourages diagnostic coverage requirements which repeatedly test as the car is being driven. This means that periodically your ABS controller goes off-line to check if it’s OK. That creates an interesting constraint – you’re happy that it’s checking itself frequently but you really don’t want it staying off-line for very long. Which in turn means that LBIST checking must be both high coverage and run very quickly.

Cadence Encounter Test addresses both of these problems. Since LBIST testing is based on random patterns, it is sensitive to random-resistant faults such as the output of a wide comparator which has a low probability of being triggered by random vectors. The software uses Random-Resistant Fault Analysis to correct for these cases, also Deterministic Fault Analysis which finds and corrects for generally hard-to-detect faults (those hard to detect even with directed tests). Both of these are used to drive insertion of test points which both improve coverage and reduce test time – as much as 50% reduced as reported by one Cadence customer. Your ABS controller can spend less time in introspection, which, all things considered, is probably better for your health.

Cadence is also increasing support for in-system test through their MBIST solution by allowing customers to add their own algorithms to test for new failure modes they may have discovered. I really like where Cadence is headed with this and their LBIST work. I have commented before that an important way for EDA to break out of its doldrums is to add value post-silicon. Encounter Test is breaking that trail and I hope other EDA domains will follow.

You can read more about the complete Cadence Encounter Test solution HERE.

More articles by Bernard…

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Calibre in the Middle of Semiconductor Ecosystem

Calibre in the Middle of Semiconductor Ecosystem
by Pawan Fangaria on 12-20-2015 at 12:00 pm
Categories: EDA, Siemens EDA

Albert Einsteinhad said, “In the middle of difficulty lies opportunity”. In today’s world dominated by technology, or I must say internet which has initiated collaborative information sharing, “leading from the middle” is the new mantra of life.
Continue reading “Calibre in the Middle of Semiconductor Ecosystem”

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The Cult of IoT! (FitBit)

The Cult of IoT! (FitBit)
by Daniel Nenni on 12-20-2015 at 7:00 am
Categories: IoT

Granted the word “cult” can have a negative connotation, especially when applied to small religious groups but cult can also mean a great devotion to a movement or intellectual fad. Some people call Apple a cult with Apple Stores being their Churches. If you look at the lines around the block or down the mall for new product releases the term cult can certainly come to mind. And that brings me to the cult of IoT and wearables.
Continue reading “The Cult of IoT! (FitBit)”

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Variation Aware FinFETs are Critical!

Variation Aware FinFETs are Critical!
by Daniel Nenni on 12-18-2015 at 4:00 pm
Categories: EDA, FinFET

As I mentioned in “EDA Dead Pool” acquisitions in our industry will continue at a rapid pace. The latest victim is 10 year old French company Infiniscale who was recently purchased by Silvaco. This was more of a “let’s put your product through our massive sales and support channel” kind of deal so it will be 1 + 1 = 3 accretive for sure. Plus, variation aware tools use SPICE licenses so it makes perfect sense for a company like Silvaco (SmartSPICE) to go into variation, absolutely.


“The increased variability associated with advanced processes result in increased yield risks that designers need to mitigate while they strive to meet aggressive power, performance and area goals,” said Infiniscale’s Chief Executive Officer Dr. Firas Mohamed. “Infiniscale invented a second generation of Monte Carlo analyses that helps designers meet these increasingly stringent goals, with a user-friendly variation-aware design methodology. We are proud of the opportunity to be part of Silvaco’s legacy of technology leadership and are deeply committed to working together to continue providing innovative solutions for our customers and the design community.”

“There is good synergy between Silvaco and Infiniscale, and this acquisition further advances Silvaco’s growth initiatives to provide our customers with a robust TCAD-to-signoff set of design tools,” said Silvaco’s Chief Executive Officer David L. Dutton. “Infiniscale’s impressive variation analyses technology strengthens Silvaco’s SPICE portfolio, which includes SmartSpice circuit simulator, EM/IR/thermal analysis, standard cell and memory characterization, bringing unique accuracy, performance and economic value to support our customers’ leading-edge IC designs. This acquisition increases our presence in the European market as the Infiniscale team will join our Grenoble, France site.”

There are four companies that play in the variation aware tool space:Solido Design, MunEDA, ProPlus, and Infiniscale. Notice none of the big four EDA companies (Synopsys, Cadence, Mentor, Ansys) compete in this area? Not yet anyway, so expect more acquisitions before #53DAC for sure.

What are the specific variation challenges FinFET designers face you ask? Great question, let’s start with PVT Corner Design at 16nm and 10nm. There are literally tens of thousands of simulation combinations to consider. You can either (1) simulate them all over a period of months with thousands of SPICE licenses or (2) you can guess at which ones to simulate or (3) you can use a variation tool to statistically tell you which ones you should care about.

Next is High-sigma Monte Carlo design. For SRAM and Standard Cells this is a no brainer since they are repeated thousands and thousands of times throughout designs and yield is extremely critical. Before FinFETs, designers would simulate to 3-sigma and extrapolate to High-sigma. If you try that with FinFETs either you will not yield or your design margins will not be competitive. Using HMC you can now do a year’s worth of simulations with a handful of SPICE licenses in a matter of hours or maybe days to get you up to 6 or 7 sigma with SPICE accuracy. Seriously, I have seen it done and know by experience that the top foundries and their biggest customers use variation tools for 16nm and 10nm SRAM and complex standard cells, absolutely.

Also Read: EDA Mergers and Acquisitions Wiki

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IEDM Blogs – Part 3 – Global Foundries 22FDX Briefing

IEDM Blogs – Part 3 – Global Foundries 22FDX Briefing
by Scotten Jones on 12-18-2015 at 12:00 pm
Categories: FD-SOI, Foundries, GlobalFoundries

While I was at IEDM I had an opportunity to sit down with Subramani (Subi) Kengeri, the Vice President, General Management, CMOS Platforms Business Unit and Jason Gorss from corporate marketing at Global Foundries (GF) for a briefing on GF’s new 22FDX process technology.

Subi told me his background was in design but that he is now the business unit head for Fab 1 in Dresden. The 22FDX platform is being developed to run in Dresden and will be the next generation process for that fab (Dresden most advanced process is currently a 28nm bulk planar process).

22FDX is targeted at mobile computing and the mobile requirements for cost, performance and power. Applications like the internet of things (IOT) will need ~$1 ASPs. Some of the key requirements include:

  • Cost.
  • Ultra-low power.
  • Security and privacy.
  • Always on sensors and modules.
  • Dynamic performance and leakage – low leakage for always-on and performance for short bursts.

Multi-patterning is driving up wafer costs. A design for a leading edge FinFET process costs $50-$80 million dollars for the design. To get a reasonable return at a 20% market share you are looking at ~$400 million dollars out of a market with a TAM of $2 to $3 billion dollars. Not many opportunities are that large.

FinFETs are used for the highest performance applications but they consume slightly higher power due to 3D capacitance. For everything else planar FDSOI is the best.

The goal with 22FDX was to maximize the shrink from 28nm, while minimizing double patterning. 22FDX can provide “FinFET like performance” while operating down to 0.4 volts. It is the only technology known today that can operate at that low of a voltage. The technology also offers software tuning of the body bias so that post silicon tuning can be used to dial in performance and recover weak SRAM bits.

My background is in process technology and I was very interested to dig in to how this process is designed. As previously stated GF wanted to minimize multipatterning.

  • The front-end-of-line (FEOL) transistor is licensed from ST Micro’s 14nm FDSOI process.
  • Middle-of-line (MOL) includes 2 metal layers (M1 and M2) with double patterning by litho-etch-litho-etch (LE2).
  • Back-end-of-line (BEOL) is all single patterned to keep down costs.

The process is basically a 14nm FEOL with a 22nm BEOL to minimize costs.

There are four versions of the process:
[LIST=1]

  • 22FDX-ulp – ultra-low power – special SRAM and doping optimization.
  • 22FDX-uhp – ultra-high performance – BEOL stack optimization and MIM capacitors.
  • 22FDX-ull – ultra-low leakage – adds dual gate oxide to create a thick oxide ultra-low leakage device.
  • 22FDX-rfa – RF & analog – passive devices and ultra-thick metal.

    The 22FDX process offers a wider range of threshold voltage/leakage options than any other known technology. As I will discuss in my forthcoming blog on Greg Yeric’s plenary talk, options on voltage/leakage are very important to designers.

    The use of body biasing in this technology is a key to its performance. Forward biasing the body (FBB) drives up performance and reverse biasing the body (RBB) provides the lowest leakage. FBB and RBB can be done on a block by block basis on a single die. For example, an IOT device might have an always on “watchdog” processor in a RBB block to minimize power. The rest of the blocks on the chip could be kept off until needed. Additional blocks could include a FBB processor block for high performance and an integrated RF block for off-chip communication. This unique feature of 22FDX allows the integration onto one chip of functions that would typically require separate chips built with different technologies.

    22FDX is 50% faster and 18% lower power than a 28nm high-k metal gate (HKMG) technology or 47% lower power at the same frequency. At 0.4 volts an ARM core can run at 520MHz while consuming 92% less power! The RF performance is good enough to implement WiFi or Bluetooth without the need for an external power amplifier.

    In terms of the schedule, design kits for 22FDX are available now and risk production is scheduled to begin mid-2016.

    Long term FDSOI can scale down to 10nm but they haven’t decided on the exact “node” for a follow on process. The 22FDX is kind of an intermediate process between 28nm and 14nm with better performance than 28nm and lower cost than 14nm. Presumably the next version will be positioned between the 14nm and 10nm FinFETs for performance and cost. Subi said the next generation process would likely be in Dresden.

    You can view the Global Foundries 22FDX presentation HERE.

    Also Read: IEDM Blogs – Part 2 – Memory Short Course

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    Mass customization coming to MEMS?

    Mass customization coming to MEMS?
    by Don Dingee on 12-18-2015 at 10:00 am
    Categories: EDA, IoT, Siemens EDA, Tanner EDA

    With the industry abuzz about the Apple purchase of a Maxim Integrated fab as a potential R&D facility for MEMS design, it begs the question: is creating a MEMS device that easy?

    MEMS technology is approaching the same fork in the road where digital design encountered LSI four decades earlier. Continue reading “Mass customization coming to MEMS?”

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    Slinging Stones at the Data Center Semi Goliaths

    Slinging Stones at the Data Center Semi Goliaths
    by Maury Wood on 12-18-2015 at 7:00 am
    Categories: Arm, IP

    For those not aware, there is quite a battle brewing in data center wired communication segment (across which most wireless data traffic traverses). A primary impetus driving the competitive positioning is the recent commercial availability of single lane 25 Gbps serdes (serializer / deserializer) channels in 28 nm CMOS from several suppliers.

    Most mainstream data centers today use 1 Gbps Ethernet over copper (1000Base-T) to interconnect server nodes to top of rack (TOR) aggregation or leaf switches, with 10 GbE over copper (10GBase-T) an upgrade path that has seen relatively slow industry adoption. For higher bandwidth uplinks between aggregation and core switches, four 10 GbE lanes on a quad SFP (QSFP) optical link provides 40 Gbps of connectivity, consuming four switch ports on both ends. Using the same approach on a larger QSFP28 optical connector, ten 10 GbE lanes provides 100 Gbps uplink connectivity to the data center core spine switches.

    By contrast, the 25 Gigabit Ethernet Consortium specification, driven by Broadcom, Cisco, Dell, Mellanox and others, 50 GbE connectivity requires only two ports, and 100 GbE connectivity requires only four ports, enabling very attractive total port ownership costs (including reduced cable costs), likely sufficient to further stunt 10 GbE uptake. Striking about this paradigm shift is that Broadcom, the 800 pound gorilla of the ethernet chip world with $8.4B in 2014 revenue, is seeing a fresh challenge to its switch dominance by much smaller companies, while its traditional 1 GbE chip competitors, Marvell and Realtek, are relative “no shows” in the race to field 25 and 50 GbE switch ports using 25 Gbps serdes technology.

    Cavium, one of the new tigers in data center semiconductors, is an impressive example. Cavium acquired Xpliant for less than $100M last year, and introduced the CNX880XX family to the market quickly thereafter. Maximum Xpliant Ethernet bandwidth is 3.2 Tbps across 128 ports (using 25 Gbps serdes), same as Broadcom’s flagship Tomahawk switch chip. Cavium’s programmable Xpliant Packet Architecture is claimed to be friendlier to Software Defined Networking specifications such as OpenFlow.

    Cavium is also offering a very competitive ARMv8 server processor family, the ThunderX, with up to 48 custom cores, dual socket coherency, and many other Xeon-class server processor features. Intel announced the 14 nm Xeon D SoC processor family at least in part as a competitive response to ThunderX and Applied Micro’s X-Gene multi-core ARMv8 server processor. Cavium also markets impressive embedded processor, security processor and network processor product portfolios. All this innovation from a company with $420M run-rate annualized revenue.

    This theme of undaunted ferocity repeats with Mellanox (current annualized revenue less than $800M). They are best known for very low port latency (down to 90 nsec) InfiniBand adapters and switches for both processor and storage connectivity. InfiniBand is more prevalent than Ethernet in high performance computing applications such as supercomputers and high frequency trading machines. Their latest Enhanced Data Rate products also use 25 Gbps serdes, with as many as 144 port instantiations per chip, same as Broadcom’s latest BCM88770 “FE3600” Ethernet switch fabric device, providing 3.6 Tbps of packet bandwidth.

    Mellanox is gaining share in the data center Ethernet segment as well, with their eighth generation 3.2 Tbps class Spectrum switch chip. To put this into perspective, mighty Intel’s highest performance Ethernet switch chip, the FM6764, offers 640 Gbps port bandwidth with 400 nsec cut-through latency. Intel reported $56B in 2014 revenue, making even the merged Broadcom+Avago operation seem small by comparison. Intel recently announced their Omni-Path Architecture, a new data center routing fabric designed to address scalability and other limitations associated with InfiniBand, and featuring 25 Gbps serdes. While this announcement raises the stakes for Mellanox, most markets generally want to see at least two competitive alternatives, and realistically it will take the Omni-Path ecosystem several years to become firmly established.

    Cloud computing data centers equipment is one of the fastest growing semiconductor application segments today and into the foreseeable future. Despite the ongoing and unprecedented level of consolidation in microchip industry, it is exciting to see small dynamic companies like Cavium and Mellanox present fresh challenges for established goliaths such as Broadcom and Intel.

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    Hyperloop: Faster Than the Shinkansen

    Hyperloop: Faster Than the Shinkansen
    by Daniel Payne on 12-17-2015 at 4:00 pm
    Categories: General

    In 1987 I made my first trip to Japan for business, then rode in my first high-speed train on the fabled Shinkansen (aka bullet train) traveling up to 200 mph on the way from Tokyo to Kyoto. Compared to the USA, our engineering friends in Japan have the most futuristic high-speed trains in the world. Today there’ s talk about another high-speed traveling mode similar to a train but running inside of tubes, dubbed the Hyperloop by Elon Musk, the billionaire made famous for SpaceX, Tesla Motors and SolarCity. The planned top speed for the Hyperloop is a staggering 760 mph, which is faster than commercial jets.

    Musk created an open source design challenge back in 2013 to create a 28 passenger pod that travels through tubes, powered by solar, and costing only $20 for a ticket from LA to SFO, while taking just $6 billion to construct. Two startups are making a quest for this project: Hyperloop Transportation Technologies (HTT) and Hyperloop Technologies Inc (HTI). At the start of 2015 Musk added plans to build a Hyperloop test track and announced a contest in 2016 where you need to build a half-scale pod. There are some 318 teams from around the world participating with pod designs.

    HTT won’t spend their efforts on the 2016 contest and they pay their engineers equity in exchange for 10 hours per week, allowing them to keep their day jobs in high tech. Ansys has partnered with HTT to run simulations of the fluid dynamics required for the Hyperloop concept. HTT has plans to build their own Hyperloop in Quay Valley, California with pod speeds up to 300 mph, quite a bit short of the 760 mph dream goal.


    HTT Concept

    HTI is raising some $80 million in its next round of growth, and they are partnered with China Railway International USA. So there are two companies kind of racing to implement the first Hyperloop system.


    HTI’s levitation ring

    Concerns about Hyperloop include:

    • Safety
    • Costs
    • Passenger experience in a confined pod
    • Infrastructure

    At the University of Illinois in the MechSE curriculum you can study the Hyperloop for credit, so Universities around the globe are getting energized with the entire high-speed transportation concept.

    I’m all for the private sector innovating and developing travel concepts like the Hyperloop, however I’d be upset if our Federal or State governments started throwing my taxpayer dollars at such a high risk venture. I was quite skeptical of the concept of powering a transportation system of this size and weight using only solar power, and then keeping the tubes perfectly aligned across any real geography, especially earthquake-prone California. The Hyperloop almost reminds me of the earlier promise of mono-rail travel where we just see relatively short distance systems in use at novelty locations like Disneyland, Seattle and some airports.

    Read the full WSJ article, “The Race to Create Elon Musk’s Hyperloop Heats Up“.

    Further Reading: