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Reinventing Power Management ICs for Mobile

Reinventing Power Management ICs for Mobile
by Karim Khalfan on 02-29-2016 at 7:00 am

Semiconductor startups are becoming rather rare in Silicon Valley, otherwise known as the cradle of technology innovation. In an era where social media and cloud-based software startups are sprouting in every nook and corner of the Valley, it is extremely difficult to get venture capital funding for semiconductor startups, in part due to the high capital investment. Yet there is hope that this may change. The battery-centric power conundrum is now opening up a new window of opportunity for semiconductor startups in the area of space-constrained mobile and wearable devices.

Lion Semiconductor, for instance, is a startup that is trying to reinvent the power management IC (PMIC), one of the biggest chips on a mobile phone. The San Francisco–based company claims to have reduced the PMIC footprint and thickness by two to three times, which, in turn, will allow mobile handset manufacturers to make the battery larger and longer-lasting.


Figure 1: Lion Semiconductor is developing smaller, thinner PMICs for mobile systems

The timing for Lion Semiconductor seems to be just right. Mobile consumables are trending and it is becoming extremely critical to manage the different voltages in devices and to manage the power with minimal energy loss. With increases in design complexity, lower technology process nodes, lower noise thresholds and the increase of analog and RF components in the SoC, there is a growing need for proper generation and control of low voltages without any significant power loss.

The constant overheating issues in smartphones are a testament to how a more innovative PMIC solution could help mobile phone hardware create a better balance between performance and power. In a wearable device, the value proposition of a smaller PMIC is even more crucial: it will lead to a smaller wearable device itself.

Reinventing PMIC
In a mobile handset, the power management IC takes voltage from the battery and delivers it to different chips across the smartphone design footprint. However, the use of discrete components like inductors creates inefficiencies inside the PMIC. The alternatives, like low-drop-out regulators (LDOs), come with lower efficiencies, while the use of switching regulators makes PMICs bulky and expensive.

Lion Semiconductor’s answer to this power puzzle: a new breed of power management ICs that use a different circuit design and manufacturing process to meet the more demanding mobile specifications. The power converter design would not require any discrete passives-like inductors (like LDOs), but would offer the efficiencies of switching regulators, merging the advantages of LDOs and switching regulators.

Lion Semiconductor’s co-founder and CEO, Wonyoung Kim, designed an integrated voltage regulator when he was a graduate student at Harvard University. He was then aiming to create a PMIC that does not require discrete passive components. The firm’s other co-founder, Hanh-Phuc Le, was carrying out similar work at the University of California, Berkeley.

Another Berkeley Ph.D. student, John Crossley, later joined them and a PMIC company specializing in solutions for mobile devices was born. Here, it’s worth noting that the battery in a smartphone has to serve a wide range of input and output voltages, and that it is challenging for the PMIC to maintain high efficiencies across this wide range.


Figure 2: The DC-DC converter chip that Kim developed at Harvard a few years back

Lion Semiconductor is tackling that challenge head-on through their proprietary technologies in circuit design and process technology. Lion Semiconductor has successfully verified several fully-functional silicon prototypes and is preparing to start sampling to customers soon.

Do small design startups also need data management tools?
Kim and his friends at Lion Semiconductor had been using the Cadence Virtuoso analog/mixed-signal design platform since their college days and it was only natural that they turned to Cadence for EDA tools. In addition to other tools, Lion Semiconductor uses ClioSoft’s SOS SoC design data management tool, which is integrated into the Cadence Virtuoso platform.


Figure 3: ClioSoft Inc. authored the chapter on SoC design data management in the “Mixed-signal Methodology Guide” published by Cadence

Does it seem strange for a semiconductor chip startup like Lion Semiconductor to use a sophisticated design data management tool created primarily for the semiconductor industry?

“Not really,” said John Crossley, now Lion Semi’s vice-president of engineering. “It just shows how crucial it is to efficiently manage data in the development of a complex chip. Inevitably, the tight schedules in the mobile world and the very short market windows make it imperative that engineering teams are working on the correct version of design data and that all design team members are in sync.”

The Fremont, California–based ClioSoft helps companies like Lion Semiconductor through a flexible licensing program that features low overhead and greater setup and administration support for startups. The SOS design management platform from ClioSoft has built-in integrations with EDA tools and a flexible architecture, making it easily customizable for small and big semiconductor companies alike for their complex design flows.

Lion Semiconductor is planning to set up a design center overseas, which would make it even more crucial to have an efficient design data management system in place.

Also Read

Evaluating the performance of design data management software

The Case for Data Management Amid the Rise of IP in SoCs

ClioSoft SOS v7.0: Faster, Smarter and Stronger


Millennial Tyranny, Tattoos and Scions!

Millennial Tyranny, Tattoos and Scions!
by Roger C. Lanctot on 02-28-2016 at 4:00 pm

Millennials tiring of TV commercials for erectile dysfunction and rheumatoid arthritis will have their revenge soon enough. The population bulge of under-35-year-olds is making its way through the demographic grinder and will soon be reformatting everything from business models and television advertising budgets to the available goods and services on the market.

Depending on who you ask, the Millennial designation encompasses as many as 90M Americans, more than 10M more than the current population of Boomers. Marketers are in a tizzy to tease out the brand and behavioral preferences of these consumers with companies such as Whole Foods threatening to open mini-tattoo parlors in some of their stores in a bid to enhance their edginess.

Desperate Whole Foods Will Offer Tattoos to Hipsters” – NYPost

This wave of new potential car buyers is of particular concern to the automotive industry in the context of a marked decline in driver’s license ownership within this increasingly dominant demographic cohort. According to research recently published by the University of Michigan’s Transportation Research Institute, nearly every demographic segment is showing declines in the possession of driver’s licenses, but Millennials are showing the steepest decline.

SOURCE: UMTRI

Auto makers have taken the hint and are scrambling to prepare for a world of alternative transportation options including ride hailing services, ride sharing, bike sharing, public transportation and, dare I say it, walking. Perhaps the most absurd example of this scramble was reported by the New York Times describing researchers working on behalf of Ford riding borrowed bicycles to get around Chicago.

In addition to being the largest demographic segment, Millennials are also the most diverse, which is giving marketers even greater headaches. This ultimately means that every expert on Millennials will be correct even though many of them will disagree.

I was particularly concerned to see an Experian report of automotive brand indexing for Millennials. The brands preferred by Millennials almost directly inverted the sales ranking of the brands in question – with the now-defunct Scion as the top indexing brand.

SOURCE: Experian SEMA presentation – November 2015

Notably missing from this roster of brands are Chevrolet, Ford, Lincoln, Cadillac GMC and Buick – as well as Acura, Infiniti, Lexus, BMW, Mercedes, Audi and a few others. Perhaps it is no surprise that both Ford (FordPass) and General Motors (Maven/Lyft) have launched alternative transportation initiatives to connect with Millennials.

Maybe it’s best that we keep our heads as marketers, take a deep breath and remind ourselves that Millennials for all their tattoos and ride sharing are human beings like everyone else. They’re a little more accepting of and interested in technology than the rest of us (they own more smartphones), but they, too, have limited means and can readily see the high cost of buying, owning, driving, parking, insuring and servicing cars.

If we can help Millennials mitigate the cost of owning, parking, insuring, servicing and buying a car, then I suspect Millennials will keep buying cars. If Uber-ing or Lyft-ing around town is cheaper and, most important, more convenient and sensible than owning a car, the outcome is a foregone conclusion. Millennials are pretty good at math.

There is nothing exotic about trying to save money and time and avoid inconveniences. If we keep it simple I think we can be successful selling cars and just about anything else to Millennials. And are we really going to miss those commercials for rheumatoid arthritis and erectile dysfunction?

More articles from Roger…


Life, the Universe and Everything

Life, the Universe and Everything
by Bernard Murphy on 02-28-2016 at 12:00 pm

In Douglas Adams’ iconic series A hitchhiker’s guide to the galaxya super-intelligent species created a super-powerful computer called Deep Thought to answer the ultimate question – what is the meaning of life (and the universe and everything)? Life imitates art so it should come as no surprise that a team in London founded a venture in 2010 called (I’m sure intentionally) DeepMind. The company was acquired by Google in 2014.

The team’s most widely-publicized achievement was beating a professional Go player with their AlphaGo program, which many consider a superior accomplishment to DeepBlue’s victory over Garry Kasparov in chess – in part simply due to the larger size of the board (19×19 versus 8×8), making a brute-force state-space search challenge even more wildly impossible. AlphaGo is also different in using deep neural networks to guide play.


The approach starts with an expert-trained policy network which assesses best moves to play from any given position. This is complemented by a value network which assesses a score for the position after the move. AlphaGo then does something quite unique – it plays thousands of games against itself, from the current position, refining these two networks to finally decide which move to make next. This self-training capability, at each move in the game, is what enables it to manage this vast search space and make it competitive against world-class players.

AlphaGo is implemented in Google Cloud across distributed CPU and GPU platforms (GPUs/DSPs are good for neural nets) – no indication of specialized hardware. Hardware-assist would presumably be possible, though is not clearly necessary.

In a more practical vein, DeepMind as an organization also has a big focus on healthcare. You’re probably thinking “ah-ha – deep reasoning for diagnosis”. You would be wrong as far as I can tell, at least today (though I’m sure there are plans). They have two products, Streams and Hark. Streams enables streaming clinical data (e.g. lab results) directly to mobile platforms. Hark is an early-stage clinical task management app – from what I have seen a sort of calendar of next tasks for a nurse or doctor. While neither of these apps seems very revolutionary, medical professionals involved in the development say that simply streamlining information flow and making sure tasks are not dropped will significantly improve patient outcomes.

What I find quite interesting about both of these apps is that they were developed in close collaboration with doctors and nurses at the Royal Free Hospital and at St. Mary’s Hospital, both in London. This is the right way to develop any app – directly with the people who will use it. And having built a level of trust, I’m sure DeepMind will have a much easier time introducing diagnostic aids based on deep reasoning.

Finally, the DeepMind team has given a lot of thought to data privacy and security. They commit that for UK patients, data is stored only in the UK and never linked to Google accounts, products or services – which should create an interesting challenge for Google who presumably plan synergies in the acquisition. However this pans out, looks like Google is developing an interesting direction in e/mHealth.

You can learn more about DeepMind HERE.

More articles by Bernard…


HW Emulator Apps Open Doors to Entirely New Uses

HW Emulator Apps Open Doors to Entirely New Uses
by Tom Simon on 02-28-2016 at 7:00 am

When the topic of hardware emulation comes up, thoughts of big iron customarily come to mind. However, hardware emulation has evolved significantly and now there are other important traits that distinguish the offerings in this area. For a very long period of time emulators provided primarily a method to accelerate gate level simulations. Advances in capacity and performance eventually allowed emulators to also be used for HW/SW co-verification.

According to Jean-Marie Brunet, Mentor’s Emulation Division Marketing Director, we now have reached the fourth age of emulation – the Application Age. The first three were ICE Age, Acceleration Age, and the Virtualization Age. Over recent years Mentor has been working on making their Veloce emulation platform useful for many new tasks. Moving it to the data center and allowing it to work in conjunction with rack mounted servers for tasks such as compilation has made using emulation a lot easier and faster.

They also made it possible for multiple users from around the world to share a single emulator, thus increasing the efficiency and cost effectiveness of their solution. However, to understand how their latest ‘age’ of emulation works we have to start thinking of the system as a platform, with hardware, networking and, most importantly, with an operating system – one that allows applications for performing specific tasks.

Once it is clear that emulation can serve as a general purpose accelerator for many design verification tasks, the range of potential applications for it expands dramatically. The Veloce emulators can already handle large gate counts, from 250M gates up to 2B gates in their top of the line offering, Double Maximus. Expanding the range of tasks these systems can accomplish should be a game changer.

A good analogy is the development of the cell phone. Having the first phones that allowed mobile calls was considered amazing in their time. But now we have come to see our phones as being capable of many more things we could not previously imagine. So it is for emulation.

Mentor’s strategy for emulation is to use it for ‘de-risking’ design. One of the three VeloceApps they just announced on February 25[SUP]th[/SUP] is for DFT. Instead of verifying test patterns using software based DFT simulations, now Veloce can be used to speed this up thousands of times, ensuring that DFT simulations are completed in seconds or minutes instead of days.

One of the other VeloceApps just announced is an optimizer that work on large multi-clock SOC emulation. This app recognizes design attributes that can slow emulation, improving emulation runtime. Mentor claims that in certain cases user can expect to see ~50% reduction in emulator runtime.

The third VeloceApp that was introduced in this announcement is for ICE. Traditionally is it hard to replicate errors in an ICE environment because of non-deterministic behavior. Through the use if this App, an entire ICE run can be captured so that there is 100% visibility. Then the engineer can use the replay data base to step though the bug or fault to identify its cause. Having this take place in software means more controllability and better debugging capabilities are available.

Also, in the latest Veloce OS release, OS3, there have been improvements in the gate level compile flow, making it more efficient. Another big performance improvement was made in reducing the processing time required to convert raw test run results into viewable waveforms. Mentor is expecting users to see a 2X improvement as a result of hardware and software enhancements.

The Mentor announcement includes other improvements in the Veloce emulation solution. The full announcement can be found here. Emulation has moved from being an exotic solution for a narrow range of verification tasks, to become an almost necessary element of any large SOC’s verification flow. Expanding the applications is a smart of way making emulation solutions even more useful and valuable.

More articles from Tom…


2015 semiconductor market flat, 2016 looking somewhat better

2015 semiconductor market flat, 2016 looking somewhat better
by Bill Jewell on 02-27-2016 at 7:00 am

The 2015 semiconductor market finished with a 0.2% decline from 2014, according to World Semiconductor Trade Statistics (WSTS). Optimists will round this to flat with 2014. The flat 2015 follows healthy 9.9% growth in 2014. Going into 2015, forecasts were in the range of 3% to 11%. We at Semiconductor Intelligence were at the high end, with our December 2014 forecast at 11.0%. The lowest forecast was from WSTS in December 2014 at 3.4%. Thus the WSTS forecast came closest to the final 2015 number. This is based on available 2015 forecasts released in the few months prior to the release of the January 2015 market data from WSTS.

The fourth quarter 2015 semiconductor market declined 2.8% from the third quarter, the largest fourth quarter decline in four years. The outlook for the first quarter of 2016 looks weak, based on revenue guidance from major semiconductor companies. Of ten major companies providing guidance, nine expect revenue declines in 1Q 2016 versus 4Q 2015. The declines range from a slight 0.2% from Renesas to an 11% decline from MediaTek. Infineon was the only company projecting an increase at 3%. Samsung did not provide specific revenue guidance for its semiconductor business, but expects “slow demand under weak seasonality.” The recent NXP/Freescale and Avago/Broadcom mergers do not allow for comparable revenue guidance for these companies. The weighted average guidance for the ten companies is a 6% revenue decline in 1Q 2016. Most of the companies provided a range of guidance for 1Q 2016, with a weighted average worst case decline of 10% and a best case decline of 3%.

[TABLE] align=”center”
|-
| colspan=”3″ style=”width: 430px; height: 33px” | Key Semiconductor Company Revenue
|-
| colspan=”3″ style=”width: 430px; height: 21px” | Change versus prior quarter in local currency
|-
| style=”width: 215px; height: 21px” |
| style=”width: 107px; height: 21px” | Reported
| style=”width: 107px; height: 21px” | Guidance
|-
| style=”width: 215px; height: 21px” | Company
| style=”width: 107px; height: 21px” | 4Q15
| style=”width: 107px; height: 21px” | 1Q16
|-
| style=”width: 215px; height: 21px” | Intel
| style=”width: 107px; height: 21px” | 3.1%
| style=”width: 107px; height: 21px” | -6.1%
|-
| style=”width: 215px; height: 21px” | Samsung
| style=”width: 107px; height: 21px” | 3.0%
| style=”width: 107px; height: 21px” | n/a
|-
| style=”width: 215px; height: 21px” | SK Hynix
| style=”width: 107px; height: 21px” | -10.3%
| style=”width: 107px; height: 21px” | n/a
|-
| style=”width: 215px; height: 21px” | Qualcomm
| style=”width: 107px; height: 21px” | 5.8%
| style=”width: 107px; height: 21px” | -8.2%
|-
| style=”width: 215px; height: 21px” | Micron Technology
| style=”width: 107px; height: 21px” | -6.9%
| style=”width: 107px; height: 21px” | -9.0%
|-
| style=”width: 215px; height: 21px” | Texas Instruments
| style=”width: 107px; height: 21px” | -7.0%
| style=”width: 107px; height: 21px” | -6.9%
|-
| style=”width: 215px; height: 21px” | Toshiba
| style=”width: 107px; height: 21px” | -10.4%
| style=”width: 107px; height: 21px” | -3.5%
|-
| style=”width: 215px; height: 21px” | Infineon
| style=”width: 107px; height: 21px” | -2.6%
| style=”width: 107px; height: 21px” | 3.0%
|-
| style=”width: 215px; height: 21px” | STMicroelectronics
| style=”width: 107px; height: 21px” | -5.4%
| style=”width: 107px; height: 21px” | -3.0%
|-
| style=”width: 215px; height: 21px” | MediaTek
| style=”width: 107px; height: 21px” | 8.3%
| style=”width: 107px; height: 21px” | -11.0%
|-
| style=”width: 215px; height: 21px” | Renesas
| style=”width: 107px; height: 21px” | -9.2%
| style=”width: 107px; height: 21px” | -0.2%
|-
| style=”width: 215px; height: 21px” | NVIDIA
| style=”width: 107px; height: 21px” | 7.4%
| style=”width: 107px; height: 21px” | -10.1%
|-

Recent forecasts for the 2016 semiconductor market range from a 1.5% decline from IBS to a range of 10% to 14% growth from Objective Analysis (shown as the average of 12% on the chart). Our latest forecast at Semiconductor Intelligence is 3.0% growth. We are assuming a decline of about 5% in 1Q 2016, healthy quarter-to-quarter growth in 2Q 2016 and 3Q 2016, and a mild seasonal decline in 4Q 2016.


The declines in 4Q 2015 and 1Q 2016 will make it difficult for the 2016 semiconductor to grow above mid-single digit rates. However there are signs the 2016 semiconductor market will be stronger than 2015. Gartner’s January 2016 forecast calls for the combined PC and Tablet markets to rebound from a 10% decline in 2015 to a modest 0.8% decline in 2016. Gartner expects mobile phone growth to pick up slightly from 1.6% in 2015 to 2.6% in 2016. The January GDP forecast from the International Monetary Fund (IMF) projects 2016 World GDP will grow 3.4% compared with 3.1% in 2015. Although China’s GDP growth is expected to slow from 6.9% to 6.3%, this is more than offset by accelerating growth in advanced economics (including the U.S., Euro area countries, and Japan) and improved growth for emerging economies such as India and Southeast Asia.

[TABLE] border=”1″
|-
| colspan=”4″ style=”width: 623px” | Annual Growth Rate Forecasts
|-
| style=”width: 155px” |
| style=”width: 155px” | 2015
| style=”width: 155px” | 2016
| style=”width: 155px” | Source
|-
| style=”width: 155px” | PC+Tablet units
| style=”width: 155px” | -10%
| style=”width: 155px” | -0.8%
| style=”width: 155px” | Gartner, Jan. 2016
|-
| style=”width: 155px” | Mobile Phone units
| style=”width: 155px” | 1.6%
| style=”width: 155px” | 2.6%
| style=”width: 155px” | Gartner, Jan. 2016
|-
| style=”width: 155px” | World GDP
| style=”width: 155px” | 3.1%
| style=”width: 155px” | 3.4%
| style=”width: 155px” | IMF, Jan. 2016
|-

The latest data from December 2015 on electronics production by country shows China growing at around 10%, slightly slower than in previous years but still a strong rate. The U.S. has picked up to 6.5% growth from below 1% growth in early 2015. Japan and Taiwan are showing declines in electronics production, but the declines are less severe than earlier in 2015.


China unit production of key electronic devices rebounded at the end of 2015, as shown below. Mobile phone unit production three-month-average change versus a year ago peaked at 25% in mid 2014 before sliding to double-digit declines in mid 2015. Mobile phone growth climbed to 15% in December 2015. TV unit production growth was 13% in December 2015 after averaging low single digit growth in the first half of 2015. PCs are the only key electronics category which has not recovered, with December 2015 down 15%. The weak PC production in China is due to a weak PC market and PC production shifting to other countries such as Mexico, India and Vietnam.


2016 will not be a strong year for the semiconductor market, but all key indicators point to a better year than 2015.


Aldec reprograms HES7 for AXI4 speed

Aldec reprograms HES7 for AXI4 speed
by Don Dingee on 02-26-2016 at 4:00 pm

FPGA-based prototyping firms are all grappling with the problem of higher speed connectivity between a development host and their hardware. Aldec is announcing their solution at DVCon 2016, turning to an AMBA AXI4 interface bridged into a host with PCIe x8.

Faster host interfaces deliver dual benefits in FPGA-based prototyping. First is the FPGA configuration itself – to program a huge Xilinx FPGA (or more than one) means shipping a large file from the host down to the prototyping hardware. Second is at run time, where co-simulation runs on the host using transactors to control hardware execution in FPGAs. This hybrid solution allows users to run familiar visualization tools at much greater speeds than possible with host-based simulation alone, enabling more extensive verification testing.

What bus should be used to do that? In the not-too-distant past, people were turning to proprietary interfaces to the FPGA-based prototyping system, but those days are over. PCIe is ubiquitous in modern PC platforms and offers plenty of throughput in wider link widths. PCIe IP now widely available in FPGA form thanks to efforts from Xilinx, PLDA, CAST, and others. In some cases, where the SoC design is intended to run on PCIe, that interface might be carried through directly into the FPGAs on the prototyping platform.

A broader range of SoC designs does not contain PCIe at all. Most IP for ASICs today uses the AMBA AXI interconnect, not only for ARM cores but for other core architectures and peripherals. For those reasons much of the FPGA world has also turned to AXI. Xilinx has put extensive efforts into AXI4, taking advantage of its higher performance streaming and memory mapping capability. One IP protocol in the FPGA-based prototyping platform eases the learning curve, makes integration much easier, and offers the throughput and control features necessary for interaction with the host-based simulation package.

When Aldec said they used a non-proprietary backplane connector on their HES7XV4000BP, they meant it. Each of these edge connector slot cards carries one Xilinx Kintex-7 FPGA in a pre-defined configuration for host interfacing, and two Xilinx Virtex-7 FPGAs in user-defined configurations for the design under test. We haven’t seen the actual demo that Aldec will be showing at DVCon, but we have seen the documentation for the HES7ProtoAXI solution.

Without changing the hardware – after all, it is three FPGAs and can be reprogrammed – Aldec is launching a new software lob they refer to as HES7.ASIC.Proto2016.01 to create standard interfacing. The host interface to the Kintex-7 FPGA is now PCIe x8 (on that non-proprietary connector), offering transfer rates of 2GB/s into the card. Interfacing from the Kintex-7 to the two Virtex-7 FPGAs, and the connection between those two parts, is now AXI4.

It’s fast in terms of hardware bandwidth. The AXI4 connections into the DUT logic are 256 bits wide running at 125 MHz. Aldec has also taken care of all the address remapping for transactions, using that DDR3 memory DIMM on the board. The rest is business as usual – there is a C++ API that the testbench on the host uses to create read and write transactions, now in theory running much faster over the PCIe x8 and AXI4 interfaces.

I expect Aldec will show just how much faster this is for co-simulation in their demonstration. If you’re at DVCon at the DoubleTree in San Jose next week, drop by the Aldec booth #602 and see this solution. For more on the concept including the Getting Started guide (one-time registration for download), visit the Aldec site:

Aldec to unveil HES-7 High-speed AXI Transmission Channel at DVCon 2016

More articles by Don Dingee…


HW/SW Interfaces for Portable Stimulus

HW/SW Interfaces for Portable Stimulus
by Pawan Fangaria on 02-26-2016 at 12:00 pm

With growing size and complexity of SoC, the semiconductor community is realizing the growing pain of verification. The cost of SoC verification grows exponentially with design size. Moreover, there is no single methodology for verifying a SoC; multiple engines are used in different contexts through different verification flows. Also, design verification methodology changes from low level design up to the system level. This keeps multiple teams engaged in doing more or less similar things in different contexts, being in silos without any effective communication between them.

It’s apparent that a significant portion of verification cost is due to duplication of efforts between different test methodologies. Currently, software driven verification methodology is being looked at as the top-down approach which could prove worthy to abstract tests at system level and map them to different verification platforms through portable code. This approach can provide a large productivity through reuse of tests, provided they can be shared across multiple platforms in standard formats.

Wait, it’s not only about test duplication. When we talk about software driven verification methodology, we must check deeper into lower levels to understand what drives hardware-software interfaces. Today, there are multiple versions of software in use for system modelling, RTL verification, bare-metal driver for SoC bring-up, and OS driver. These different versions of driver software are being created by different teams (in different geographies and even different organizations) in different languages for almost same functionality under different operating environments. There is a lot of duplication of effort here in software development too. Note that the lack of a common formal specfor the hardware-software interface (ideally to be shared by different teams) adds to the problem.

Recently, Accelleraannounced the formation of Portable Stimulus Working Group (PSWG) with participation from the leaders in EDA and semiconductor industry. The charter of this group is to develop a Portable Test and Stimulus Standard for defining a common specification across all levels under different configurations that can be shared across the industry between different verification platforms.

It’s interesting to learn about a variety of companies (in semiconductor and electronics world) joining hands together to realize the PSWG strategy on a larger scale. Vayavya Labs, a company delivering embedded system design tools and solutions for last several years has joined the PSWG initiative to deliver a common standard for Hardware/Software Interface (HSI) specification.

Vayavya has immense expertise in device driver and firmware development, hardware board bring-up, OS porting, hardware modelling & prototyping. Driven by this expertise, Vayavya counts several Semiconductor, IP and EDA companies as its customers for hardware-software co-verification, embedded software development, system design, and so on.

Vayavya Labsis headquartered in India with its subsidiary, Vayavya Labs Inc. in USA. Their technology is based on important patents filed by them in USPTO. I will talk more about Vayavya later. For now, let’s review what Vayavya is delivering to PSWG and how it will benefit the overall semiconductor industry.


Vayavya proposes a standard specification language to capture hardware-software interface. Vayavya’s contribution in PSWG is derived from their own language called DPS for specifying Hardware/Software Interface. The Device Programming Sequence (DPS) captures device programming aspects such as register meta-data and access, device capabilities and configurations, FIFO management, descriptor management, interrupt management, programming sequences, and so on. It is worth emphasizing again that DPS is much more than just a simple register specification.

The Runtime Specification (RTS) captures details of the operating environment. The DPS and RTS for a particular device driver are fed to an automated tool that generates the device driver for the target operating environment.


To put the things in perspective, this methodology allows hardware and software teams to focus on writing the DPS and RTS specifications only and not duplicate the effort in writing multiple device drivers in their entirety. Clearly, this methodology saves a significant amount of time, effort, and cost of SoC verification, specifically at hardware-software interface level.


Connecting the dots together with the overall software driven verification methodology, the environment specific tests are derived from Scenario Specification of applications running on a system. The drivers are generated from the DPS (i.e. HSI Specification) for different target operating environments. The environment specific tests and drivers are compiled together to form the executables for particular platforms. This is the most simplistic representation; there are multiple processing steps involved at each stage in this.

This level of contribution by Vayavya in solving such complex issues in SoC verification space will go a long way in the semiconductor industry. Going forward, we are expected see more products, technologies and solutions from Vayavya.

Karthick Gururaj, Principal Architect at Vayavya Labs is one of the panellists in a panel on Portable Stimulus at DVCon USA

March 02, 12:00PM – 1:15PM – Software Driven Verification with Portable Stimulus: The Next Productivity Leap Enabling the Continuum of Verification Engines

To know more about this panel and attend, click HERE.

More Articles from Pawan


Design Verification Challenges: Past, Present and Future!

Design Verification Challenges: Past, Present and Future!
by Daniel Nenni on 02-26-2016 at 7:00 am

Next week I will be at DVCON which is not to be confused with DEFCON the community of black and white hat hackers that challenge our online privacy on a daily basis. DVCON is the premier conference for the functional design and verification of our beloved electronic devices. The big draw next week of course is the keynote by Dr. Walden Rhines:
Continue reading “Design Verification Challenges: Past, Present and Future!”


Mentor ARM subscription signals ecosystem shift

Mentor ARM subscription signals ecosystem shift
by Don Dingee on 02-25-2016 at 4:00 pm

Since creating the landmark “all-you-can-eat” license with Samsung in 2002, ARM has inked several subscription deals with chipmakers and EDA firms. The latest ARM subscriber license deal just announced is for Mentor Graphics. What makes their strategy unique? Continue reading “Mentor ARM subscription signals ecosystem shift”


Sustainability, Semiconductor Companies and Software Companies

Sustainability, Semiconductor Companies and Software Companies
by Daniel Payne on 02-25-2016 at 12:00 pm

I certainly want to leave the Earth a better place to live for my children and generations to come, so sustainability is a value that resonates with me. How is a consumer like me to know which companies are the most sustainable in areas that matter, like:
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