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An End of Year View of Semi Consolidation

An End of Year View of Semi Consolidation
by Bernard Murphy on 12-14-2016 at 7:00 am
Categories: Foundries

The last couple of years have been tumultuous for the semiconductor market. IC Insights just released a report showing just how much consolidation has concentrated market strength in a small number of companies. The report (which excludes fabs) shows that the 5 top companies – Intel, Samsung, Qualcomm, Broadcom and SK Hynix – now hold 41% of worldwide semiconductor market share.


Contrast this with 2006 when the top 5 held 32% share. That’s a ~30% increase in share in a market that grew in the same timespan by about the same amount. In other words, the top 5 (who were not all in the top 5 in 2006, but that’s secondary to my point) have soaked up the great majority of growth in the market. In the musical chairs of semiconductor consolidation, if you’re not in the top 5 then you’ve grown revenue on average about 3% a year, hardly better than the US GDP – you’re just rising with the tide. It’s very hard to break out of that trap through M&A – who wants to lend money to a company with that kind of growth?

Of course, the top-end of the next tiers are still growing but not nearly as rapidly. The next 5 companies below the top on average gained 2% share in a growing market. The next 10 companies below that had essentially zero growth in share, still (in some cases) making money but moving the needle negligibly for what we’ve always assumed was a high-growth industry.

Again, this is an argument based on averages, indifferent to which companies are in those groups. Any given company may have grown more or less than these averages. Mediatek and Nvidia are two excellent examples, both likely to show ~30% growth this year (which has to make them prime targets for acquisition). But the bottom line for most other companies in this class is clear. Investor pressure to find buyers must be intense; expect more consolidation in 2017.

Of the top 5 this year, Intel and Samsung are no surprise. Both Qualcomm and Broadcom have made recent significant moves to bulk up, most recently seen in Qualcomm’s acquisition of NXP and Broadcom’s acquisition of Brocade. SK Hynix stays in the top 5 this year but not in auspicious circumstances; they are expected to post a 15% revenue drop for the year. Micron, immediately behind them are also likely to post a significant drop. Behind them are TI who are perhaps best positioned to jump into the top 5 next year, though falling quite a long way short of Qualcomm/NXP and Broadcom/Brocade combined revenues. Then again, Broadcom+Brocade looks like a different animal that perhaps doesn’t quite fit in a semiconductor ranking any more. But then the same could be said for Samsung I suppose. Which maybe points to a bigger truth – perhaps the best path to significant growth lies outside pure-play semiconductors.

You can read a more complete summary of the IC Insights report HERE.

More articles by Bernard…

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Advanced Semiconductor Process Cost Trends

Advanced Semiconductor Process Cost Trends
by Scotten Jones on 12-13-2016 at 4:00 pm
Categories: Foundries, Semiconductor Services, TechInsights, TSMC

The cost trend for leading edge semiconductor technologies is a subject of some controversy in the industry. Cost is a complex issue with many interacting factors and much of the information out in the industry is in my opinion misleading or incorrect. In this article, I will discuss each of the factors as well as present a view of the status and a future forecast.
Continue reading “Advanced Semiconductor Process Cost Trends”

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#CES2017: Aftermarket to the Rescue

#CES2017: Aftermarket to the Rescue
by Roger C. Lanctot on 12-13-2016 at 12:00 pm
Categories: Automotive

Has it really been 50 years? Listening to a George Hotz Udacity podcast got me to thinking that the upcoming CES 2017 in Las Vegas will be a turning point in automated driving technology. It was just two years ago that Audi was self-driving itself from California to Nevada for CES 2015, but we don’t seem to have come that far in perfecting automated driving. In fact, the biggest headlines have come from people losing their lives in autopilot-equipped Tesla’s in the U.S., Europe and China.

Dying on the highway is becoming popular again in the U.S., with highway fatalities on the rise. Meanwhile, the U.S. Department of Transportation repeatedly intones the estimates of experts attributing 94% of crashes to the failings of human beings.

The 94% figure, which we are hearing more and more frequently, is part of the argument promoted, interestingly enough, by both Alphabet/Google and the National Highway Traffic Safety Administration. Both agree that humans are the source of all driving woes – or at least 94% of them – and therefore should be removed from those tasks. This is, of course, reminiscent of the complaint that business would be so much easier to conduct if it weren’t for those pesky customers.

Near the end of his talk, Hotz assesses the various paths to automated driving. He points out that he has met with multiple car maker CEOs, all of whom, he says, are at least five years away from delivering anything. (Hotz is the apostle of what he calls “shipability,” which he recently modified to “buildability.” His sub-$1,000 vision of semi-autonomous driving, though, has now escalated to $2,000+.)

He notes that the next closest prospects for building or shipping vehicles capable of automated driving are Alphabet, Uber and Tesla. He notes the recent departures of senior Google car executives and founders at Alphabet and concludes that the team, now headed by a former auto industry executive, is crippled and unlikely to realize the objective.

As for Uber, he questions whether funding sources have the stamina and tolerance to support the ongoing bleeding and burning for another five years with an uncertain outcome. With each passing quarter Uber looks more and more like a Ponzi scheme with no payoff… except for the passengers.
Which leaves Tesla Motors, with whom Hotz was unable to reach a development deal but for which Hotz harbors abiding respect. The bottom line for Hotz, though, is speed to market and in that respect the aftermarket rules.

With that in mind, one can’t help but root for Hotz’s success even if his semi-open source gambit allows him to take advantage of the open source community while preserving his core value proposition. Regardless of how you feel about Hotz’s open source strategy, though, his activities reflect the current state of automated driving development which is hard core research. (It’s worth remembering that Hotz is only currently offering aftermarket enhanced cruise control – Level 2 automation.)

Unlike Hotz, Polysync is offering a true open source development platform which the company has already begun selling to universities in the form of development kits. Both the Hotz and Polysync initiatives point the way to automated driving research expanding and stimulating aftermarket opportunities.

CES 2017 will see more dash-mounted solutions from Harman’s Navdy to Caruma, Nauto, Carvi and Brandmotion all designed to enhance driving with driver alerts, sensors, cameras and wireless connections. There will also be parking assist systems from companies such as Pearl Auto integrating cameras, OBDII connections and smartphone displays for collision avoidance, parking assistance and back-up camera applications.

Hotz is probably right that Alphabet seems to be losing its way, car companies are taking too long and Uber is losing too much money. But where there are lives to be saved, there are solutions to be sold and CES 2017 will be the place to find those solutions.

While you’re in Vegas you might want to check out:
http://tinyurl.com/zzf4qwm – Go NV: CES Summit on transportation.

Roger C. Lanctot is Associate Director in the Global Automotive Practice at Strategy Analytics. More details about Strategy Analytics can be found here: https://www.strategyanalytics.com/access-services/automotive#.VuGdXfkrKUk

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Flex Logix is a Different Kind of IP Company!

Flex Logix is a Different Kind of IP Company!
by Daniel Nenni on 12-13-2016 at 7:00 am
Categories: FPGA, IP

The embedded FPGA business has been getting quite a bit of press lately so it is definitely worth a closer look. Intel started it all when they acquired the #2 FPGA company Altera for $16.7B last year. Microsoft is also a big FPGA fan for search and deep learning. In fact, Microsoft’s commitment to FPGAs, specifically Altera FPGAs, is what led to the Intel acquisition. The mainstream media now knows what programmable logic means and they are intently following any and every mention of it.

Semiconductor IP has also garnered a lot of attention lately after the $32B acquisition of ARM by SoftBank. FinFETs are also helping commercial IP vendors get more attention as they significantly add to the design complexity and require a more intimate relationship with the foundry for leading edge process nodes. Even major semiconductor companies like Broadcom are jettisoning internal IP development in favor of more cost effective commercial IP solutions.

The other interesting thing to note is that fading FPGA vendors Achronix and QuickLogic have recently jumped on the embedded FPGA bandwagon with announcements of their own. It is funny more than interesting I suppose but it does provide further validation of the technology itself.

While as a rule we do not post press releases on SemiWiki because rarely do they have enough content to prevent the dreaded page view bounce, this one however answers quite a few questions:

Flex LogixHigh-Performance Embedded FPGA IP CoreNow Available for TSMC 16FF+ and 16FFC

Reconfigurable embedded FPGA to transform the design of data center, networking and base station chips

MOUNTAIN VIEW, Calif., December 13, 2016 – Flex Logix Technologies, Inc., the leading developer of embedded FPGA IP cores and software, today announced it has completed design of a high-performance IP core for TSMC 16FF+ and 16FFC, with performance for wide, single-stage logic around ~1GHz at worst case PVT conditions. Expected to be fully validated in silicon in early 2017, the EFLX-100 embedded FPGA IP core for TSMC 16FF+ and 16FFC will enable customers to design their next-generation networking, base station and data center chips with reconfigurable RTL that can be quickly, easily and cost-effectively updated or changed at any time after fabrication, even in-system.

“Configurable-cloud data centers will change the world with their ability to reprogram a data center’s hardware protocols: networking, storage and security,” said Geoff Tate, CEO and co-founder of Flex Logix. “High performance embedded FPGA enables this ability in chips cost effectively and at high performance.”

The EFLX-100 embedded FPGA core in TSMC 16FF+ and 16FFC has an architecture optimized for high speed control logic where hundreds of signals can be processed at speeds around 1GHz with single stage RTL logic, producing dozens of control signals. The EFLX-100 can be “arrayed” to build high speed control logic blocks from ~100 LUTs to ~3000 LUTs. The 16nm version of EFLX-100 has two architectural changes and physical design optimatizations from the 40nm version:

  • 224 inputs and 224 outputs: increased I/O enables wider control signal paths to be processed
  • 6-input LUTs (which can also be dual 5-input LUTs): enables more processing to be done in a single stage for higher logic density and higher performance
  • The power bus has been designed to be very robust to handle high switching activity at 1GHz+ at worst case PVT conditions
  • The core operates over the full range of voltages
  • The core requires only 5 routing layers of metal and is compatible with almost all metal stack ups
  • An EFLX-100 IP core in TSMC 16FF+/FFC has an area of 0.05mm[SUP]2[/SUP]

Flex Logix has already begun design of the larger EFLX-2.5K embedded FPGA IP cores in TSMC 16FFC: both the all-logic and DSP versions, which are interchangeable to build arrays over 100K LUTs. These will be available in early 2017 and will be validated in silicon. A TSMC 16FF+ version will also be available. The EFLX-2.5K enables large, fast array that can be used to implement accelerators for wireless base stations, networking and data center processor acceleration functions.

The design kit for the Customer’s requested EFLX Array includes GDS-II, LIB, LEF, Verilog model, CDL/Spice netlist, Test Vectors, Validation report, detailed Datasheet, Integration Guidelines & the EFLX Compiler.

EFLX Compiler for TSMC 16FF+ and 16FFC
The software for programming and checking timing performance is available now for TSMC 16FF+ EFLX-100 arrays. Flex Logix offers evaluation licenses at no cost so designers can check RTL performance and architecture ideas.

Validation Silicon in Fab
Flex Logix proves out all of its IP cores in silicon for each major process node to ensure low risk of integration, even though its IP is all digital and compatible with logic DRC rules and the IP is simulated under worst case conditions: maximum frequency, high utilization and RTL with very high toggle rates to check for worst case static and dynamic IR drops. Validation verifies in silicon that the recommended power grid architecture enables full speed operation at full utilization with high toggle rates under worst case conditions. The company checks enough array combinations to be sure that the inter-core array-interconnect is functional on all sides thus ensuring array reliability.

Flex Logix uses an on-chip PLL to test on-chip at frequencies of 1GHz+ and above to confirm all functional and performance operation over the full temperature and voltage range. Each EFLX array interconnects with external I/O for test and with on-chip SRAM for high speed pattern testing. Each array has a process, voltage and temperature monitor to ensure precise control over testing at worst case conditions. Power domains are dedicated to each EFLX array and separately for SRAM and I/O and PLL so voltage range can be measured precisely for each IP. Once validation is complete, a detailed validation report will be available under NDA to interested customers.

The validation chip for the EFLX-100 IP cores in TSMC 16FF+/FFC will soon be in fabrication, and expected to complete validation in early 2017.

About Flex Logix
Flex Logix, founded in March 2014, provides solutions for reconfigurable RTL in chip and system designs using embedded FPGA IP cores and software. Flex Logix is the leader in embedded FPGA with the widest offering on the most process nodes, including the 3 highest volume process nodes: TSMC 40ULP/LP, TSMC 28HPM/HPC and TSMC 16FF+/FFC. The company’s technology platform delivers significant customer benefits by dramatically reducing design and manufacturing risks, accelerating technology roadmaps, and bringing greater flexibility to customers’ hardware. Flex Logix is backed by leading venture firms Lux Capital and Eclipse Ventures and headquartered in Mountain View, California, with additional sales rep offices in China, Europe, Israel, Taiwan and Texas. More information can be obtained at http://www.flex-logix.com or follow on Twitter at @efpga.

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Performance Analysis for ARM Based SOC’s

Performance Analysis for ARM Based SOC’s
by Tom Simon on 12-12-2016 at 4:00 pm
Categories: Arm, IP

ARM estimates that many SOC’s designed today have over 200 IP components. This statistic comes from a recent white paper ARM published addressing the topic of system performance analysis. This number is only going to go up. According the ARM this creates a huge challenge in ensuring the system is designed with adequate performance margins. Conversely, over-design comes with high costs in terms of silicon area and power consumption. Their white paper is the first in a series that talks about how ARM is helping their customers model system performance at the earliest possible stages of the design process.

System performance in a SOC is in part determined by the following factors:

  • Processor speed (CPU, GPU, Video, Display, etc.)
  • Cache types and sizes
  • Interconnect
  • Memory speed, efficiency and data width
  • Effectiveness of IP integration

To facilitate their customers’ implementation projects, ARM has embarked on a program of developing and utilizing performance analysis methodologies on SOC designs. They are pursuing this internally as well as with customers. They see high value in making sure that performance analysis can be done effectively and systematically. ARM describes a multi-step process that they have developed.
As you might expect the first iteration is done with a spreadsheet. This is where the most fundamental issues such as bandwidth and latency are estimated for the first time. Immediately after this ARM constructs a model of the system including the path from the major IP blocks to the memory. This is exercised with verification IP to simulate traffic first for single IP blocks, then IP blocks in combination. This is where latency and traffic management are looked at. If there are no fundamental bottlenecks and the system is dimensioned properly, the next level of analysis can begin.

Key master IP such as CPU’s and GPU’s are run individually to see if they have enough data bus bandwidth with sufficiently low latency. Real world effects like competing traffic, shared resource competition, and other system loads can be modeled for more insight. Code for these tests typically run on bare metal to avoid the complexities of operating system issues. Single and multiple CPU interactions are examined at this stage, including ARM big.LITTLE technology. At this point, there probably are benchmarks or real world test cases to take advantage of.

Video codec performance in the system is tested for the gamut of encode formats, bit rates, pixel type, frame sizes, etc. These are run in isolation and in combination with other IP components. Due to the real-time nature of this data, the penalty for delays is high. If part of a frame is late, the entire frame might need to be dumped. Stress testing at this phase is essential to proper system function later.

Other ancillary functions are layered on for system performance analysis. There may be DMA, DSP, security, communications, and other blocks that all need to be factored in. Also modeling will shift to include code running on OS software.

ARM is running these kinds of analysis internally to validate their IP and the performance levels that finished products incorporating them can achieve. Various levels of abstraction are used – everything from static analysis through RTL, gate, FPGA and silicon. Software simulation and emulation are both used as needed.

ARM also works closely with their licensees, and shares their knowledge and experience in this kind of analysis. The goal is to work early in the process to anticipate system needs well in advance of the point of no return for design decisions. If you are interested in reading this white paper and the upcoming subsequent follow-on piece, look here on the ARM website.

Read Other Articles by Tom Simon

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Design for Fanout Packaging

Design for Fanout Packaging
by Bernard Murphy on 12-12-2016 at 12:00 pm
Categories: EDA, Foundries, Siemens EDA, TSMC

In constant pursuit of improved performance, power and cost, chip and system designers always want to integrate more functions together because this minimizes inter-device loads (affecting performance and power) and bill of materials on the board (affecting cost). However it generally isn’t possible to integrate everything onto one piece of silicon; digital, RF, memory and sensor functions typically must be built using incompatible processes and often depend on isolation from other functions. So product teams have turned to advanced packaging options in which multiple die, potentially built in different processes, can be integrated within a package. This still reduces inter-die loads significantly and still results in a single device at the board level.

Among the best-known approaches, 2.5D and 3D packaging are particularly popular for memory, FPGA and CPU/GPU applications. But another related packaging methodology, Fanout Wafer-Level Packaging (burdened with the unappealing abbreviation FOWLP) is already seeing wider adoption in automotive, RF and mobile applications (as seen in recent iPhones).

Avoiding the gory details, the essence of FOWLP is to embed die side-by-side in an epoxy mold compound with IO pads exposed; routing distribution layers (RDLs) are then grown over the exposed faces to connect die together, and to connect to locations for external IOs. TSVs and traditional interposers are not required, which reduces cost and allows for thinner packages.

This might be no more than an interesting alternative for packaging were it not for the fact that TSMC (among other foundries) now offers an integrated FOWLP solution they call Integrated Fanout or InFO (a much more appealing abbreviation). You can fab die with TSMC and you can integrate them into an InFO package also with TSMC. This contrasts with FOWLP solutions offered by out-sourced assembly and test (OSAT) companies who obviously do not fab die themselves.

OSATs provide features that integrated foundry solutions do not (such as integrating die from multiple foundries) but with multiple suppliers in a package customers are ultimately responsible for managing yield issues. However, with an integrated solution like InFO and sufficient market muscle to force partner die providers to fab at TSMC, managing yield should be more tractable. As a friend once told me, it’s good to have just one throat to choke when you run into problems.

Which brings me to the EDA tooling you need to design this kind of integration. FOWLP packaging methods blur the line between die design (using Linux-based design tools with all kinds of disciplined design and verification automation) and package design (usually PC-based and driven more by expert judgment than automation). More information must be communicated between package designers and chip designers and it is increasingly common to expect some level of co-design between these two, to optimize die pinouts and power distribution networks for example. Analysis at the package level must also be much more comprehensive, considering electromigration, thermal, stress and warping effects, requiring more comprehensive analysis than commonly expected in package design.


Mentor offers a very complete flow covering both design and signoff verification of FOWLP systems, starting with the Xpedition Package integrator. In conventional PCB applications Xpedition helps IC, packaging, and printed circuit board (PCB) co-design teams visualize and optimize complex single or multi-chip packages integrating silicon on board platforms. In FOWLP flows, the platform offers a single layout tool supporting fan-out as well as PCB, MCM, silicon photonics, RF and BGA designs. Users can drive rule-based I/O-level optimization and perform pin and ball-out studies from their respective domains, visualizing the impact across the complete system.

Electrical modeling and analysis of the package (die, package, substrate, board, etc.) is provided by Mentor’s HyperLynx simulation software. This analyzes design rule checks, power and signal integrity, EM, EMI and thermal; it also provides package model creation for use at the PCB level.

All of that is very necessary to design the integration but how do you get to a concept of signoff in these flows? Yields can’t be guaranteed or improved unless there is some kind of contract between customer and packager. In the IC world, this is accomplished through process design kits (PDKs). The customer signs off a design based on a PDK and the foundry guarantees their performance based on that signoff.

Mentor has introduced an approach for sign-off quality physical verification of packages which they call an assembly design kit (ADK). The purpose is similar to a PDK—to enable a contract for manufacturability and performance. What makes that happen, in both PDKs and ADKs, are standardized rules that ensure consistency across a process, qualified tool flows, interface formats, input/output formats—in short, everything a designer needs for successful design, tested and qualified and proven to produce working products. In one sense the ADK concept is not new. OSATs are already providing rules and tools for their own solutions. But the Mentor approach offers the hope of standardized requirements definitions, usable by OSAT and foundry providers and by EDA tool providers, just like we now expect for PDKs.


The platform to implement those signoff checks is the Calibre 3DSTACK functionality in Calibre nmPlatform. This is not just the IC Calibre you know and love, since it has to deal with a much more complex verification space. It requires a better understanding of the z-dimension than required for IC design. It has to deal with non-Manhattan shapes common in package design. And it must understand a wider range of formats such as ODB++ and comma-separated values for package netlists. Given these capabilities, package DRCs, package LVS, and interface checks can all be combined into a single Calibre 3DSTACK deck and checked in one run. The only individual runs required are for die-specific DRCs and LVS.

Calibre 3DSTACK is designed to support FOWLP designs for OSATs and foundries through ability to express die-by-die and package layer characteristics and rules. This is a big topic for which there’s a lot more detail than I have room (or expertise) to cover here. I recommend you read the more detailed white paper from Mentor to get a better understanding of capabilities and requirements.

More articles by Bernard…

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CEO Interview: Jack Harding of eSilicon

CEO Interview: Jack Harding of eSilicon
by Daniel Nenni on 12-12-2016 at 7:00 am
Categories: CEO Interviews, eSilicon, Semiconductor Services

I recently spoke with Jack Harding, CEO of eSilicon Corporation and Duy-Loan Le, one of eSilicon’s Board members about eSilicon’s progress in Vietnam, a large design location for the company. eSilicon also gives back in the region through its association with Sunflower Mission, a U.S. based non-profit organization that is committed to improving the lives of the people in Vietnam, mainly through educational assistance programs. Duy-Loan is a co-founder of Sunflower Mission, so I explored what is happening there with eSilicon’s support.

eSilicon has been operating in Vietnam for many years, what are the key developments over the past year?

Jack Harding: eSilicon has experienced substantial growth. We are now designing some of the most complex chips in the world. Applications for these devices range from advanced networking, high performance computing and even artificial intelligence. eSilicon Vietnam is critical to many of these achievements. The core strength of our large Vietnam team has been semiconductor IP memory development and developing new memories at the most advanced semiconductor FinFET processes. We have also built a world-class chip design team in Vietnam. This team works with our worldwide network of eSilicon expert designers. Recently we also added a specialized IC testing facility, which we believe is the first such facility in Vietnam.

With over 300 engineers, eSilicon Vietnam represents our largest workforce and to highlight the importance of this team, our vice president of worldwide human resources, Bruce Newton, is located in Vietnam.

Duy-Loan, what drove you to co-found Sunflower Mission 15 years ago?

Duy-Loan Le: There are three fundamental beliefs I hold regarding the work of Sunflower Mission. First, education forms a strong foundation for a person’s future. Second, I cannot think of a gift that is more relevant, impactful, and sustainable than the gift of knowledge through a broad scope of education. And third, the difference between success and failure is often opportunity. I have reached my position today, because I have been fortunate enough to receive a broad scope of education that engages not only academic excellence but also civic leadership to create opportunities for all.

I co-founded Sunflower Mission as my way of giving back, allowing those who are not as fortunate as me to get a good education and prosper.

What are some of Sunflower Mission’s accomplishments over the years in Vietnam?

Duy-Loan Le: Sunflower Mission has three operational pillars: elementary classroom construction, three different scholarship programs, and an annual international work camp. In the first 14 years of operation, we have built 149 classrooms across Vietnam. Importantly, October 2016 marks the start of our 15th anniversary year in Vietnam. In 2017, we will be building two kindergarten classrooms and six elementary school classrooms equipped with computer rooms. The schools are located in Quang Nam province.

Over the last 14 years, we have given scholarships to nearly 16,000 students from elementary school level through university level with over 400 of our students having graduated from a University. Many of our former teenage work camp participants go on to attend a University and while there, they apply the leadership skills learned to raise funds and lead projects to help others.

Can you tell us about current activities at Sunflower Mission?
Duy-Loan Le: This year, we received over 200 applications for the Engineering & Technology Scholarship for Excellence Program which is one of three scholarship programs of Sunflower Mission. eSilicon administers this scholarship program under Sunflower Mission’s guidance. Jack and I went to Ho Chi Minh City on November 29[SUP]th[/SUP] and Danang on December 1[SUP]st[/SUP] to present the scholarship awards to 59 winners.

This kind of success is what we aim for at Sunflower Mission.

About Sunflower Mission
Sunflower Mission’s focus is exclusively on educational programs. We strive to make a significant difference in the lives of Vietnamese youth. We reach our goals by being focused and dedicated. We are committed to ensuring that for every dollar raised, at least 97 cents will go toward the cause of educating children in Vietnam. Learn more about our scholarship, school building, and work camp programs.

About eSilicon
eSilicon guides customers through a fast, flexible, low-risk ASIC journey, from concept to volume production. We provide system-on-chip (SoC) design, custom IP, manufacturing solutions and online decision-making tools. Our strength is in optimizing our customers’ complex chips for cost, schedule, power, performance and area. Everyone worries about the cost of developing and manufacturing an SoC — investment, time, unit production price. And everyone worries about meeting power, performance and area (PPA) targets.

Finding the Right Chip Recipe
But as the number of semiconductor process and IP choices explodes, it becomes more and more difficult for designers to make informed, data-driven decisions regarding how to implement their SoCs. There are simply too many combinations to run enough trial implementations to narrow the choices down to the optimal SoC recipe. And making the right technology choices has an enormous impact on cost, schedule and PPA.

Introducing Design Virtualization
eSilicon’s design virtualization technology maps actual physical results from hundreds of SoC tapeouts and thousands of simulations to our customers’ targets to assist in finding the best possible implementation recipe. Through our proprietary STAR platform, the ability to explore — in real time — the implications of various chip implementation recipes is now possible. This is how we help our customers build the right chip, right now.

Also Read:

CEO Interview: Randy Caplan of Silicon Creations

Expert Interview: Rajeev Madhavan

CEO interview: Rene Donkers of Fractal Technologies

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Expanding your IOT Horizon

Expanding your IOT Horizon
by Bill McCabe on 12-11-2016 at 4:00 pm
Categories: IoT

There are some in the IoT industry who see certain technologies as prohibitive, especially for the average user. There are a number of areas that are currently unserved by IoT technologies, sometimes due to a lack of innovation, and at other times due to there being a lack of network support in a particular geographic location.

With the increased penetration of 4G cellular coverage around the world, there is huge potential for DIY IoT services that are independent of any major branch of technology. Learning about the companies that are preparing niche devices can help you to expand your vision of what IoT is, and who it can benefit.

Here are three exciting areas that have already been embraced by the DIY IoT community:

Environmental Tracking for Agriculture
Agricultural operators could gain a lot from IoT sensors, and independent developer Mesur would like to provide the technology. This startup company creates simple sensor devices that can track atmospheric and environmental conditions to help with seeding and harvesting, allowing operators to minimize waste and increase crop yields. They also provide tailored analytical sensor software to benefit turf management, vineyard management, and even mining operations.

Private Car Telemetry Tracking
Telemetry tracking can be hugely beneficial when used for legal defense or during insurance claims. One driver who wanted to put the power of data in his own hands, went as far as creating a device that tracked his vehicle behavior, detecting speed, location, and acceleration/braking patterns. Using simple components like gyros, a GPS module, and a transmitter, individuals could create their own vehicle tracker with telemetry, and connect it to a cellular network for extensive urban and suburban coverage.

Plant Health Monitor for Home Gardeners
By combining a GSM connected microcontroller module from Particle, along with a temperature and moisture sensor, home DIY enthusiasts could create a simple device that tracks soil quality in home planters or gardens, letting them know when it’s time to get out and water the plants. With the Particle microcontroller, alerts can be sent via SMS, email, or to a mobile app. An electron 3G kit from Particle costs less than $70 USD, and as demand for DIY devices increases, these costs are likely to come down even further.

Using a Particle Microcontroller for Almost Any Application
Particle is one of the leading companies when it comes to home and small scale IoT development. Their electron IoT microcontroller kit can provide cellular service in virtually any country that has coverage, and the microcontroller can be used with multiple sensors for virtually any application. Whether a user wanted to create a GPS tracker for their vehicle, or a door sensor for their home, the Particle would be perfect for the job.

As other companies develop DIY-friendly kit sets and technologies, it is likely that the number of home-based IoT enthusiasts will increase, and devices like the Particle could even find their way into schools and tertiary education facilities, where they will inspire the next generation of IoT designers and innovators.

For more information on IOT please check out our new website at www.internetofthingsrecruiting.com – For Help with you next IOT Search Please click here for a Free Consultation : http://internetofthingsrecruiting.com/schedule-a-conference/

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3 Reasons Why is Cybersecurity Losing

3 Reasons Why is Cybersecurity Losing
by Matthew Rosenquist on 12-11-2016 at 12:00 pm
Categories: Security

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Cyber threats are currently outpacing the defenders but it does not need to be the case. Attacks are increasing in number and type, with the overall impacts are becoming greater. Cybersecurity is struggling to keep our digital lives and assets protected from the onslaught of attacks but facing great challenges. By understanding the root causes, we can adapt and change the equation for everyone’s benefit.
Continue reading “3 Reasons Why is Cybersecurity Losing”

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Samsung Note7 Recall Was Handled Pretty Well But Not Perfect

Samsung Note7 Recall Was Handled Pretty Well But Not Perfect
by Patrick Moorhead on 12-11-2016 at 7:00 am
Categories: Mobile

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Samsung Electronics recently issued a voluntary recall on their newly released Galaxy Note7 devices, saying the battery cells of the device have the potential to overheat and pose a safety risk. Obviously, any recall is a serious matter and doesn’t ever look good for the company in question. However, I think Samsung has handled the situation pretty well, all things considered, even though the response wasn’t perfect. I want to explain that position here and it’s important that you read the complete analysis before arriving at a conclusion.

Timeline of events
When looking at recalls, it’s important first to get all the facts and understand the timeline of events. It’s a lot of information, but it’s worth going through it to get the full picture. Here’s how it played out, sequentially:

August 19th

  • Samsung announces that the Note7 is available for purchase in the U.S., Canada, Mexico, Puerto Rico, Australia, New Zealand, Singapore, Taiwan, the UAE, and Korea. This was the day when consumers were able to walk into stores and buy the device, though some who had pre-ordered received theirs a few days before.

September 2nd

September 8th

Southwest Airlines app notice (Credit: Patrick Moorhead)

September 9th

September 9th

  • Samsung starts emailing out “power down” orders and exchange information. The email was entitled, “Power down your Note7 and exchange it now”.

Samsung September 9 “power down” email (Credit: Patrick Moorhead)

September 10th

September 15th

September 16th

  • AT&T issues release entitled “Samsung Galaxy Note7 – AT&T Statement on CPSC Recall,” reiterating the “power down” command, and adding the September 21st date for new Note7s.
  • The FAA issues guidelines on any recalled items, prohibiting recalled or defective lithium batteries and lithium battery-powered devices from being turned on or charged on board aircraft.

September 21st

  • New CPSC-approved Note7s are supposed to be available through exchange programs at AT&T, T-Mobile, and Sprint.

Interestingly enough, Verizon Communications appeared to be the least vocal carrier on the recall based on at least what I could find.

As you can see, there are many different moving parts to the story. Since Samsung doesn’t have their own stores in the U.S. (like they have in other countries with 29,000 points of sale), they’re having to work through the carriers—making things inherently more challenging.

Making the best of a bad situation
I don’t want appear to downplay how serious this recall is. It is. What makes this situation so unique is that it’s a smartphone. Smartphones are so close and personal, in the sense that we wear it on our body, put them up to our heads, and even sleep next to them. This understandably compounds the reaction.

But with all the understandable grief put on Samsung, while not perfect, I believe Samsung did do the right thing and focused on customer safety – they have been ultra-cautious for the customer. They’ve followed CPSC regulations, even uniquely offering an exchange program in advance of CPSC announcing the official recall. I believe Their preemptive strategy helped Samsung avoid the sticky situation of nearly twice as many Note7 devices being in customers’ hands, but had an opposite effect in that people questioned why they didn’t work through the CPSC. Samsung told me they were actually working with the CPSC but couldn’t talk about it “because those conversations are confidential”.

Samsung Note7 paid search result on Google.com (Credit: Patrick Moorhead)

If Samsung hadn’t offered an exchange program on the 2nd, they would undoubtedly have been criticized for allowing more at-risk devices to be sold. Playing armchair quarterback, I would have preferred Samsung to have issued their “power down” directive on the 2nd instead of the 9th—but I can only speculate that it probably took a week for Samsung to fully characterize the severity of the problem. If I were them, I would also have told the public when exactly the CSPC was informed of the issue, but again, apparently those conversations are confidential and couldn’t tell that to Consumer Reports. I also need to say that I cannot validate or verify whythose conversations need to be confidential.

For some background, recall completion rates are generally lower than you might expect. The auto industry, in which people are used to bringing in products for checkups, has one of the higher completion rates at 48%. Electronics are significantly lower and I have heard that a 30% return is good. Since Samsung got out ahead of the official recall, they’ve already been successful by reaching the 15% mark—though without context that number may sound small.

Samsung not the first big company to issue a recall
It’s important to keep this all in perspective—while recalls are certainly a serious matter, they happen a whole lot in electronics. And we’re talking with big brands here, not just fly-by-night companies with shoddy reputations. I’m not going to name any specific companies in this column, but you can see there are a lot of electronics recalls:

  • U.S. CPSC-issued electronics recalls here—16 since the beginning of 2016.
  • Best Buy U.S.’s list of recalls shows 10 so far in 2016.
  • Canada’s list of electronics recalls shows 17 this year.
  • Australia consumer safety site shows 10 in 2016.

There’s overlap in these lists, but you get the picture. While it admittedly sounds a little cavalier to say “these things happen,” the truth of the matter is they kind of do—even from big name companies with big brands and the overhead to have massive supply chain and quality organizations. Note, too, that most of these recalls involve power, power cords or batteries. I worked in product management, product marketing and product strategy over 20 years and it’s an unfortunate reality that power is a tough thing.

Wrapping Up
While a serious recall such as this won’t necessarily ruin a company’s reputation, poor handling of it certainly could. In the end, this is what Samsung will be measured on. While there’s a few things I might have done differently, Samsung has more-or-less done all the right things they need to do to mitigate the situation, look out for consumers and minimize fallout. They were wisely preemptive in establishing their exchange program, and by getting the jump on it, have demonstrated a pretty clear commitment to customer safety. We’ll see what happens next, and how many phones end up being exchanged when all is said and done, but I think Samsung has handled this pretty well so far. I’m looking forward to getting my replacement unit the week of the 21st as it really is a good smartphone.

Also read: Samsung’s Galaxy Note 7 phones caught fire because of the ‘aggressive’ battery design: Report