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AAPl Vs QCOM Who wins?

AAPl Vs QCOM Who wins?
by Daniel Nenni on 01-26-2017 at 7:00 am
Categories: Ceva, Foundries, Intel Foundry, IP, Mobile, TSMC

Things just got interesting in the iPhone supply chain with the $1B AAPL Vs QCOM legal action filed this week. For the life of me I could not understand why Apple second sourced the normally QCOM modem in the iPhone 7. It caused quite a stir in the technical community but we could only surmise that it was a price issue on the business side. Well, clearly it was more than just price.

AAPL:“For many years Qualcomm has unfairly insisted on charging royalties for technologies they have nothing to do with. The more Apple innovates with unique features such as TouchID, advanced displays, and cameras, to name just a few, the more money Qualcomm collects for no reason and the more expensive it becomes for Apple to fund these innovations. Qualcomm built its business on older, legacy, standards but reinforces its dominance through exclusionary tactics and excessive royalties. Despite being just one of over a dozen companies who contributed to basic cellular standards, Qualcomm insists on charging Apple at least five times more in payments than all the other cellular patent licensors we have agreements with combined.”

Apple seems to be piggy backing on the legal actions against QCOM from China, Korea, Taiwan, EU, and the USA. But Apple’s problems may have started when they used Intel modems and broke an exclusivity clause with QCOM. Either way this is a legal mess that may not be resolved for months or even years.

QCOM:Apple’s complaint contains a lot of assertions. But in the end, this is a commercial dispute over the price of intellectual property. They want to pay less than the fair value that QUALCOMM has established in the marketplace for our technology, even though Apple has generated billions in profits from using that technology

In the meantime let’s look at the modem issue and see who will ultimately profit. My bet is TSMC of course and here is why:

Remember, even though Intel supplies the XMM 7360 LTE modem used in the iPhone 7, TSMC manufactures it on their 28nm process. The next-in-line Intel modem is the XMM 7480 which was announced one year ago and is now being qualified by AT&T and other carriers. Intel has made statements in the past that they will move modem manufacturing from TSMC to Intel so the $1B question is: Who will manufacture the XMM 7480?

Here is the answer from the J.P. Morgan Tech Forum at CES 2017:

Q – Harlan Sur: So you guys recently got qualified with your next-gen XMM 7480 modem. Help us understand, first of all, is this product being manufactured by Intel internally or is it still being manufactured at TSMC?

A – Navin Shenoy: We’ll make decisions on where we manufacture the modem on a pragmatic basis. I’m not going to tell you right now yet where we’re going to manufacture XMM 7480 or the subsequent ones. But suffice it to say, we’re looking at both internal and external options.

Clearly that decision has already been made since the chip is in production. As you can tell Navin (Intel Client Computing Group VP) is a career Intel employee well versed in doublespeak. I was hoping Murthy Renduchintala (Navin’s boss) would rid Intel of double speakers but clearly that is not the case, yet.

If it was on an Intel process you can bet Navin would have proudly boasted, so my bet is that the XMM 7480 is already in high volume manufacturing using TSMC 28nm and it is highly unlikely it will be moved to Intel 14nm. In my opinion the first Intel modem to use an Intel process (14nm) is the 5G modem they announced this month. 4G modems are a price driven commodity and nobody does 28nm better than TSMC. I would also argue that the TSMC 16FFC process is better than Intel 14nm for price and power but Intel needs to prove their ability to manufacture mobile chips to justify the huge investment they have made so it will probably be Intel 14nm.

The other winner of course is one of my favorite IP companies (CEVA) as their IP is designed in the Intel 4G modem. Intel licensed CEVA-XC core for LTE chips back in 2010 at around the same time it acquired Infineon’s wireless business unit. Infineon is also a CEVA licensee for their ARM-based 3G and 4G LTE modems.

The Intel Corporate Earnings call is tonight so we can continue this discussion in the comments section…

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Power Management Beyond the Edge

Power Management Beyond the Edge
by Bernard Murphy on 01-25-2017 at 7:00 am
Categories: Ansys, Inc., EDA

Power in IoT edge devices gets a lot of press around how to make devices last for years on a single battery charge, significantly through “dark silicon” – turning on only briefly to perform some measurement and shoot off a wireless transmission before turning off again. But we tend to forget that the infrastructure to support those devices – gateways, backhaul communication and clouds – cannot play by the same rules. This infrastructure must deal with unpredictable traffic in high volumes, where power-down strategies are impractical.

Moreover, if you consider total power burned and the cost of that power, this is far, far higher in the infrastructure than in the edge devices. Datacenters alone are believed to consume about 3% of total energy produced worldwide. Those costs motivate owners of infrastructure to lean hard on equipment suppliers to reduce power by whatever means they can. Meeting that objective generally requires a much more nuanced management of power, depending heavily on understanding how a wide range of realistic workloads will drive the system.

AMD is a company whose products are used in datacenters, wireless and wireline network applications, network security and unified communications applications, so they feel that pressure across their product line. Illustrating this, they have a white-paper on how they approached power reduction in one of their server-class designs, written by a couple of technical team members based in Austin.

The objective was a retooling for lower power since they were starting from an existing design; changes to the fundamental architecture weren’t an option. Implementation-stage tweaks wouldn’t return big enough savings so that left micro-architectural fine-tuning as the only way to drive down power. While such changes are usually quite modest, impact can be significant – AMD was able to reduce idle power by 70% and peak power by 22%. But as always in power reduction, there’s no simple recipe for finding the best places to make changes. You have to try a lot of possibilities against a lot of different use-cases, then decide which of those are most promising in power saving, while balancing impact on other factors such as area and timing.


That kind of iteration isn’t possible if you’re going to measure the impact through power estimation at the gate-level since each RTL what-if would require a re-implementation cycle through multiple tools. AMD estimated that it would take 6-8 weeks to generate power estimates at the gate-level, at which point that analysis would be irrelevant to a design that had evolved far beyond the point at which the measurements were made.

A much better approach is to iterate on changes with power estimation at RTL. In absolute terms this won’t be as accurate as estimation at the gate level – RTL-based estimation must estimate Vt mixes, design-ware mapping, clock trees and interconnect parasitics, all factors which are known at the gate level and on which gate-level accuracy depends. But relative accuracy between RTL-based estimates for modest changes on the same design can be much better. Moreover, for incremental changes estimation can intelligently re-compute the impact on activity factors without need for re-simulation, making power-estimation even faster. AMD observed that these factors together trimmed analysis time to a day.

The design team chose Ansys’ Power Artist to drive their RTL power estimation. This is a product with a distinguished history. Commercial RTL-based power estimation was first introduced to the world back in the 1990’s by Sente, in a product called WattWatcher. The product and the team have gone through a couple of acquisitions and some names have changed, but PowerArtist is that same product, greatly evolved of course. Point being, they’ve been doing this for a long time and have wide-spread industry recognition as experts in the space.

AMD provide detail on how they used PowerArtist to isolate power hogs and experiment with improved clock gating. They also found that 50% of estimated power was being burned in the clock distribution network (PowerArtist models this network for this reason). This is a good example of why designer judgment (guided by input from the tool) is so crucial in power reduction. You could reduce power by gating clocks at the leaf-level where feasible and still not significantly reduce power, whereas carefully planning gating higher in the clock tree for a smaller number of leaf-cases could make a much bigger difference.


Power reduction is a process as almost anyone in the game will be eager to tell you. You don’t do one task then put the power tools away. You’re constantly checking and improving, which is again why fast iteration in power estimation is so important. I found one chart in the AMD write-up particularly interesting – a trend chart for estimated power as the design progressed. Power-aware design teams have this process embedded in their regression suites so they can update trend charts like this as the design evolves. You fixed that timing problem or you changed the queue-manager from fixed length to variable length but power spiked up again – what happened? Getting frequent updates is the best way to check and correct before problems become unfixable. PowerArtist has the tools you need to support this kind of analysis and trending.

You can read the AMD team’s write-up HERE.

More articles by Bernard…

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Mentor Safe Program Rounds Out Automotive Position

Mentor Safe Program Rounds Out Automotive Position
by Bernard Murphy on 01-24-2017 at 7:00 am
Categories: Automotive, EDA, Siemens EDA

Mentor has an especially strong position in the automotive space given their broad span of embedded, SoC, mechanical and thermal and system design tools. Of course, these days demonstrating ISO 26262 compliance is mandatory for semiconductor and systems suppliers, so EDA vendors need to play their part to support those suppliers in demonstrating that components and design tools they offer meet appropriate levels of certification.

Mentor has recently announced the Mentor Safe Program which aims to comprehensively qualify and document, to ISO 26262 standards, a select range of components and design tools used in the design of automotive systems. This includes the software components Nucleus SafetyCert and the Volcano VSTAR AUTSAR basic software stack, as well as several design tool qualifications. This is an important addition for systems suppliers who ultimately must demonstrate complete compliance to the standard. The Safe Program provides the documentation and certification to back that up in areas covered by Mentor components and tooling.

Nucleus SafetyCert is a version of the popular Nucleus RTOS, in the certification process with TÜV-SÜD, and is verified and documented to meet requirements for device manufacturers developing to avionics DO-178C Level A, industrial IEC 61508 SIL 3, medical IEC 62304 Class C, and automotive ISO 26262 ASIL B. Volcano VSTAR is also TÜV-SÜD certified to ASIL B. The process for design tools is a little different because what is required for a tool depends on the tool classification level (TCL). I’ll talk a little about that further on in this piece.

ISO 26262 is dry stuff, but we need to understand it if we want to succeed in this rapidly growing market so it’s worth digging into the process in a bit more detail. By way of example, look at what Mentor supplies in the Nucleus SafetyCert certification package:

  • Source code
  • Documentation on the software development, configuration management and QA processes
  • Documentation on the requirements process, designs standards and coding standards
  • Documentation on the software verification process, the test plan and the complete software test suite
  • A safety manual to be used by system integrators to guide correct/permissible usage

All of this with traceability across the safety lifecycle and extensive hyperlinking to simplify audits and reviews. (And yes, you need to sign an NDA to get access to this package!)


For tools, Mentor generates a report which becomes a component of documentation for their product certification where required. These have up to 8 sections:

  • Sections 1, 2 and 3 covering boilerplate information on the document and the tool classification process.
  • Section 4 covering the tool classification– the tool impact (TI) and tool error detection (TD) levels, leading to a tool confidence level (TCL), based on use-cases, configuration, environment, safety checks and tool/tool-chain restrictions. If the classification is TCL1, the rest of the report is not required.

(The following sections are only required for tools at TCL2 or TCL3 levels)

  • Section 6 describes the software tool qualification process
  • Section 7 describes the tool qualification – QA documents, test-cases, errata and tool error detection relative to use-cases
  • Section 8 describes the software tool qualification conclusion

Tools that are currently covered by this certification program are several of the Tessent silicon test and yield analysis tools and ReqTracer for requirements tracing. Mentor intends to add more tools over time.

Nine of the Tessent silicon test and yield analysis tools can be used at the TCL2 level so have been certified through SGS-TÜV-Saar for use at any TCL level. ReqTracer is classified as TCL1 so is not required to have certification. However, Mentor provide justification in their report for the tool on why they classified tool impact (TI) and tool error detection (TD) levels leading to this TCL classification.

Per the ISO 26262 standard, this is all Mentor must do to demonstrate compliance for a TCL1 tool but they have actually taken it a step further for ReqTracer. The standard requires that confirmation measures (review and approval of the process) are assessed by a different person than the one performed the classification (a level I1 degree of independence per the standard), but Mentor took review to level I3 where the review was performed by independent Functional Safety Certified Automotive Manager (FSCAM). Looks like they take this pretty seriously.

You can read more about the Mentor Safe program HERE.

More articles by Bernard…

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Qorvo and KeySight to Present on Managing Collaboration for Multi-site, Multi-vendor RF Design

Qorvo and KeySight to Present on Managing Collaboration for Multi-site, Multi-vendor RF Design
by Mitch Heins on 01-23-2017 at 12:00 pm
Categories: Cliosoft, EDA, IP

Over the last several weeks I’ve been having a lot of discussions with colleagues around IP reuse and design data management. This led me to a discussion with Ranjit Adhikary, Marketing Vice President for ClioSoft.

ClioSoft is best known for their design collaboration software platform called SOS. They also sell an enterprise IP management platform that works in conjunction with SOS. As I spoke with Ranjit it became clear to me that a discussion about IP and design management really is indeed a discussion about how to work in a collaborative environment. IP blocks are simply an artifact of collaborative design that must be managed.

So backing up a bit I started to quiz Ranjit about what they are seeing in the design arena today and how this has affected how they are marketing their products. With the advent of the internet of things (IoT), a key driver for ClioSoft’s business for last two years has been wireless design. How so you might ask?

Well, wireless implies RF, analog and mixed signal designs and these types of designs are typically done using full-custom design methodologies. Further, full-custom design methodologies imply lots of hands-on engineering work in interactive EDA tools. To handle complexity, designs get carved up into blocks that can be easily managed by humans. Large designs use lots of hierarchy and lots of blocks. Combine this with ever increasing competition and ever shortening design cycles times, and that means you must have big teams of engineers working simultaneously on these designs with the need to collaborate with each other.

To make matters more complex, companies that create these type of RF and mixed-signal ICs typically come about through multiple rounds of mergers and acquisitions and as a result, have design teams scattered around the world in multiple locations across multiple time-zones and many times with multiple different EDA tool sets. As you can imagine, this is a very fluid environment and can be fraught with peril as a company gets closer to tape-out time. The worst case scenario being that the left hand doesn’t always stay in sync with the right hand and a design gets taped-out using a wrong and incompatible version of a block making the entire IC dead on arrival.

This then begs the question of how do companies manage these types of designs when using geographically dispersed design teams with different EDA tools? Ranjit started to explain more of the details about how their product offerings help and then stopped short and said, hey why am I telling you this? We are hosting a webinar in a week’s time where one of our customers, Qorvo, and one of our EDA partners, Keysight, will be presenting on just this topic. You should attend the webinar and they can tell you in their own words how they are managing RF designs in just such an environment. Qorvo will talk about how they manage their RF designs and Keysight will talk about how they handle the issues of EDA interoperability.

Great, I’m all in! And…while I’m at it, I’ll let everyone else know about the webinar as well because if I’m asking, I’m sure everyone else is probably thinking the same thing. The webinar is being hosted by ClioSoft and will be held on February 1[SUP]st[/SUP], 2017 at 10:30am PST. To register for the webinar simply follow this link and use the “CLICK HERE TO REGISTER” button at the bottom of the page.

In the meantime, if you have interest to learn more about ClioSoft’s offerings you can visit their website at: www.cliosoft.com.

Also Read

Tool Trends Highlight an Industry Trend for AMS designs

Managing International Design Collaboration

Making your AMS Simulators Faster (webinar)

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DARPA Flex Logix and TSMC!

DARPA Flex Logix and TSMC!
by Daniel Nenni on 01-23-2017 at 10:00 am
Categories: eFPGA, Flex Logix, IP, TSMC

When I first saw emerging semiconductor IP company Flex Logix actively involved with TSMC I knew something big was coming and boy was I right. DARPA announced today that an agreement is in place with Flex Logix to develop EFLX eFPGA technology on TSMC 16FFC for use by companies or Government agencies designing chips for the US Government. Wow! GO DARPA!

“Embedded FPGA technology is a game changer in the chip design process and we are pleased to be working with DARPA,” said Geoff Tate, CEO and co-founder of Flex Logix. “Chip development costs and lead times keep increasing and the ability to reconfigure RTL at any time can eliminate expensive chip spins, enable one chip to address many customers and applications, and extend the life of chips and systems. As a result, designers can easily keep up with changing standards and customer requirements.”

Digging a little deeper you will find that this announcement is tied to the DARPA Microsystems Technology Office (MTO) and specifically the Craft Project:

It can cost up to $100 million and take more than two years for a large team of engineers to design custom integrated circuits for specific tasks, such as synchronizing the activity of unmanned aerial vehicles or the real-time conversion of raw radar data into tactically useful 3-D imagery. This is why Defense Department engineers often turn to inexpensive and readily available general-purpose circuits, and then rely on software to make those circuits run the specialized operations they need. This practice can speed up design and implementation, but it also results in the deployment of unnecessary and power-hungry circuitry. And that, in turn, can lead to technology that requires more power than can be practically supplied on small flying platforms or on warfighters already burdened by too much battery weight.

The Circuit Realization at Faster Timescales (CRAFT) program seeks to shorten the design cycle for custom integrated circuits to months rather than years;devise design frameworks that can be readily recast when next-generation fabrication plants come on line; and create a repository of innovations so that methods, documentation, and intellectual property can be repurposed, rather than reinvented, with each design and fabrication cycle. This novel, less expensive design paradigm also could help diversify the innovation ecosystem by making it practical for small design teams to take on complex custom circuit development challenges that are out of their reach today.

Reducing the time and cost for designing and procuring custom, high-efficiency integrated circuits, should drive more of those in the DoD technology community toward best commercial fabrication and design practices. A primary payoff would be a versatile development environment in which engineers and designers make decisions based on the best technical solutions for the systems they are building, instead of worrying about circuit design delays or costs.

The program manager on Craft is Dr. Limton Salmon who came to DARPA from both sides of the semiconductor industry. He spent 15 years in executive roles directing development of CMOS technology from the 130nm through the 7nm node at GlobalFoundries, Texas Instruments and Advanced Micro Devices. Prior to that Dr. Salmon was an academic at Case Western Reserve University and Brigham Young University.

We have been covering FlexLogix on SemiWiki for 12 months now and have a dozen articles on different aspects of the technology and company. The SemiWiki Flex Logix landing page is HERE.

Congratulations to the hard working people at DARPA, Flex Logix, and TSMC, absolutely.

About Flex Logix
Flex Logix, founded in March 2014, provides solutions for reconfigurable RTL in chip and system designs using embedded FPGA IP cores and software. The company’s technology platform delivers significant customer benefits by dramatically reducing design and manufacturing risks, accelerating technology roadmaps, and bringing greater flexibility to customers’ hardware. Flex Logix recently secured $7.4 million of venture backed capital. It is headquartered in Mountain View, California and has sales rep offices in China, Europe, Israel, Taiwan and Texas. More information can be obtained at http://www.flex-logix.com or follow on Twitter at @efpga.

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Technology Update With Andrew Faulkner and Jim Lipman of Sidense

Technology Update With Andrew Faulkner and Jim Lipman of Sidense
by Daniel Nenni on 01-23-2017 at 7:00 am
Categories: IoT, IP, Sidense

Sidense is an interesting company in a very important market segment. Sidense was founded in 2004 and their 1T-OTP memory macros are now used in hundreds of chips from 180nm to 16nm for code storage, secure encryption keys, analog and sensor trimming and calibration, ID tags, and chip and processor configuration.

If you are designing chips for mobile, automotive, industrial, consumer, or Internet of Things (IoT) you probably already know Sidense but just in case you don’t I was able to catch up with Andrew Faulkner and Jim Lipman for a brief Q&A update on their technology and what we can expect moving forward.

Your one-time programmable memory IP products are based on an antifuse bit cell. Can you briefly explain how the bit cell works?
The antifuse bit cell, when un-programmed, behaves like a capacitor with an insulating SiO[SUB]2[/SUB] layer between a transistor gate and silicon substrate. When programmed, the insulating oxide undergoes a permanent and controlled breakdown and the bit cell behaves like a conducting diode. Unlike an electrical fuse, which is normally conductive or “closed” until a current of sufficient magnitude flows through the fuse and interrupts (blows) the conductive path, an antifuse OTP bit cell is normally non-conductive, representing a “0” logic bit state, until it is programmed to a logic bit state of “1.”

The antifuse OTP bit cell is programmed by applying a sufficiently high-voltage across the gate and substrate of a thin oxide transistor (around 6V for a 2 nm thick oxide, or 30MV/cm) to break down the oxide between gate and substrate. The positive voltage on the transistor’s gate forms an inversion channel in the substrate below the gate, causing a tunneling current to flow through the oxide. The current produces additional traps in the oxide, increasing the current through the oxide and ultimately melting the oxide and forming a permanent conductive channel from gate to substrate. Once programmed, the antifuse bit cell cannot be un-programmed.

Antifuse-based OTP memory operates very reliably over a wide temperature range compared to other types of NVM memory that depend on charge storage to determine the state of the memory’s bit cells. The memory is also highly secure, since it is extremely difficult to read or modify the OTP memory’s contents.

Sidense’s 1T-OTP is one transistor per bit cell – how is this accomplished?
The Sidense bit cell utilizes a unique split channel architecture, 1T-Fuse™, in which the bit cell transistor’s gate overlaps both thick (I/O) and thin (gate) oxide regions. This architecture has been implemented in many foundry and IDM process flows from180nm down to 16nm.

Why have you been able to successfully use a single transistor antifuse-based bit cell for your OTP and what are the advantages over a two-transistor antifuse bit cell?
The 1T-Fuse bit-cell architecture has several advantages over two-transistor antifuse bit cells. Using only one transistor per bit cell results in very small OTP memory arrays that minimally impact the size and cost of the chips in which they are embedded. Since the programming channel is very small and only occurs over the transistor channel, the programming is very robust and reliable. In addition, it is almost impossible to ascertain whether or not a bit cell is programmed, either by physical methods (de-processing or cross sectioning) or by scanning techniques since the bit-cell state does not depend on charge storage, like a flash bit cell.

Sidense has successfully demonstrated 1T-OTP operation down to 16nm FinFET processes. What do you think is the scaling limit for your technology?
Sidense 1T-OTP macros are designed such that the bit-cell programming voltage, which is higher than normal chip operating voltages, does not affect the macro’s peripheral circuitry. The 1T-OTP bit cell architecture has shown good scalability down to 16nm and we don’t expect to run into problems down to 7nm. However as process technology scales, it becomes more difficult to design peripheral circuitry, such as sense amplifiers, to work at the lower voltages of the process. The technology scaling limit may well be set by these circuits rather than by the 1T-OTP bit cell.

What technical challenges are your customers facing with respect to NVM and how does Sidense address them?
We have seen universal acceptance of our OTP across many applications in the Smart Connected Universe, which comprises the mobile computing and communications, IoT, automotive, industrial, medical and wearable market segments. The challenges our customers are seeing in implementing NVM include low-power and low-voltage operation, an expanding need for high temperature operation for automotive and industrial applications and the ever-increasing need for higher security both for data-in-transit and data-at-rest in storage.

Along with the inherent low power and security of the 1T-OTP bit cell, Sidense has developed various circuit techniques to minimize power consumption and enhance OTP IP security. In addition, 1T-OTP is available at more than 17 foundries and almost 60 process variants, including those targeting highly demanding automotive and low-power IoT and mobile applications.

What are the advantages for your customers to design in 1T-OTP compared to other OTP?
I’ve already mentioned 1T-OTP’s broad scalability, from 180nm to 16nm and below, low power and high security attributes. 1T-OTP arrays are available in several BCD, HV and CIS technologies at more than 11 nodes across more than 5 foundries. Compared to other OTP technologies, such as eFuse, 1T-OTP is easy to program and read and is very reliable with retention greater than 10 years at maximum operating temperature and a 100% read duty cycle. Since the state of an antifuse OTP bit cell is not determined by charge storage it is difficult to determine the state of the bit cell, making it inherently secure.

Antifuse-based 1T-OTP does not require any additional masks or process steps and does not require burn-in, again making it a very cost-effective NVM solution. Furthermore, bit-cell programming may be done either by using an external power supply or using an integrated IPS macro, supporting programming at-test or in the field. Once data programmed into OTP is finalized, either for an entire memory array or part of it, conversion to ROM is simple, just by changing one non-critical mask step.

Where does your 1T-OTP fit in with all the new memory technologies (FRAM, MRAM, RRAM, and PCRAM) that are currently under development or in production?
We feel that 1T-OTP serves markets not targeted by the new memory technologies, which are mostly being developed and used as NAND-based flash and DRAM replacements in high-density cache or data storage applications. Many of the new technologies do and will require additional process steps and hence additional cost. For the most part, they are or will be available as separate chips rather than memory IP cores.

What is your take on the IoT market? Does it represent a big opportunity for Sidense?
Absolutely! However, we look at it in a slightly different way than others. Analysts like to talk about killer apps and after the smartphone wave there was a void – without a doubt, IoT has filled that void.

Unfortunately many folks have difficulty getting their heads around IoT and what it is. Is it devices? Is it big data? Is it everything in between? How do we define which market segments it comprises and, more importantly, how do we target them? In our opinion IoT should really be the IoE, the Internet of Everything!

As we discussed earlier we defined the “Smart Connected Universe” that cuts across traditional markets, including automotive, industrial, consumer and others. Devices in the Smart Connected Universe are defined by a few common characteristics: sensing, smarts and connectivity. In fact wherever we see a combination of these characteristics we find a sweet spot for our OTP and eMTP products. Our products are used to store secure keys and trim and calibration parameters, among many other uses. These Smart Connected devices exist as bridges between the analog world that surrounds us and the digital world and with that in mind, sensors are key components. In the IoT ecosystem, sensors are everywhere and so are opportunities for Sidense NVM products.

www.sidense.com

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Another Interesting Thing From TSMC!

Another Interesting Thing From TSMC!
by Daniel Nenni on 01-21-2017 at 7:00 am
Categories: Foundries, Intel Foundry, TSMC

As I mentioned in my previous post, the TSMC investor call this month was very interesting and Morris Chang was in fine form during the Q&A. As a semiconductor professional I think some of the questions are ridiculous but maybe they have value to the financial people. This one question from Randy, who I think is very astute, is SemiWiki discussion worthy:

Randy Abrams
Yes, thank you. The first question, I wanted to ask your outlook is more in line with the industry where you are guiding 5% to 10% for foundry near similar levels. Could you talk about the factors to be more inline after gaining the last few years? And can you also address the China business; we are seeing the China foundries grow faster. SMIC is growing 20% to 30%, how does TSMC combat or defend share more on the mature nodes, where they’re starting to grow faster?


(At the bottom it says SMIC is partially owned by TSMC. TSMC did get a 10% equity stake after the IP litigation which I thought TSMC had already divested. Please post a comment if you know otherwise.)

First and foremost, TSMC is being conservative as they always are and they are shielding their #1 customer which is Apple. There is no way the second half of the year will be 5% growth with Apple single sourcing 10nm from TSMC for the next iPhone and iPad. TSMC will again be in double digits (10-15% revenue growth) for 2017 as I previously stated.

This is going to be another strong year for the foundries but I do find it interesting that while the semiconductor foundry business is posting double digit gains the semiconductor industry as a whole is relatively flat… Comments?

Second, SMIC is surging on 2[SUP]nd[/SUP] source business now that they are shipping a TSMC compatible 28nm, most of which is in China. How does TSMC combat or defend the mature nodes? In China they don’t, they push the market to FinFETs. Remember, the TSMC GDS compatible market stops with FinFETs and SMIC does not expect to have 14nm until 2020 or so. Meanwhile TSMC is getting ready to release a fourth generation (12nm) FinFET process optimized for density and cost. In fact, I hope TSMC shows an updated version of the infamous Intel chip scaling graph shown below.


Remember, this graph was based on a paper done by TSMC before 16nm went into production. TSMC then released 16FF+, 16FFC, and now 12nm.

My guess is that TSMC 12nm will easily be on par with Intel 14nm in regards to chip density and superior in cost per transistor… Comments?

Unfortunately, Intel is still flogging this outdated slide. In fact, just this month at the J.P. Morgan 2017 Tech Forum, Intel Client Computing Group VP Navin Shenoy said Intel 14nm is equivalent to Samsung and TSMC 10nm so they are considering renaming their 10nm:

“I’m confident that when 10 nanometer — our 10 nanometer — comes out, and this is something that maybe we should rename it, I don’t know, we’ll think about that, but when our 10 nanometer comes out, we will have a clear density advantage, and a clear performance and power advantage versus what others in the industry have.”

Well, yes and no. Unfortunately for Intel their 10nm will come out about the same time as TSMC 7nm so no, Intel will not have a clear density advantage:

Morris Chang
I think 2017 will be pretty strong in terms of technology, it will be a pretty strong 16 or 14 FinFET year, and our market share in 16, while it’s quite high, is not as high as I would like, it’s actually in the close to 70% or 65% to 70%. Now that is not quite as high as our 28 nanometer which even now, you know, like almost 80% and now, 2017 is – I think it’s a pretty – we think will be a pretty strong year and result.

Absolutely…

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TCAD Simulation of Organic Optoelectronic Devices

TCAD Simulation of Organic Optoelectronic Devices
by Daniel Payne on 01-20-2017 at 4:00 pm
Categories: EDA

In my office there are plenty of LED displays for me to look at throughout the day: three 24″ displays from Viewsonic, a 15″ display from Apple, an iPad, a Samsung Galaxy Note 4, a Nexus tablet, a Garmin 520 bike computer, and a temperature display. LED and OLED displays are ubiquitous in all sorts of consumer electronics, so there must be some clever way that engineers simulate and design these. To learn more about OLED and LED devices I spoke with Steve Broadbent by phone, and his background includes a MS degree in physics from the University of Maryland plus decades of experience in the world of TCAD. I was surprised to discover that OLED devices are now being used for residential and commercial lighting applications and not just consumer electronics. Steve works at Silvaco and will be hosting a webinar on January 26th on this TCAD topic, from 10AM-11AM PST.

Device simulators in TCAD have been around for many years now and they work with calibrated models and then use mesh structures for the predictive analysis of creating new device structures. With a device simulator you can speed up new development, reduce risks and even improve the reliability. Command-line device simulation was the earliest approach, however to make the TCAD experience even easier a GUI approach is now being used as the starting point for device simulation. The new GUI-based device simulator for LED and OLED devices from Silvaco is called Radiant, and they first announced it in 2015.

Related blog – It’s Better than SUPREM for 3D TCAD

With the Radiant tool you are looking at a 2D cross section for an LED or OLED device as shown below in the left-hand side of the screen, where each layer is a different color in the stack. In the right-hand side of the screen we are defining the structure of the stack.


The GUI for Radiant

In the webinar Steve will be showing how you go about setting up each of the seven organic layers of an OLED in the Radiant tool. You get to specify the properties of each material being used, like the work function, permittivity, heat capacity, and color.


Making a multi-layer OLED

From the Radiant GUI you can run analysis like a DC simulation, which then creates a DeckBuild to run the simulation. When DeckBuild is finished you can view a current plot. Another type of analysis is an optical simulation, and one example to be discussed is from M. Baldo as published in Nature, volume 395 on page 151:

Emission spectra of two OLEDs

Another way to help optimize the design of LED and OLED devices is to sweep a parameter through a specific range and then run a number of simulations in sequence. This allows the TCAD user to better understand how to make trade-offs in reaching their design requirements.

Related blog – 3D TCAD Simulation of Silicon Power Devices

Webinar

Register for the webinar today, and learn something new about TCAD for OLED and LED devices on January 26th. Here is the webinar outline:

 

  • TCAD simulation of Organic LED
    • Simulations required in the developemt of Oragnic LED
    • Theoretical background (Electrical simulation, Optical simulation)
  • An integrated simulation environment for the LED/OLED devices
    • What is Radiant
    • Features
    • Areas of simulations Radiant will cover
    • Simulation flow (Electrical simulation, Optical simulation)
  • Examples
    • Electrical simulation of a multilayer OLED device
    • Optical simulation of a multilayer OLED device
    • FDTD simulation of light propagation in an OLED device
  • Summary and future enhancement

Even if you register for the live webinar and cannot make it on January 26th, don’t worry, because you will receive an email with a link to the archived webinar. My favorite part of any webinar is always the Q&A time where you can get those nagging questions answered and receive clarification on what you just learned.

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Fan-Out Wafer Level Processing Gets Boost from Mentor TSMC Collaboration

Fan-Out Wafer Level Processing Gets Boost from Mentor TSMC Collaboration
by Mitch Heins on 01-20-2017 at 12:00 pm
Categories: EDA, Siemens EDA, TSMC

I caught up with John Ferguson of Mentor Graphics this week to learn more about a recent announcement that TSMC has extended its collaboration with Mentor in the area of Fan-Out Wafer Level Processing (FOWLP).

In March of last year Mentor and TSMC announced that they were collaborating on a design and verification flow for TSMC’s InFO (integrated Fan-Out) packaging technology using Mentor’s Xpedition Enterprise and Calibre nmDRC/RVE platforms. That flow allowed designers to layout the InFO structures with Mentor’s Xpedition Package Integrator and then use Calibre nmDRC for design rule checking with cross probing back into Xpedition using Calibre RVE.

Since then, the Mentor and TSMC teams have been working closely together to enhance the flow to shorten design cycle times, minimize designer effort and ensure higher quality GDS hand-offs to improve first-time success rates. Key to the collaboration were efforts to ensure seamless assimilation of TSMC’s newest technologies whether it be single or multiple die on InFO packaging, with or without a substrate, and with or without package-on-package. To achieve this, Mentor has attacked several different areas.

Firstly, Mentor developed new Xpedition Enterprise functionality to make it easier to create InFO-specific fab-ready metal structures such as seal rings, parameterized mesh pad generation, degassing holes and additional metal for balancing metal density.

Mentor next added HyperLynx DRC technology to the flow for in-design InFO-specific manufacturing verification checks. HyperLynx DRC allows designers to find and fix DRC issues while still in the design phase reducing the number of iterations out to GDSII for DRC checking in Calibre. Final sign-off rule checking is still done with Calibre nmDRC for both die and InFO package design rule checks.

New to the flow with this release is the addition of Calibre 3DSTACK and the capability to do sign-off level layout-vs-schematic (LVS) checks for inter-die connectivity verification of the entire InFO-based package.

For IC designers this may sound trivial, but when you realize that you are possibly dealing with multiple die, each with their own CAD database, as well as data for the silicon wafer providing the InFO connectivity you start to see how messy the CAD flow can get. Also considering each die may have thousands of pins you also realize how easy it would be to get something hooked up wrong and how hard it would be to find a mistake without good LVS tools. This will be a much appreciated addition to the flow.

In December of 2016, John was interviewed for an article in Chip Scale Review in which he outlined how TSMC has worked with EDA companies like Mentor to develop EDA solutions for IC and package design with an intent to ensure that InFO designs would be fully compliant with TSMC’s packaging design rules and sign-off requirements. At that time, John mentioned that TSMC was in fact working to expand the InFO tool support into sign-off electrical analysis to enable designers to analyze the parasitic impacts from InFO and its neighboring layers. It appears this is now in place for the Mentor flow, with the addition of signal integrity checking of the InFO interconnects using signal path tracing, extraction, simulation and netlist export.

The flow also now supports integration to thermal analysis and thermally-aware post-layout simulation flows to provide early identification of potential system level heat issues. The connection to the simulation world also enables such things as multi-die reliability analysis including analysis of electromigration and IR drop.

While Fan-Out Wafer Level Processing is catching on with its promises of low cost, small form factors, and low power with high performance, the addition of a fully integrated IC and package design flow goes a long way toward making this a truly usable technology. TSMC is using its extensive expertise in generating process design kits for advanced IC processes along with their significant experience and long historic relationships with EDA players like Mentor Graphics to jump out well ahead of their OSAT (outsource assembly and test) competitors in bringing FOWLP technology into real production use.

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