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Semiconductor Expert Forum

Podcast EP237: The Expanded Use of Functional Test Patterns for Manufacturing with Robert Ruiz

Podcast EP237: The Expanded Use of Functional Test Patterns for Manufacturing with Robert Ruiz
by Daniel Nenni on 07-26-2024 at 10:00 am

Dan is joined by Robert Ruiz, a product management director responsible for strategy and business growth of several verification products at Synopsys. Robert has held various marketing and technical positions for leading functional verification and test automation products at various companies including Synopsys, Novas Software, and Viewlogic Systems. He has more than 30 years of experience in advanced EDA technologies and methodologies and spent several years designing application-specific integrated circuits (ASICs).

Dan explores the growing use of functional test patterns in manufacturing test with Robert. Due to the high reliability demands for application areas such as automotive and medical, functional patterns must be used to deliver highly reliable silicon – ATPG vectors are no longer enough. Robert discusses these changes, including the development of new fault models and the work Synopsys is doing to deploy its golden VCS simulator to handle expanded testability demands.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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CEO Interview: Dr. Babak Taheri of Silvaco

CEO Interview: Dr. Babak Taheri of Silvaco
by Daniel Nenni on 07-26-2024 at 6:00 am
Categories: CEO Interviews, EDA, Silvaco

Babak Taheri Headshot

Babak A. Taheri, Ph.D., has served as Chief Executive Officer and member of the Silvaco board of directors from August 2019 to September 2021 and from November 2021 to present. From October 2018 to August 2019, Dr. Taheri served as our Chief Technology Officer and Executive Vice President of Products.

Tell us about your company?

Silvaco Group, Inc. (Nasdaq: SVCO) is a provider of software platforms for design, fabrication, and SIP solutions. We specialize in generating accurate and AI-assisted digital twin modeling for faster and lower-cost product development and manufacturing for our customers. Our customers utilize our solutions in several large and growing markets, including display, power, memory, automotive, high-performance computing, foundries, photonics, the Internet of Things, and 5G/6G. Silvaco is headquartered in Santa Clara, California and has a global presence with offices in North America, Europe, Brazil, China, Japan, Korea, Singapore and Taiwan.

What application areas are your strongest?

Silvaco has been working with customers on their next generation products for decades with a proven track record. Examples of applications include:

  • Power Semiconductor such as GaN/SiC for automotives including EV, Chargers, and automotive power systems
  • Displays including photonics design and fabrications for display panels from watches, to automotive, to industrial applications
  • Memory devices such as DRAM, Flash, and new advanced embedded memories such as MRAM, ReRAM,
  • Foundries including AI assisted Fabrication Technology Co-Optimization (FTCO TM) through AI and accurate digital twin modeling
What keeps your customers up at night?  

As Semiconductor and photonics industries pursue the next generation of products, our customers face several critical challenges in semiconductor design and fabrication that keep them up at night. These include:

  • Complexity and Scale: The increasing complexity and scale of semiconductor designs and manufacturing make it difficult to manage and verify every aspect of the design process efficiently.
  • Time-to-Market  Pressure: Rapid advancements in technology and fierce market competition create immense pressure to shorten the time-to-market for new products while maintaining high-quality standards.
  • Cost Management: Balancing the costs of research and development, manufacturing, and operational processes is a constant concern, especially when dealing with advanced technologies that require significant investment.
  • Technological Innovation: Keeping pace with technological innovation, such as the transition to smaller process nodes, new materials, and advanced packaging technologies, presents ongoing challenges.
  • Yield Optimization: Ensuring high yield rates in fabrication is crucial for profitability. Identifying and mitigating potential issues that could affect yield is a top priority.
  • Supply Chain Stability: The global supply chain for semiconductors is complex and can be affected by various factors, including geopolitical tensions, natural disasters, and pandemics, which can disrupt production and delivery schedules.
  • Regulatory Compliance: Adhering to international regulations and standards in different regions requires continuous monitoring and adaptation to ensure compliance.
  • Intellectual Property Protection: Safeguarding intellectual property from infringement and theft is a significant concern in an industry driven by innovation.
What does the competitive landscape look like and how do you differentiate?

The electronics design automation and manufacturing software market is highly completive yet large and expanding. From major competitors to emerging ones, Silvaco has always addressed the new and emerging challenges our customers face in their respective markets. We are addressing customer needs and further expanding the market with advances in AI and digital twin modeling, enabling semiconductor fabs to produce products cheaper, faster and with better quality. This technology addresses the manufacturing aspect, whereas historically, EDA companies have primarily focused on design. Additionally, we focus on fast growing markets, allowing us to expand geographically and address customer needs with agile R&D.

What new features/technology are you working on?

At Silvaco, the majority of our revenue comes from advanced R&D projects that our customers are working on. We typically work on projects that are 2 to 5 years ahead of production.  Our top growing markets are Power, Display, Memory and Foundry. We are working on the next generation of technologies in these markets using AI and digital twin modeling to address complexity, scale, cost, and time to market for our customers.

How do customers normally engage with your company?

At Silvaco, we employ a variety of customer engagement models to ensure that we meet the diverse needs of our clients. Our engagement models include:

  1. Direct Sales and Support:
    • We maintain a robust direct sales team that works closely with customers to understand their specific requirements and provide tailored solutions. We view our customers as partners in the R&D process.
    • Our dedicated support teams (Including FAEs, CEAs and R&D) offer ongoing assistance, troubleshooting, and optimization services to ensure that our customers get the most out of our products.
    • We provide agile R&D for customer that need to differentiate and off-the-shelf solutions are not adequate. We sometimes call this “Just in Time R&D”.
  2. Enterprise Agreements:
    • We offer enterprise agreements that provide comprehensive access to our entire suite of tools and service or parts thereof.
    • These agreements are customized to meet the unique needs of each customer, often including dedicated support teams and strategic planning sessions.
  3. Partnership and Collaboration:
    • We collaborate with customers on joint development projects, particularly in cutting-edge areas like AI-assisted design, fabrication, and advanced process nodes.
    • These partnerships often involve co-development and co-investment in technology that benefits both parties.
  4. Training and Education:
    • We provide extensive training programs, workshops, and webinars to help our customers stay up-to-date with the latest tools and techniques.
    • Our education initiatives ensure that customers’ teams are proficient in using our solutions which enable them to maximize their effectiveness.
  5. Voice of Customer is our Customer Success Program:
    • Our customer success teams work proactively with clients to ensure they achieve their desired outcomes using our products.
    • Regular check-ins, performance reviews, and feedback sessions help us continuously improve our offerings and support.
  6. Technical Collaboration and Customization:
    • We engage in technical collaboration with customers to customize our solutions to their specific needs.
    • This can involve bespoke development, integration with existing workflows, and the creation of unique features or functionalities.
  7. Community and Ecosystem Engagement:
    • We foster a strong community around our products, encouraging customers to share knowledge, best practices, and feedback.
    • Participation in industry consortia, forums, and user groups helps us stay aligned with the latest trends and customer needs.
Also Read:

CEO Interview: David Heard of Infinera

CEO Interview: Dr. Matthew Putman of Nanotronics

CEO Interview: Dieter Therssen of Sigasi

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Empowering AI, Hyperscale and Data Center Connectivity with PAM4 SerDes Technology

Empowering AI, Hyperscale and Data Center Connectivity with PAM4 SerDes Technology
by Kalar Rajendiran on 07-25-2024 at 10:00 am
Categories: AI, Cadence, EDA, IP

High Speed PAM4 SerDes Use Scenarios

The rapid expansion of data-intensive applications, such as artificial intelligence (AI), high-performance computing (HPC), and 5G, necessitates connectivity solutions capable of handling massive amounts of data with high efficiency and reliability. The advent of 224G/112G Serializer/Deserializer (SerDes) technology, utilizing PAM4 (Pulse Amplitude Modulation 4-level) signaling, represents a significant leap in addressing these demands. Yang Zhang, a senior product line manager at Cadence’s Silicon Solutions Group, gave a talk at the ChipEstimate.com Booth at the recent Design Automation Conference (DAC) on this topic.

Importance of PAM4 High-Speed SerDes

Increased Data Throughput: PAM4 modulation effectively doubles the data rate compared to traditional NRZ (Non-Return-to-Zero) encoding by transmitting two bits per symbol instead of one. This capability is critical for hyperscale data centers and AI applications, which require rapid data transmission to manage vast data volumes efficiently.

Power Efficiency: By enabling higher data rates without proportionally increasing the signaling rate, PAM4 technology manages power consumption and heat dissipation more effectively. This efficiency is vital for maintaining operational costs and thermal management in large-scale data centers.

Scalability and Integration: PAM4 SerDes supports high interconnect density, crucial for scaling data center networks. Its integration into advanced packaging solutions, such as chiplets and co-packaged optics, further enhances performance and scalability by reducing latency and improving signal integrity.

Use Scenarios for High-Speed SerDes

High-speed SerDes technology is highly adaptable, catering to various reach requirements essential for modern connectivity solutions. For long-reach (LR) applications, SerDes is suitable for backplane copper cables, chip-to-chip, and backplane scenarios, ensuring reliable communication over extensive distances. Medium reach (MR) applications, such as chip-to-chip, benefit from a balance of performance and distance. Meanwhile, short reach (VSR and XSR) are ideal for chip-to-module, near-package optics, die-to-die and co-packaged optics applications, offering ultra-low latency and high bandwidth within a confined area.

These diverse application domains demonstrate the versatility and critical role of high-speed SerDes technology. In data centers, it supports the essential need for rapid and reliable data transmission within and between facilities. AI and HPC applications demand high bandwidth and low latency to efficiently process large datasets, a requirement well-served by SerDes technology. With the advent of 5G, telecommunications also benefit significantly from high-speed SerDes, ensuring robust and high-speed connections that facilitate seamless transfer of substantial amounts of data.

Ethernet in Data Center Operations

Ethernet technology is integral to data center operations, providing versatile solutions across long-reach, medium-reach, and short-reach applications. For long-reach, Ethernet connects various parts of the data center infrastructure over longer distances. Medium-reach Ethernet supports chip-to-chip scenarios, balancing performance and distance. Short-reach Ethernet caters to chip-to-module, near-package optics, die-to-die and co-packaged optics applications, ensuring ultra-low latency and high bandwidth within confined spaces. These varied applications underscore Ethernet’s critical role in maintaining efficient, high-performance data center operations.

The Ultra Ethernet Consortium (UEC)

While ethernet solutions are optimized for low latency to support high-speed data transfers and efficient processing, continued advancements are crucial. The Ultra Ethernet Consortium (UEC), founded under the Linux Foundation, aims to enhance Ethernet for high-performance computing and AI applications. UEC’s mission is to develop Ethernet-based solutions that rival technologies like InfiniBand, offering flexibility, high performance, and cost-effectiveness. By improving Ethernet’s transport layers and introducing features such as advanced congestion control and multi-pathing, UEC seeks to meet the specific needs of AI and HPC workloads.

Cadence’s Leadership in SerDes Technology

The company’s solution offerings include industry-leading 224G/112G/56G PHY IPs and controller IPs. These solutions not only support subsystems up to 800G/1.6T but also exhibit exceptional silicon performance, proven in both Cadence test chips and customer production chips.

In addition to LR, MR, VSR and XSR support, Cadence’s solutions support Ultra Long Reach (ULR) as well. Through its membership in the UEC, Cadence also plays an active role in the UEC’s effort to advance ethernet to support future AI and HPC applications demands.

Highlights

Maximum Likelihood Sequence Detector (MLSD) and Reflection Cancellation are two main features of their SerDes solutions.

The integration of MLSD in high-speed SerDes technology represents a significant advancement in signal processing for data transmission. By leveraging the Viterbi algorithm, MLSD provides substantial improvements in BER and mitigates the effects of far-out reflections, all while maintaining power efficiency. These are important, particularly in applications requiring low latency and high bandwidth, such as AI, HPC, and data center connectivity.

The incorporation of reflection cancellation techniques helps improve the Bit Error Rate (BER) and overall reliability of data transmission. Reflections can be caused by various design impairments such as connector coupling, package/PCB impedance mismatch, and package crosstalk, significantly impacting the link’s BER in production systems. Reflection cancellation can improve BER by one to two orders of magnitude.

Summary

The deployment of 224G/112G PAM4 SerDes technology is crucial for meeting the increasing demands of hyperscale connectivity, AI, and networking applications. Cadence’s advanced SerDes solutions, with their proven performance and versatility, play a significant role in this technological shift. As the industry continues to evolve, the innovations led by consortia like the UEC will further enhance Ethernet’s capabilities, ensuring it remains a cornerstone of global communication and data exchange infrastructure.

You can learn more here.

Also Read:

Accelerating Analog Signoff with Parasitics

Novelty-Based Methods for Random Test Selection. Innovation in Verification

Using LLMs for Fault Localization. Innovation in Verification

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CEO Interview: Dr. Pierre-Yves Lesaicherre of Finwave

CEO Interview: Dr. Pierre-Yves Lesaicherre of Finwave
by Daniel Nenni on 07-25-2024 at 10:00 am
Categories: CEO Interviews

Dr. Lesaicherre holds an MBA with a focus on International Business and Strategy from INSEAD, and has an MS degree and a PhD degree in Material Science from the Grenoble Institute of Technology (Grenoble INP).  He is a Board Leadership Fellow, Governance Fellow and Director Certified for NACD (National Association of Corporate Directors) and an active member of NACD and SVDX (Silicon Valley Director’s Exchange).

Tell us about your company?

Finwave is a leading GaN (Gallium Nitride) semiconductor company with a disruptive 8” GaN-on-Si technology for 5G/6G cellular infrastructure, handset market and other RF applications. Finwave was founded in 2012 by world-leading technologists from MIT, whose ground breaking invention has been recognized by the prestigious IEEE George Smith Award. Finwave has developed a proprietary, low-cost manufacturing process that leverages existing 8” Si fab infrastructure for significant cost reduction and that is particularly well suited to deliver high-performance RF Switches and Power Amplifiers. With its scalable technology innovation, Finwave is unlocking the true power of GaN for RF applications.

What problems are you solving?

Finwave’s GaN on Si technology unlocks the true power of GaN. Finwave’s 3DGaN FinFET technology brings significant linearity improvement and power efficiency improvement for 5G/6G infrastructure applications.

In addition, Finwave’s enhancement-mode, low-voltage GaN MISFET technology enables high-performance handset RF Front-End (RFFE) applications for the first time, besting the competing GaAs technology in both cost and performance.

Finwave’s GaN-on-Si Switch technology delivers broadband, high-power RF switches with fast switching and fast settling at mmWave frequencies and above.

Lastly, Finwave’s GaN-on-Si technology is produced on standard 8” Si CMOS fabrication tools, not only significantly reducing manufacturing cost but also enabling “Moore’s Law” for GaN technology to be scaled from 8” to 12”, from 0.18um to deeply scaled transistor nodes.

What application areas are your strongest?

The strongest applications for Finwave in order of importance are (i) 5G/6G infrastructure (Base Stations, FWA – Fixed Wireless Access, CPE – Customer Premise Equipment), (ii) 5G/6G handset front-end modules and (iii) Military and Aerospace applications (Satcom, Radar, military communications and other Mil/Aero RF applications). Finwave products are also used in Test Equipment and Medical Equipment applications.

What keeps your customers up at night?

In most advanced RF communication applications, the issues of linearity, power efficiency, ability to deliver high power at mmWave frequencies and switching speed are front and center. Cost and the ability to integrate RF components into an RF Front-End device or RF Front-End module are also very important considerations.

With Finwave proprietary GaN-on-Si technology, we offer high-performance RF devices in a very cost-efficient process technology, as well as the ability to integrate an RF Switch, Power Amplifier and Low Noise Amplifier into a single technology and possibly a single chip, thus simplifying our customers’ system design and lowering their component sourcing costs.

With Finwave proprietary GaN-on-Si technology, we offer Power Amplifier products with enhanced linearity and enhanced power efficiency as well as RF Switch products with fast switching times and high-power capability up to 40W at mmWave frequencies.

What does the competitive landscape look like and how do you differentiate?

We are one of the few RF semiconductor companies with a portfolio of RF Switches and Power Amplifiers manufactured in GaN-on-Si technology. Most existing GaN-on-Si semiconductor companies are focusing on Power Electronics rather than RF applications.

We differentiate ourselves from other RF semiconductor companies with our high-performance and proprietary GaN-on-Si process technology and device architecture that allow Finwave to deliver performance for RF Switches and Power Amplifiers not achievable with other technologies.

In the Telecom Infrastructure space, we compete with GaN-on-SiC semiconductor companies, who have a much less favorable cost structure because of the high cost of SiC wafers and the limitations in scaling SiC wafer manufacturing up to 8” and eventually 12”.

In the handset Power Amplifier and Rf Front-End module market, we compete with GaAs HBT technology, which has limitations in its ability to deliver high power at mmWave frequencies.

In the RF Switch market, we compete with RF-SOI technology and pin-diode manufacturers. RF-SOI has limitations in terms of the power that can be delivered, especially above 10W, and pin-diodes are expensive components that require a lot of board real estate as well as additional components to operate.

How do customers normally engage with your company?

To engage with Finwave, customers can either talk to us directly or through a network of RF semiconductor distributors that we are in the process of expanding. The easiest way to get in touch with us or to get information about our technology and products is through our company web site at https://www.finwavesemi.com/

Also Read:

CEO Interview: Pim Donkers of ARMA Instruments

CEO Interview: Dr. Babak Taheri of Silvaco

CEO Interview: Orr Danon of Hailo

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Samtec Simplifies Complex Interconnect Design with Solution Blocks

Samtec Simplifies Complex Interconnect Design with Solution Blocks
by Mike Gianfagna on 07-25-2024 at 6:00 am
Categories: Samtec, Semiconductor Services

Samtec Simplifies Complex Interconnect Design with Solution Blocks

The development of cost effective, high-performance silicon to silicon interconnect at the system level can be a vexing problem. So many choices, which one will work best? Ease of use and customer support are woven into the DNA of Samtec. Almost four years ago I explored the company’s focus on putting the customer first here. Fast-forward to today, the options are more plentiful, and the complexity has gone up. This is why a new approach from Samtec to make it easier to identify the best interconnect architecture caught my eye. Let’s explore how Samtec simplifies complex interconnect design with Solution Blocks.

Silicon-to-Silicon Solutions, Simplified

Thanks to the incredible rise in AI/ML applications, data centers are experiencing disruptive demands regarding compute performance and data throughput. These demands put extreme stress on both copper and optical channels. Finding the right mix of technologies to support these new AI-fueled demands is far from simple.

From standard cataloged products to unique high-performance design, Samtec’s Solution Blocks are designed to support any interconnectivity need, regardless of application, performance requirements or environment. Let’s examine the various Solution Blocks Samtec offers to organize and simplify high-performance channel design.

High-Speed Board-to-Board and Backplane

In this Solution Block, we explore high speed connectors, mezzanine systems with integral ground planes, high-density arrays, backplane interconnects, rugged signal integrity optimized Edge Rate® systems and high-speed performance to 56 Gbps NRZ/112 Gbps PAM4. Some of the options offered here include:

High-Speed Performance, with speeds to 112 Gbps PAM4. More than 4.0 Tbps of aggregate bandwidth and extremely low crosstalk beyond 40 GHz.

Application Flexibility that includes 10-1,000 positions with 1 mm – 40 mm stack heights and vertical, right-angle, edge mount configurations.

Signal Integrity Support with free test reports, models, app notes, and break out region. Easy access to live EE support and a unique Channelyzer® online tool.

There is a substantial pallet of connectors to get the job done. These include: High-Density Arrays, High-Speed Dual Row Strips (Mezzanine), High-Speed Edge Cards, Ultra Micro Interconnects, and Backplane Connectors. The figure below summarizes the bandwidth options that are available.

High speeds & increased bandwidth with optimized signal integrity

Optics Transceiver Solutions

When power and bandwidth demands become unmanageable for copper, optical interconnect becomes attractive. Samtec is the industry-leading provider of mid-board optical transceiver solutions.  Reliable signal integrity over an extended distance in chip-to-chip, board-to-board, on-board and system-to-system connectivity is what attracts design teams.

Optical channel design can be quite challenging. Optical products include Samtec’s Sudden Service® – full engineering support, online tools and that strong service attitude I mentioned previously. Some of the attributes of this product line include:

Low power that delivers minimal power usage per module in a small footprint. This allows for high-density placement close to the IC for significant power savings in the overall system.

Small form factor is enabled thanks to the flexibility of copper and optical using the same micro connector. This allows for increased density, simplified PCB and reduced power dissipation.

High-performance versatility because the data connection is taken “off board” for up to 28 Gbps per lane with a path to 112 Gbps PAM4 via optical cable at greater distances.

Integrated thermal management with a variety of integral heat sinks or through-the-board cooling provides optimal thermal control for harsh environments and wide temperature ranges.

A complete range of optical cables and connectors are available, supported with evaluation boards and development kits.

High-Speed Cable Interconnect Solutions

When copper is the choice, Samtec’s high-speed cable systems – Flyover® and HDR – provide innovation for next generation architectures with industry leading support, in-house manufacturing and customization capabilities to create a solution for any application.

There is wide selection of cable interconnects available in this Solution Block. Some of the key attributes include:

Flyover® Architecture that improves signal integrity & reach at higher data rates. In-house high-level design & engineering support is available to ensure a successful design supported by full system signal integrity expertise.

Flexibility & Customization facilitated by mix & match connector end options, extensive customization capabilities, and modular backplane flexibility.

Manufacturing is done by Samtec, with R&D/manufacturing of precision extruded cable & next gen RF cable in several global locations. The company offers multiple proprietary ultra-high performance cable technologies.

With this extensive product line, you can configure an optimal solution across many requirements. Solution Blocks helps to sort out the details for you.

RF Interconnect Solutions

Most systems will require some level of RF communication. Samtec offers complete RF interconnect solutions supporting traditional sub-6 GHz frequencies to 110 GHz microwave/mmWave frequencies (sub-Terahertz spectrum). Products include end-to-end RF cable assemblies, board connectors, cable connectors, adaptors and Samtec Original RF Solutions.

Samtec offers a wide range of RF cables and connectors to address just about any requirement. Some attributes of this product line include:

Cables included are phase & amplitude stable cables, microwave assemblies to 110 GHz, and RG cable solutions (RG316, RG174, RG178, etc.).

Connectors, including compression mount for test & measurement applications, board-to-board & cable-to-board, and precision in-series & between-series adaptors.

Taking Solutions Blocks for a Test Drive

Beyond presenting all the relevant product information in one place, Solution Blocks provide interactive, guided product selection to get your best choice fast. Links are coming so you can try it out for yourself. Here is a real session I did with the system:

Under the High-Speed Board-to-Board Solution Block, I pressed Explore Picture Search. That took me to a Solutionator screen. I then began making selections.

I chose an Edge Card connector type. This dynamically changed the balance of choices to be consistent with an edge card. Next, I chose a Vertical orientation with a .8mm pitch. I then chose 20 and 32 as valid position choices and a .062” card thickness. I was then presented with 9 results that fit my criteria. The system informed me I could click on any row for items like 3D models and free samples.

Below is a screen shot of the results. Assembling this list of valid options took seconds. Without Solution Blocks it would entail a lot of research.

Edge Card Exploration Results

To Learn More

Samtec’s Solutions Blocks can save you a lot of time on your next system design. I highly recommend you check it out. You can access the capability here. Don’t forget to try the Explore Picture Search functions. It’s a lot of fun to see what is compatible with what. And that’s how Samtec simplifies complex interconnect design with Solution Blocks.

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Perforce IP and Design Data Management #61DAC

Perforce IP and Design Data Management #61DAC
by Daniel Payne on 07-24-2024 at 10:00 am
Categories: EDA, Events, Perforce

Helix IPLM, Helix Core min

I recall first blogging about Helix IPLM (formerly Methodics IPLM) at DAC in 2012, then Perforce acquired the company in July 2020, so I stopped by the Perforce booth this year at DAC to get an update from Martin Hall, Principal Solutions Engineer at Perforce. Martin’s background includes working at Dassault Systemes, Synchronicity, Innoveda and Texas Instruments. The four big messages this year were:

  1. Managing costs and footprint in an AI world
    More effective management of costs through IP-centric design practices and managing/enforcing traceability for high value IP — such as AI GPUs and cores, and low power components — to help reduce power running costs and footprints.
  2. The critical need for AI data set management
    AI depends on curating large amounts of data on which to train models, but this data needs to be reviewed and cleaned to avoid pollution. Plus, new data needs to be onboarded in a measured way, and secondary data sets need to be weighted to influence AI outcomes appropriately.
  3. Plans for the commoditization of AI
    As the world of AI designs evolve, expect to see a move away from proprietary models to third-party AI solutions (standard AI processing units) that can be used as building blocks. Efficiently managing the AI IP supply chain is going to be vital, to reduce complexity, enable scale, improve security and prevent IP leakage.
  4. What’s new in Perforce Helix IPLM and Helix Core
    Helix IPLM and Helix Core together provide a unified, scalable IP and design data management platform that tracks IP and its metadata across projects, providing end-to-end traceability and enabling IP reuse. Some tier-one semiconductor firms use Perforce solutions for IP and data management, like NVIDIA, Micron, and Samsung.

Martin walked me through a demonstration of the Helix tools, where Helix Core takes in design files and Helix IPLM performs configuration management operations to enable an IP-level abstraction of these files. Beyond the base design file content, these configurations can also include data sheets, requirements, and meta-data representing the quality and state of the IP in its lifecycle. The resulting database is used to build workspaces, a centralized, corporate IP catalog, and generally organize the IP ecosystem across the enterprise.

This increased level of transparency of the corporate IP assets will increase IP reuse, saving time and money. This approach also provides complete traceability for a project and its constituent IP hierarchy. As a project moves through its lifecycle, each release can be memorialized as an object in the Helix IPLM platform. Important releases can be tagged and easily identified. For example, when an LVS/DRC clean physical implementation is reached for an IP. Releases can also be controlled to implement certain design methodology steps and then further qualified to manage upstream integration, improving IP quality and control throughout the enterprise.

The Bill of Material (BoM) defines the complete SoC IP hierarchy, including its subsystems, PDKs, SW and all of the dependencies. In Helix IPLM, an IP can be any SoC component, including design data, material meta-data, or even the design tool versions being used. Traceability is enforced by Helix IPLM using immutable releases for each asset, including the parent project. Each engineer on a project has a workspace that renders the design files from the BoM hierarchy, and team members are notified as changes are made or bugs issued. Helix IPLM is integrated with EDA vendor flows, Jira for bug tracking, and includes helpful analytics. Git, Subversion, and ClearCase are also supported as alternatives to Helix Core for the data management layer.

Helix IPLM, Helix Core

Part of Martin’s demo showed how an SoC with many IP blocks had an issue with an ADC block. In this scenario, the ADC vendor had changed their IP and then re-ran DRC/LVS, so a new version of the ADC block was released. The team was informed of the new release, reviewed the details, then integrated the new version into their SoC. This tight communication loop improves the design team’s velocity.

With Helix IPLM the user can quickly view all of the library elements as IP blocks in the web interface, or via the command line if preferred, to query the design. In Martin’s demo, Virtuoso was used to make schematic edits on an IP, and meta-data was used to tag this as a work in progress. A new release was made, and checks were run for consistency.  To make the release the DRC had to be clean first, and finally the IP version gets updated. Users can view the complete history for any IP to understand what has changed in each release version. Your team gets to enforce its own methodology as a set of rules, scripts, triggers and schema, so that each IP has management governance.

Summary

Designing an SoC is a complex endeavor, requiring scalable data management, IP lifecycle management and an open architecture to co-exist with all popular EDA tool flows. Perforce has been offering an IP Lifecycle Management tool for many years now with Helix IPLM, along with data management through Helix Core. The combination of Helix IPLM and Helix Core have been demonstrated at the major semiconductor design companies, so it’s worth taking a closer look at for your organization.

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IROC Introduces an Upgraded Solution for Soft Error Analysis and Mitigation #61DAC

IROC Introduces an Upgraded Solution for Soft Error Analysis and Mitigation #61DAC
by Mike Gianfagna on 07-24-2024 at 6:00 am
Categories: EDA, Events, IROC Technologies

DAC Roundup – IROC Introduces an Upgraded Solution for Soft Error Analysis and Mitigation

#61DAC Is the place to go for the latest ideas, technology and products for semiconductor design and manufacturing. Between the exhibit floor and the technical program, you can get a vast education on almost any topic. In this post, I will focus on a unique company and a new version of a unique solution. IROC Technologies specializes in helping the semiconductor industry evaluate and manage reliability risks during chip design to minimize soft errors over the life of the design. Advanced semiconductor processes make circuits more sensitive to soft errors and the growing use of these circuits in reliability-critical applications demands protection against glitches of all kinds. Here are some useful details from the show floor where IROC introduces an upgraded solution for soft error analysis and mitigation.

What’s New and Why It Matters

I recently covered a critical part of the technology portfolio from IROC – TFIT.  This tool delivers a best-in-class transistor/cell level soft error simulator. It essentially performs a comprehensive analysis of the circuit and particle interactions to determine if there is a potential for soft errors to occur. What is unique about the software is that it runs models using a standard SPICE simulator. Other approaches require 3D TCAD simulators which are hard to setup and run slowly, so TFIT makes detailed analysis of circuits much more accessible since it runs 100X faster than TCAD simulators. Partnerships with major foundries also ensure accurate results.

As discussed in the prior post, TFIT can be used to calculate the SER of basic cells and helps optimizing the layout of radiation hardened designs.. Once a system is built with these  basic cells, the next question to answer is how resilient the overall system is to soft errors. IROC’s SoC Failure in Time (SoCFIT) addresses this challenge, and a new version of the tool was announced at #61DAC.

SoCFIT and Its Role in Soft Error Analysis and Mitigation

Dr. Maximilien Glorieux

I was fortunate to be able to spend some time at the IROC booth with Dr. Maximilien Glorieux, the CTO at IROC. Max has been a key driving force for tools like SoCFIT, so it was a very informative discussion. Max began by explaining that SoCFIT essentially provides the next level of analysis after TFIT.

The tool embeds a fault simulator, but it’s not like the ones used for test coverage that most of us are familiar with. These products inject faults (typically stuck at one or zero) into a circuit to see if a set of test vectors will find the fault. After applying the test vectors, if the output of the faulty circuit is different from the good circuit, that fault is deemed to be “covered”. 

Max explained that SoCFIT was doing a different kind of analysis. In this case, faults from single event upsets are injected into the circuit and the focus is on how these glitches propagate through the circuit. Many don’t propagate and so don’t represent high risk. But some do, and those logic paths must be fortified with approaches such as redundant logic and arbitration circuits to monitor the outputs of the redundant elements. If there is a discrepancy, the faulty data is filtered-out, and the back-up copies are used.

Protecting the whole SoC is an expensive process in terms of area and power, so a tool like SoCFIT is critical to ensure only the risky areas of the system are treated. The tool coordinates and analyzes a large amount of information about the system as shown in the graphic at the top of this post. Max explained that this work helps meet stringent functional safety standards by identifying critical circuit weakness from the earliest stages and throughout the design cycle.

Some of the features of SoCFIT include:

  • Comprehensive error propagation analysis: evaluates fault propagation based on circuit structure and simulation vectors
  • Detailed vulnerability reporting: computes logical (LDR), temporal (TDR), functional (FDR) de-rating/vulnerability factors
  • Broad design language support: compatible with SystemVerilog, Verilog, and VHDL, fitting seamlessly into existing workflows
  • Scalable for large designs: handles over 1 million flip-flops per partition, bottom-up approach makes it ideal for even the most complex SoC
  • Ultra-fast simulation: achieves over 1,000X faster simulations than typical approaches, drastically reducing analysis time
  • Extensive reporting: generates detailed reports highlighting the contribution of each cell, module, and instance to the overall FIT rate
  • Efficient mitigation strategies: provides clear guidelines for mitigating vulnerabilities, helping you develop robust and reliable designs

Max went on to describe the features of the newest release of SoCFIT, that includes FDR FastSIM, an ultra-fast fault propagation simulation engine. This capability allows an efficient functional de-rating analysis about 1,000 times faster than conventional methods. Max also mentioned that the tool is designed to integrate seamlessly into the whole digital design flow, significantly improving end-product reliability by mitigating transient fault threats early. Its advanced features and speed make it ideal for handling complex SoC designs, maintaining accuracy and efficiency throughout the process.

To Learn More

I came away from my visit with Max knowing a lot more about what IROC can do for a wide range of designs, and why the work they are doing is so important. If high-reliability operation is important in your design work, you should learn more about how IROC can help. You can get an overview of how IROC fits into many markets here. And you can get more details on SoCFIT here.  And that’s how IROC introduces an upgraded solution for soft error analysis and mitigation at #61DAC.

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Cadence® Janus™ Network-on-Chip (NoC)

Cadence® Janus™ Network-on-Chip (NoC)
by Kalar Rajendiran on 07-23-2024 at 10:00 am
Categories: Cadence, EDA, IP

Design Flow when using Janus NoC

A Network-on-Chip (NoC) IP addresses the challenges of interconnect complexity in SoCs by significantly reducing wiring congestion and providing a scalable architecture. It allows for efficient communication among numerous initiators and targets with minimal latency and high speed. A NoC facilitates design changes, enabling quick iterations to meet specific design goals regarding bandwidth, latency, area, and power. Cadence recently expanded their system IP portfolio with the addition of the Janus NoC IP. At the surface, it may prompt the question, what is the big deal, NoC IP is not a new concept and this type of IP is common in the industry. I got deeper insights by chatting with Cadence’s George Wall, group director of product marketing and Ronen Perets, senior product marketing manager, both in the Cadence Silicon Solutions Group.

Integral Subsystem Component

The Cadence Janus NoC IP is in response to requests from the company’s customer base for expanded system-level solutions. This IP is an integral part of Cadence’s silicon solutions strategy, aimed at providing significant value to its licensee partners. It leverages Cadence’s extensive design expertise and best-in-class verification tools and methodologies, ensuring that the NoC meets the highest standards of quality and performance. This strategic addition enhances Cadence’s portfolio, making it a crucial component for advanced SoC designs. The IP is designed to handle inter-chiplet communication efficiently, using programmable routing and supporting dynamic configurations. The NoC is designed to support the evolving multi-chip module and chiplet-based design architectures. This adaptability ensures future-proofing for increasingly complex SoC designs.

Leverages Cadence’s Extensive Portfolio of Software and Hardware Offerings

Cadence offers a comprehensive system solution that includes processors with a full set of Software Development Tools (SDT) and Software Development Kits (SDK), Digital Signal Processors (DSP), libraries, and frameworks, I/O controllers to facilitate various interface requirements, and PHY for physical layer implementations ensuring reliable data transmission. The Cadence Janus NoC enhances performance, power, and area (PPA) by efficiently managing high-speed communications within and between silicon components with minimal latency. By optimizing RTL for PPA and utilizing packetized messages, the NoC reduces wire count and mitigates timing closure challenges, thereby accelerating time to market.

Architectural Exploration and Verification

Cadence offers extensive simulation and emulation options to support architectural exploration and verification. The Palladium Accelerator provides full visibility and increases simulation speed, making it ideal for extensive performance benchmarking. The Protium Platform maps the full SoC onto FPGAs for extremely fast emulation, which is particularly useful for debugging at the SoC level. SystemC modeling allows for fast debugging and firmware bring-up using a functional SystemC model generated alongside the RTL. Additionally, the Cadence Helium Virtual and Hybrid Studio enables the mixing of different model types and running each module on different platforms, facilitating performance monitoring and rapid iteration.

Designed for Ease of Use

The Cadence Janus NoC is designed with ease of use in mind, offering a highly configurable and flexible architecture. It features a GUI configuration tool that allows users to easily configure and generate NoC RTL, and comes with a comprehensive package that includes synthesis scripts, a testbench, and a functional model, streamlining the design process. Early optimization of NoC design is facilitated through iterative design exploration and performance validation using Cadence simulation and emulation technologies, along with the Cadence System Performance Analysis (SPA) tool, ensuring that the architecture meets performance needs.

Cadence Janus NoC Architecture

The Cadence Janus NoC architecture consists of three main components: the Initiator Endpoint Adapter (IEA), which connects initiator endpoints to the NoC; the Target Endpoint Adapter (TEA), which connects target endpoints to the NoC; and the Routing Node, which routes packets between IEAs and TEAs to their respective destinations. A typical NoC comprises multiple IEAs, TEAs, and routing nodes. These nodes are interconnected, allowing messages to traverse from origin to destination efficiently. Routing nodes can be configured to optimize bandwidth and latency, with pipeline stages added to maintain the desired speed despite physical distance challenges.

Summary

The Cadence Janus NoC architecture offers a scalable, efficient, and adaptable approach to addressing the complex interconnect requirements of modern SoCs. With advanced configuration tools, robust simulation and emulation options, and comprehensive power management and verification strategies, Cadence’s NoC technology empowers designers to create optimized, high-performance SoCs efficiently and effectively. By managing high-speed communications efficiently, the Janus NoC helps design teams achieve their PPA targets faster and with lower risk, freeing up valuable engineering resources for SoC differentiation. As the industry continues to evolve, Cadence Janus NoC stands as a future-proof platform, enabling designers to meet current and future demands with confidence.

You can learn more about the Janus NoC System IP from here.

Also Read:

Accelerating Analog Signoff with Parasitics

Novelty-Based Methods for Random Test Selection. Innovation in Verification

Using LLMs for Fault Localization. Innovation in Verification

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A Joint Solution Toward SoC Design “Exploration and Integration” released by Defacto #61DAC

A Joint Solution Toward SoC Design “Exploration and Integration” released by Defacto #61DAC
by Daniel Nenni on 07-23-2024 at 6:00 am
Categories: Defacto Technologies, EDA, Events

flow ip explorer soc compiler (1)

When I was at DAC last month, I had the chance to talk with Chouki Aktouf and Bastien Gratréaux from Defacto and they told me about a new innovative solution to generate Arm-based System-on-Chips. I heard that this solution has now been released.

Defacto and Arm developed a joint SoC design flow to help Arm users cover all needed automation—from SoC design architecture and exploration to top-level generation of all needed files for implementation and verification flows.

Through the intuitive graphical interface from the Arm design platform, Arm IP Explorer, helps make specification of the SoC easy and user friendly. Once SoC exploration is realized, RTL and IP-XACT design files are automatically generated using Defacto’s SoC Compiler design solution.

The jointly developed solution is built around a strong link between Arm IP Explorer and Defacto’s SoC Compiler to enable users to generate quickly several SoC design configurations. The speed of the Defacto SoC Compiler enables the generation of a multitude of SoC configurations based on different user specifications. With this solution, the overall design time from specification to an SoC ready for synthesis can be significantly reduced.

Why was this solution needed?

With the complexity of current SoC designs and the design space possibilities, designers and architects face significant challenges when exploring SoC architectures. They traditionally access an IP database, where they select, configure, and download IP. The following step is to connect the IPs to build the complete SoC design database which is ready for logic synthesis. Iterative work is usually needed for each of the configurations created, which impacts overall turn-around time (TAT).

Providing a comprehensive and automated design solution from specification to implementation with all necessary exploration metrics, such as chip size, power consumption, and so on, is needed more than ever.

How it works?

The joint Arm IP Explorer/SoC Compiler solution is the shortest path from the definition of Arm-based system architecture to implementation and design verification.

The first step is that users access Arm IP Explorer and start selecting IP cores from the catalog. IP parameters can be set at this level and IP configuration in general is made easy. With the selected IPs, users can architect the complete system. The platform gives also the flexibility to add custom IPs to reflect the desired system. At this stage, an estimation of the overall size of the SoC is provided.

Integration checks are performed on-the-fly to ensure that the built SoC is correct including all needed and complex connectivity. The completed and validated system is then exported into the Defacto SoC Compiler, which automatically generates the top-level IP-XACT / RTL / UPF files, along with different reports. These reports provide detailed connectivity density, chip size, and power consumption.

The generated files are fully compatible with standard RTL2GDS SoC design flows and can be provided directly to both logic synthesis tools and design verifications tools. With the simplicity, speed, and flexibility of this solution, users can quickly and automatically explore and generate several SoC design configurations.

Who is this solution for?

This solution has been developed for Arm users who need to quickly build new Arm-based SoC configurations. Using this solution users increase efficiency and productivity, making easy to find and compare Arm IPs in a unique source. With the simplified IP configuration, coupled with the automatic generation of the top level SoC, users are drastically reducing costs and time to market.

This flow has already been validated for a large number of systems and is ready to be used for several applications such as IoT, automotive, mobile, 5G, cloud computing, HPC, AI, etc.

More information can be found on the Defacto page on the Arm partner website: https://www.arm.com/partners/catalog/defacto-technologies

To have a dedicated demo and presentation of the flow, feel free to reach out to Defacto by email. (info_req@defactotech.com)

Also Read:

Defacto at the 2024 Design Automation Conference

WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems

Lowering the DFT Cost for Large SoCs with a Novel Test Point Exploration & Implementation Methodology

Defacto Celebrates 20th Anniversary @ DAC 2023!

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TSMC Foundry 2.0 and Intel IDM 2.0

TSMC Foundry 2.0 and Intel IDM 2.0
by Daniel Nenni on 07-22-2024 at 10:00 am
Categories: 3D IC, Foundries, TSMC
7 Comments

TSMC 2Q2024 Investor Call

When Intel entered the foundry business with IDM 2.0 I was impressed. Yes, Intel had tried the foundry business before but this time they changed the face of the company with IDM 2.0 and went “all-in” so to speak. The progress has been impressive and today I think Intel is well positioned to capture the NOT TSMC business by providing a trusted alternative to the TSMC leading edge business. The one trillion dollar questions is: Will Intel take business away from TSMC on a competitive basis? I certainly hope so, for the greater good of the semiconductor industry.

On the most recent TSMC investor call, which is the first call with C.C. Wei as Chairman and CEO, TSMC branded their foundry strategy as Foundry 2.0. It is not a change of strategy, it is a new branding based on what TMSC has been successfully doing for years now, adding additional products and services to keep customers engaged. 3D IC packaging is a clear example but certainly not the only one. The Foundry 2.0 brand is well earned and is clearly targeted at Intel IDM 2.0 which I think is funny and a great example of CC Wei’s sharp wit.

I thought for sure that Intel 18A would be the breakout foundry node for Intel but according to the TSMC investor call, that is not the case. TSMC N3 was a runaway hit with 100% of the major design wins. Even Intel used TSMC N3. I hadn’t seen anything like this since TSMC 28nm which was on allocation as a result of being the only viable 28nm HKMG node out of the gate. History repeated itself with N3 due to the delay of 3nm alternatives. This made the TSMC ecosystem the strongest I have ever witnessed with both the domination of N3 and TSMC’s rapidly expanding packaging success. I had originally thought that some customers would stick with N3 until the second generation of N2 appeared but I was wrong. On yesterday’s investor call:

CC Wei: We expect the number of the new tape-outs for 2-nanometer technologies in its first two years to be higher than both 3-nanometer and 5-nanometer in their first two years. N2 will deliver full load performance and power benefit, with 10 to 15 speed improvement at the same power, or 25% to 30% power improvement at the same speed, and more than 15% chip density increase as compared with the N3E.

CC had mentioned this before but I can now confirm this based on my hallway discussions inside the ecosystem at recent conferences: N2 designs are in progress and will start taping out towards the end of this year.

I really don’t think the TSMC ecosystem gets enough credit, especially after the overwhelming success of N3, but the N2 node is a force in itself:

CC Wei: N2 technology development is progressing well, with device performance and yield on track or ahead of plan. N2 is on track for volume production in 2025 with a ramp profile similar to N3. With our strategy of continuous enhancement, we also introduce N2P as an extension of our N2 family. N2P features a further 5% performance at the same power or 5% to 10% power benefit at the same speed on top of N2. N2P will support both smartphone and HPC applications, and volume production is scheduled for the second half of 2026. We also introduce A16 as our next nanosheet-based technology, featuring Super Power Rail, or SPR, as a separate offering.

And, of course, the TSMC freight train continues:

CC Wei: TSMC’s SPR is an innovative, best-in-class backside power delivery solution that is forcing the industry to incorporate another backside contact scheme to preserve gate density and device with flexibility. Compared with N2P, A16 provides a further 8% to 10% speed improvement at the same power, or 15% to 20% power improvement at the same speed, and additional 7% to 10% chip density gain. A16 is best suited for specific HPC products with complex signal routes and dense power delivery network. Volume production is scheduled for the second half of 2026. We believe N2, N2P, A16, and its derivative will further extend our technology leadership position and enable TSMC to capture the growth opportunities way into the future.

Congratulations to TSMC on their continued success, it is well deserved. I also congratulate the Intel Foundry team for making a difference and I hope the 14A foundry node will give the industry a trusted alternative to TSMC out of the starting gate.  In my opinion, had it not been for Intel and of course CC Wei’s leadership and response to Intel’s challenge, we as an industry would not be quickly approaching the one trillion dollar revenue mark. Say what you want about Nvidia, but as Jensen Huang openly admits, TSMC and the foundry business is the real hero of the semiconductor industry, absolutely.

Also Read:

Has ASML Reached the Great Wall of China

The China Syndrome- The Meltdown Starts- Trump Trounces Taiwan- Chips Clipped

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