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Semiconductor Expert Forum

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WEBINAR: Outrunning the Data Wave – Why we need to keep pace with the coming 400% data surge 

WEBINAR: Outrunning the Data Wave – Why we need to keep pace with the coming 400% data surge 
by Daniel Nenni on 03-12-2026 at 10:00 am
Categories: EDA, yieldWerx

A Practical Blueprint for Scaling the Digital Foundation of Silicon Photonics and Co Packaged Optics (1)

The semiconductor manufacturing industry has hit a new era of data intensity. We know that we need to look at alternatives to silicon and that electrical interconnects are unable to keep pace. We know we need to design more chiplets and alter microchip architecture. But how much data are we talking specifically, and how much time do we have to readjust our analytics to keep pace with the tsunami of data that’s around the corner?

The industry’s response has been multifaceted. Advanced semiconductor design strategies, the adoption of chiplets, and the integration of optical I/O and photonics are enabling higher performance, faster AI computation, and increased modularity. These approaches overcome traditional electrical I/O limits and scale functionality across larger, heterogeneous systems. Yet these same innovations generate massive amounts of data, from design simulations to fab telemetry and optical and electrical test results, creating an unprecedented amount of data growth.

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Measured per wafer, data volumes have already grown dramatically. Modern fabs with high-frequency sensors, inline inspection, multi-stage electrical testing, and optical characterization tools produce tens of terabytes per day. Compared to 2010, this is roughly 100% growth, highlighting that traditional analytics approaches will increasingly struggle, particularly when integrating diverse datasets across advanced architectures.

Accommodating this growth already requires more precise and detailed data genealogy tracking, now multiply that need by four. Aggregating design and simulation, process development, fab telemetry, metrology and inspection, electrical test, packaging and assembly, and system-level performance shows total data projected to grow 400% or more by 2030. Optical interconnects and photonics add high-resolution measurement streams, further increasing the complexity of correlating test results with process and design variables.

These diverse datasets demand more than storage; they require cross-domain correlation and insight to guide yield, reliability, throughput, and enable quick and precise root cause analytics.

Preparing for the Data Surge: Practical Steps for Engineers

Unified Data Infrastructure — Consolidate heterogeneous datasets across design, fab, metrology, and test environments while normalizing formats and maintaining consistent identifiers across wafers, die, and modules.

Commonality Correlation — Link design simulations, fab telemetry, metrology and inspection data, electrical test results, and optical characterization through shared identifiers to enable correlation across process, design, and performance variables.

Scalable Analytics Workflows — Implement batch or streaming pipelines capable of processing terabyte-scale datasets using distributed frameworks while supporting statistical, spatial, and pattern-based analysis across diverse data formats.

Data Genealogy and Lineage Management — Maintain traceability across design revisions, wafer fabrication, assembly, packaging, and system-level testing to enable faster root-cause analysis and yield optimization.

Operational Insight — Deliver engineering dashboards and automated alerts through tools such as Power BI, enabling faster decision-making across design, manufacturing, and quality teams.

Conclusion

The wave of data approaching semiconductor manufacturing is immense and multifaceted. While per-wafer manufacturing data may double, combined lifecycle datasets, including chiplets, packaging, and optical I/O, are projected to increase fourfold or more by 2030. Preparing now, by building unified, scalable analytics capable of transforming raw data into insight, is essential. Only then can manufacturers harness the benefits of chiplets, advanced design, and photonics without being overwhelmed by the digital tsunami they generate.

Fortunately, tools already exist to help manufacturers harness and organize this rapidly expanding data landscape.

Join our upcoming webinar, Scaling Silicon Photonics and Co-Packaged Optics: A Practical Blueprint for Managing Manufacturing Data, where we will walk through practical approaches for building resilient data infrastructure and analytics workflows for next-generation semiconductor systems.

Also Read:

CEO Interview with Aftkhar Aslam of yieldWerx

Qnity and Silicon Catalyst Light a Path to Success at the Chiplet Summit

Intel Foundry: How They Got Here and Scenarios for Improvement

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Ravi Subramanian on Trends that are Shaping AI at Synopsys

Ravi Subramanian on Trends that are Shaping AI at Synopsys
by Daniel Nenni on 03-12-2026 at 8:00 am
Categories: EDA, Events, Synopsys

Ravi Interview Synopsys Converge

Right before the Synopsys Converge Keynote I caught an interview with Ravi Subramanian, Chief Product Management Officer at Synopsys, which highlights several important trends shaping the future of AI, semiconductor technology, and engineering. His discussion focuses on how the worlds of silicon design and system engineering are converging, driven largely by the rapid growth of AI and the need for more efficient computing infrastructure. The conversation provides insight into the technological, economic, and engineering challenges that will define the next decade of innovation.

Ravi and I are well acquainted. I worked for him at Berkeley DA advising him on foundry strategy and specifically how best to work with TSMC. I held a similar position with Solido Design and was hoping to merge the two companies. Mentor interceded and purchased both Berkley DA and Solido and the rest is as they say history. Interesting enough, the former CEO of Solido Amit Gupta now runs AI Strategy at Siemens EDA. Small world indeed. Two old friends are now competitors, I will comment on that in another article, you will not want to miss this one.

One of the first ideas Ravi discusses is the meaning of the event called “Converge.” This event represents the merging of two traditionally separate engineering communities: silicon engineers and systems engineers. Silicon engineers focus on designing semiconductor chips, while systems engineers design complete products such as cars, medical devices, and industrial machines. In the past, these fields operated somewhat independently. However, modern technologies, especially those powered by AI, require both disciplines to work closely together. For example, autonomous vehicles, robotics, and smart devices rely on specialized chips, complex software, sensors, and physical systems all working together. As a result, the boundaries between hardware and systems engineering are becoming less clear.

Another major theme of the interview is how performance in AI systems is measured. Traditionally, the industry focused on metrics like “tokens per second,” which measures how quickly an AI system can process information. However, Ravi explains that the industry is now paying more attention to efficiency-based metrics such as “tokens per dollar” and “tokens per watt.” These metrics evaluate how much useful AI computation can be performed relative to the cost and the amount of energy consumed. This shift is important because running large AI systems is extremely expensive and energy-intensive. For instance, Ravi mentions that an AI-assisted search query can require four to six times more energy than a traditional search query. As AI becomes more widely used, improving energy efficiency will become one of the most critical challenges in the technology industry.

Ravi also connects AI technology to global economic growth. He explains that the global economy currently produces about $117 trillion in annual output. Of this total, around $41 trillion comes from physical products that require engineering to design and manufacture, while about $60 trillion comes from services. Many economists believe that global GDP could double to around $250 trillion over the next 25 years. According to Ravi, much of this growth will be driven by productivity gains made possible by AI. However, these AI systems rely heavily on advanced semiconductors and computing infrastructure, meaning that the semiconductor industry will play a central role in enabling future economic expansion.

To understand how AI hardware will evolve, Ravi identifies four critical components that determine AI system performance: compute, interconnect, storage, and power. Compute refers to the processors, such as GPUs and specialized AI accelerators, that perform the calculations needed to train and run AI models. Interconnect refers to the technologies that move data between chips and computing nodes. Efficient data movement is crucial because transferring data often consumes more power than performing the computations themselves. Storage, particularly high-bandwidth memory, is another major challenge because modern AI models require enormous amounts of data to operate effectively. Ravi warns that shortages in memory supply could even disrupt certain industries if AI data centers consume most available memory resources. Finally, power consumption is a major constraint because large AI systems require vast amounts of electricity to operate.

The interview also highlights the possibility of significant changes in the semiconductor supply chain. Ravi suggests that the industry is entering the first decade of a major reconstruction as companies adapt their manufacturing processes, design methods, and infrastructure to support the growing AI economy. This transformation will affect everything from chip architecture to memory production and data center design.

Bottom line: Ravi emphasizes that future engineers will need broader knowledge across multiple disciplines. Systems engineers must understand semiconductor technology, while chip designers must understand real-world physics and system behavior. As AI continues to expand into robotics, autonomous systems, and other forms of “physical AI,” the integration of software, hardware, and physical systems will become increasingly important. The convergence of these fields will ultimately define the future of technological innovation.

Also Read:

Efficient Bump and TSV Planning for Multi-Die Chip Designs

Reducing Risk Early: Multi-Die Design Feasibility Exploration

Building the Interconnect Foundation: Bump and TSV Planning for Multi-Die Systems

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Axiomise Introduces nocProve to Transform NoC Design Verification

Axiomise Introduces nocProve to Transform NoC Design Verification
by Daniel Nenni on 03-12-2026 at 6:00 am
Categories: Axiomise, Semiconductor Services

Axiomise Launches nocProve for NoC Verification

Axiomise has recently launched a new verification tool called nocProve which will transform how Network-on-Chip designs are validated in modern hardware development, absolutely.

The tool is designed to be the first configurable formal verification application specifically created for NoC implementations. It addresses one of the most complex challenges faced by semiconductor engineers and promises to provide a more efficient and thorough approach to ensuring correctness in advanced chip designs.

A Network-on-Chip serves as the communication backbone of complex integrated circuits. These networks route information between processor cores, memory controllers, and specialized accelerators within a chip. NoCs are critical to achieving high bandwidth, low latency, and reliable operation. Every instruction or data transfer in high-performance computing tasks or artificial intelligence workloads relies on these networks functioning correctly. As new custom AI architectures and multi-core processors emerge, designers are creating bespoke NoC configurations to maximize performance and support novel protocols. These custom designs, however, introduce significant verification challenges due to their complexity, multiple clock domains, virtual channels, and advanced routing schemes. Errors such as deadlocks or livelocks can occur in rare circumstances that traditional simulation techniques may not detect.

Formal verification is a method that mathematically proves a design meets its specification under all possible conditions. It is considered the gold standard for ensuring reliability in critical systems. Despite its advantages, formal verification has historically been difficult for NoCs due to the large number of possible states and the nondeterministic behavior of complex designs. Axiomise built nocProve as a configurable application within its existing platform using the company’s proprietary proof engine. This engine is optimized to handle the challenges of formal verification for large, nondeterministic systems. It allows engineers to prove the correctness of their designs exhaustively while reducing the computational burden that often prevents formal methods from completing successfully.

The tool can be adapted to a wide variety of bus protocols, channel types, and routing policies. Engineers submit their designs, usually in hardware description languages such as Verilog or VHDL, along with assertion specifications written in SystemVerilog Assertions. nocProve automatically generates formal proofs to verify that the design conforms to the specifications. This approach allows engineers to catch subtle bugs and corner-case errors that could otherwise go unnoticed until after production. By automating these tasks, nocProve also saves time and reduces the need for labor-intensive manual verification efforts.

The launch of nocProve is significant because traditional verification techniques such as simulation or constrained random testing can only examine a finite set of scenarios. These methods may miss rare but critical faults that could cause functional errors or degrade performance. Formal verification using nocProve provides exhaustive confidence that the design is correct, which is particularly important for high-stakes applications in artificial intelligence accelerators, data centers, and high-performance computing chips. Early detection of potential faults reduces the risk of expensive post-production fixes and silicon respins that can delay product launches.

Axiomise has demonstrated nocProve on real-world NoC designs. The tool was able to verify complex open-source designs with high throughput and multiple simultaneous transactions within a few hours. This speed and reliability showcase the potential for nocProve to be integrated into modern chip development workflows and provide meaningful results early in the verification process. The automation of formal proofs allows design teams to innovate more quickly and with greater confidence, ensuring correctness without sacrificing development time.

Bottom line: nocProve represents a major advance in the formal verification of Network-on-Chip architectures. By automating exhaustive proof generation and efficiently handling complex designs, it addresses one of the semiconductor industry’s most pressing verification challenges. As chips become more customized and performance demands continue to grow, tools like nocProve will be essential for ensuring reliability while accelerating development and reducing the risk of costly errors. Axiomise’s new tool promises to give engineers the confidence to build advanced systems without compromising on correctness or speed.

CONTACT AXIOMISE

Also Read:

Akeana Partners with Axiomise for Formal Verification of Its Super-Scalar RISC-V Cores

IP Surgery and the Redundant Logic Problem

Podcast EP274: How Axiomise Makes Formal Predictable and Normal with Dr. Ashish Darbari

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Qnity and Silicon Catalyst Light a Path to Success at the Chiplet Summit

Qnity and Silicon Catalyst Light a Path to Success at the Chiplet Summit
by Mike Gianfagna on 03-11-2026 at 10:00 am
Categories: 3D IC, Chiplet, Events, Semiconductor Services, Silicon Catalyst

Qnity and Silicon Catalyst Light a Path to Success at the Chiplet Summit

The Chiplet Summit recently concluded. Multi-die heterogeneous design is a hot topic these days and chiplets are a key enabler for this trend. The conference was noticeably larger this year. There were many presentations and exhibits that focused on areas such as how to design chiplets, what standards are important, how to integrate chiplets and what applications show the most promise. All important, exciting and useful topics. There was one session hosted by Silicon Catalyst that stood out for me as different.

Silicon Catalyst is a different kind of organization. One that doesn’t make chips (or chiplets), develop standards or build software design tools. Instead, it has developed a unique, worldwide incubator to bring semiconductor startups from PowerPoint to product. The organization did showcase a number of promising new companies at the show. More on that later. What I want to focus on first is Qnity, a strategic partner of Silicon Catalyst that has substantial size with more than 10,000 employees serving customers in more than 80 countries. This organization is also the last pure-play electronics supplier in the U.S.

The breadth and depth of Qnity create a powerful force for the semiconductor supply chain. Let’s examine how Qnity and Silicon Catalyst light a path to success at the Chiplet Summit

The Silicon Catalyst Footprint

You can learn a lot about Silicon Catalyst and what the organization does on SemiWiki here. Nick Kepler, COO of Silicon Catalyst gave an excellent keynote at the Chiplet Summit that provided some good context as to what the organization does for chiplets and why it’s unique.  Nick explained that Silicon Catalyst is the only accelerator focused on the global semiconductor industry including chips, chiplets, materials, IP and silicon fabrication. Applications include photonics, MEMS, sensors, life science and quantum.

He went on to describe the extensive, worldwide ecosystem that the organization has built. Many organizations have a logo slide. The one from Silicon Catalyst is quite impressive. It is included below.

Silicon Catalyst ecosystem

Qnity and its Unique Impact on the Semiconductor Supply Chain

Chris Gilmore

Chris Gilmore, Advanced Packaging Technology Strategy Leader for Qnity, presented at the Silicon Catalyst session. (The company name is pronounced “Quenity”.) The company was formed when DuPont spun out its electronics business last year, creating a publicly traded (NYSE: “Q”), worldwide force in advanced electronics materials and solutions empowering AI, high performance computing, and advanced connectivity.

Qnity has 39 manufacturing sites and 17 R&D facilities around the world. The majority of its portfolio is tied directly to semiconductors, giving the company a total addressable market exceeding $30 billion. Qnity gains more than 40% of its revenue in interconnect technologies, including metallization chemistry and laminates, alongside thermal materials through subsidiary Laird Performance Materials.  This vast size and technology base is what unlocks the opportunity for a substantial impact on the chiplet market. More on that in a moment.

With a Ph.D. in synthetic organic chemistry and well over a decade of experience in advanced packaging and materials research at Dow Chemical and DuPont, Chris brought substantial knowledge of the current semiconductor supply chain challenges.

He explained that Qnity has two primary areas of focus. In semiconductor technologies, it provides consumable materials and solutions for semiconductor chip fabrication, fab equipment, and advanced display panels. In interconnect solutions, it provides advanced materials, systems and engineering solutions for signal integrity, power management and thermal management to address interconnect challenges. This totals about a $4.75B business for the company. The figure below provides a view of the company’s product mix.

It turns out this broad technology base provides Qnity with a unique perspective to advance chiplet designs. Chris explained that chiplets are a simple concept with a complex execution path. One of the primary drivers of this complexity is the fact that chiplets invert typical supply chain dynamics. He explained that the traditional semiconductor supply chain is characterized by low mix/high volume requirements. Due to the many specialized solutions offered by chiplets, the new chiplet supply chain requires a high mix/low volume dynamic.

He explained that chiplet-based design winners will be chosen by performance against high value challenges in many diverse targeted fields of use. The figure below illustrates the wide impact Qnity has on the entire semiconductor value chain. This is unique to Qnity and is the source of its substantial impact on the chiplet market.

Qnity technology portfolio

Thanks to the incredible breadth of Qnity’s offerings, the company is uniquely positioned to rebalance the semiconductor ecosystem to manage the demands of the new chiplet-based breed of design. Chris described a focus of interdisciplinary investment and innovation to help bring chiplets to fruition with broad and deep collaboration across the supply chain.

If you are contemplating a high-volume chiplet application, Qnity is a company to be aware of, and probably one to work with. You can explore the company’s website here.

To Learn More

Silicon Catalyst has put together a video summary of the Qnity presentation at the Chiplet Summit. You can view it at on the Silicon Catalyst website here. There were many other significant events that were part of the Silicon Catalyst session. Other Silicon Catalyst portfolio companies that presented include:

Athos Silicon delivers safe AI for the physical world with a product called Chiptile, the Athos-designed foundational compute chiplet, and the building block of its Multiple Systems on Chip (mSoC) architecture for safety-critical autonomy across robotics, automotive, and aerospace.

CrossFire Technologies tackles Interconnect challenges with an approach called Wire Abundance. No silicon interposer is required, and the product works with current chiplets, SoCs and memory die, delivering a 10X smaller area.

HEPT Lab provides 3D sensors for harsh environments. The HEPT Lab sensor is based on silicon photonics technology that was developed at CalTech for over 10 years. The goal is to make silicon photonics sensors as ubiquitous as cameras.

Quadric delivers a new approach to scalable AI at the edge with a fully programmable stand-alone processor. The architecture is not an accelerator, but rather a processor that is programmable in C++ and Python.

The Silicon Catalyst session ended with a spirited panel discussion. The participants are shown below. You can see a recording of this panel on on the Silicon Catalyst website here.

And that’s how Qnity and Silicon Catalyst light a path to success at the Chiplet Summit.

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Intel Foundry: How They Got Here and Scenarios for Improvement

Intel Foundry: How They Got Here and Scenarios for Improvement
by Mark Webb on 03-11-2026 at 8:00 am
Categories: Foundries, Intel Foundry, MKW Ventures Consulting, Semiconductor Services
1 Comment

Intel Foundry How They Got Here and Scenarios for Improvement

How do you get a shortage while not growing???

Intel Announced earnings in January. Then David Zinsner presented updates on business this week. David is open when talking and always shares 2-3 things he probably should not share. Often he shares things some of us know, but we cannot present because it is not public. Then he makes it public, Thank you David! Our model for what is happening:

Intel Shortage

Intel is unable to meet demand for processors in Q1 and Q2 2026. Their manufacturing is the constraint. The shortage is not TSMC as Intel specifically mentioned moving wafer starts from CCG to DCAI (TSMC is not used for most DC CPUs). The shortage is not 18A. 18A is not running at full capacity in Fab 52, 18A is not in highest demand (Panther lake is a good CPU but it is expensive). Intel 3 is not what is short. It is still ramping and demand has not increased like expected. What is short is Intel 7/10. Raptor lake/Refresh and older on Client. Sapphire/Emerald Rapids on DC.

These are short despite declining sales and despite Intel losing market share in both Client and Datacenter. Less volume than before and yet somehow it is short.

How did this happen?

Intel had a plan. Develop Intel 3 and Intel 18A. Put products on those nodes and ramp them as fast as possible. Products on both were delayed some but there are two main issues that caused the blowback to older nodes. One: the new products are more expensive and there are limits to the number of customers who want to pay that higher price. Granite Rapids and Sierra Forrest are examples and Panther lake is a new example. Good products but customers like sticking with reorders of older products at a lower price OR are looking at AMD products instead. Two: Both technologies have cost/yield/capex expenses that made it so that it is not financially great to ramp them until they are more mature. Yields, output per tool, wafer cost have slowed the ramp below what was expected in 2024.

The plan a couple years ago was to remove Intel 7 capacity (the node is five years old) and add Intel 3 and 18A. Apparently, they did remove Intel 7 capacity assuming people would jump to new products. Historically, this has always been a problem and Intel was able to deal with it. Tell customers they have to move, Tell them the price of the old product is going up, Tell them they can only have the new product. But Intel is not a monopoly now. People are already leaving Intel for AMD and ARM. Intel cannot force people. Intel customers want Sapphire rapids and Raptor lake. Less expensive, mature and they do what we need. If Intel wont sell it to us, we can look elsewhere. Since Intel is already losing share, this is not good and Intel is not pushing

Result: Intel sales are down, Market share is down, people want the older nodes, Intel cannot force them to new nodes. Intel 7 ships way more wafers than Intel 3 and 18A combined. But Intel doesn’t have enough Intel 7 capacity.

Zinsner alluded to some of these items. The Key points are 18A margins are currently negative, Intel 3 needs to get mature, 18A needs to get mature, and they need people to move to new nodes when they can be ramped cost effectively. Until then they need to add capacity to Intel 7.

Scenarios for Future

Due to DRAM shortages and high prices, The future is murky. We expect 10% less PC sales in 2026. We expect PC OEMS to prioritize lower DRAM PCs. Lunar Lake has no discrete DRAM, many people expect it to sell well. Server CPU units will increase but AMD will take some of that share. The key is to get newer products cost effective, then ramp those fabs, then push customers to those parts using pricing.

Intel is/was planning new CPUs in 2026. Arrow lake refresh. Clearwater forest. Diamond rapids. But the most important part in our opinion is Wildcat Lake. This is a cost reduced Panther lake and our cost model shows it can be a solid replacement for Raptor lake at a competitive price and still make money (Panther lake is in a different market with limited volume). But the key is to get Intel 3 and 18A cost effective so they can push customers to the newest products at a competitive price.

When does all this get better? We expect 18A/Panther lake to get more mature by Jan 2027. It will not be cost effective til then…. And yields are not the only problem. It will then get close to filling Fab 52. We know 90%+ of Nova lake CPUs are on TSMC N2 so that needs to play out as well. Intel 3 will continue to ramp but datacenter products are very slow to ramp so it is not clear when this gets fixed.

In 2028, Intel should have its newest fabs ramped and mature and hopefully CPUs have been pushed to these new nodes. We are not expecting IFS to break even in 2027 without a huge one time writeoff, although Zinsner said it was possible, the numbers don’t seem to add up. After Jan 2028, the goal is to continue to ramp 18A and eventually 14A, convert all product to those nodes and start manufacturing external customer volume. If this happens, IFS could break even by 2030. We can go through the gory details on why this will or wont happen and how to update the projections.

Based on all of this, Intel is revisiting its roadmap. Do they really want a new CPU on Client and Datacenter every year? Should they ramp TSMC parts more? We shall see

We have spreadsheet and models to explain all this and how to see if Intel can change the end of the story.

Mark Webb

www.mkwventures.com

Also Read:

Things From Intel 10K That Make You Go …. Hmmmm

The Next Hurdle AI Systems Must Clear

Why Your LLM-Generated Testbench Compiles But Doesn’t Verify: The Verification Gap Problem

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The Next Hurdle AI Systems Must Clear

The Next Hurdle AI Systems Must Clear
by Bernard Murphy on 03-11-2026 at 6:00 am
Categories: AI, Arteris, Automotive, IP

datacenter surrounded by power plants

AI isn’t having an easy ride. The media and Wall Street swing wildly between extremes on any hint of a shift in AI sentiment. Dickens saw this coming: “It was the best of times, it was the worst of times, it was the age of wisdom, it was the age of foolishness, it was the epoch of belief, it was the epoch of incredulity, it was the season of light, it was the season of darkness, it was the spring of hope, it was the winter of despair”. Beneath these headlines lurks an important problem for AI inference scaling: a widening gap between theoretical peak performance and what system providers can guarantee. This gap proves to have significant implications for power demand and safety.

What is this gap?

Large semiconductor systems make heavy use of pre-designed subsystems, developed in-house for earlier generation products or sourced externally. This is particularly true for the chiplet-based designs now common in datacenters, also in our cars. Best-in-class chiplets are available from industry experts: CPU server subsystems, AI accelerator subsystems, and high-bandwidth memory (HBM) subsystems, while other chiplets are fashioned by the semiconductor system prime. Connections between chiplets are managed through industry-standard UCIe interfaces.

A system built on these components, each independently rated for high performance, connecting through industry-standard interfaces. Why wouldn’t this deliver near to optimum throughput?  Simple economics dictates that a big expensive semiconductor product must handle multiple inference tasks simultaneously. Individually these chiplets have been designed to do just that, but none of these has responsibility to manage traffic performance between chiplets. UCIe is designed to provide basic connectivity, not system-level traffic management. That management is the responsibility of the network subsystem between these chiplets, a system layer not unlike the internet but optimized for in-chip/in-package performance.

Multi-tenant inference platforms face unique traffic challenges. Traffic is managed through a common network for cost and power efficiency, as in any modern electronic system. However, AI traffic between CPU control, HBM and an AI accelerator is very lumpy, some bursty yet requiring high bandwidth, some very sensitive to latency, and some critical to maintaining forward progress, especially control data (valid, ready, credits, etc).

Lumpy traffic hogs bus bandwidth, not indefinitely but until a transaction is completed. The massively parallel nature of AI processing creates a second problem. A step can’t start until all the data needed for that step has arrived. Until then, the step must stall. When multiple inferences are running at the same time it is not difficult to imagine frequent stalls, inferences sitting idle waiting for complete data before they can move onto the next step.

So far this may not sound too surprising: increasing traffic leads to lower per-inference performance. The shocker is that performance does not degrade gracefully. As traffic contention rises between inferences, just as in rush hour traffic, stalls build up. At some point, performance drops off a cliff. Net utilization of the system plummets from 80% to 45%.

Why not just increase bandwidth in the network? Unfortunately, that alone isn’t enough. Between lumpy traffic and synchronization stalls, the control information critical to manage fairness between inferences is progressively squeezed out and fairness between inferences collapses. Effective multi-tenant management needs more than just increased bandwidth. It needs to provide predictability.

Fixing the gap

High performance AI accelerators, CPU subsystems, HBM, and UCIe interfaces are absolutely necessary for a chiplet-based AI product, but they are not sufficient. The product must also build on a traffic management network able to serve the unique challenges of multi-tenant AI inferencing, requirements well beyond the scope of best-effort networks. Interconnect design must be re-conceived to deliver predictability for these workloads.

Andy Nightingale (VP Product Management and Marketing at Arteris) shared some must-haves to ensure predictability. The network must support isolation between traffic streams from different tenants so that one inference can’t block another. Increasing load will naturally degrade throughput but it should do so gracefully. Coherency guarantees must be maintained, even under load, and behavior must be deterministic under load so that service level agreements can be guaranteed. A network designer can then craft a network fabric to meet their target use-case needs, building on a network IP that can support those guarantees.

Giant datacenters can’t define pricing models against unpredictable performance. Without an inter-chiplet network architecture designed for the task, the only way to guarantee a service level agreement is to add more servers and more power stations. Clearly, the better solution is to use AI systems with network architectures designed to the task, to deliver dependable utilization from servers and power stations already budgeted.

I mentioned safety at the outset of this article. Chiplet-based design is now very popular in automotive systems for a host of reasons. Predictable power is certainly a concern in that domain, but even more important is predictability for safety. In cars, trucks and other vehicles, predictable response is not a performance preference. It is a certification requirement. The same network traffic considerations apply.

You can learn more about Arteris HERE.

 

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Why Your LLM-Generated Testbench Compiles But Doesn’t Verify: The Verification Gap Problem

Why Your LLM-Generated Testbench Compiles But Doesn’t Verify: The Verification Gap Problem
by Admin on 03-10-2026 at 10:00 am
Categories: Chiplet
2 Comments

fig1 vg chart

By Vikash Kumar, Senior Verification Architect | Arm | IEEE Senior Member. 

The Problem Every Verification Engineer Recognizes

You ask an LLM to generate a UVM testbench. It produces 25 files. Everything compiles. You run the simulation — and nothing happens. The scoreboard reports zero checks. The slave driver stops after 10 transactions. The simulation hangs.

This is not a hypothetical. In a controlled experiment generating a UVM testbench for an AHB2APB bridge using a state-of-the-art commercial LLM, this is exactly what happened — after an automated agentic repair loop had already resolved 37 compile errors across 4 iterations.

The core problem: compile success is nearly uncorrelated with functional correctness at the protocol level. Yet compile success is the dominant evaluation metric in LLM-for-hardware research. This article explains why that is the wrong metric, what the right metrics are, and what it means for verification teams trying to use LLMs in production.

What Compile Success Actually Tells You

A compiler verifies type consistency, scope resolution, and syntactic validity. It does not verify protocol timing, handshake sequencing, interface role semantics, or transaction counting.

Here are three failures from the AHB2APB case study — each catastrophic to verification, none producing a compiler error:

Role confusion: The LLM generated an APB slave driver that drives PADDR, PSEL, and PENABLE — the master’s outputs. An APB slave only drives PRDATA, PREADY, and PSLVERR. The simulation ran without complaint. The slave simply never responded.

Timing phase error: The AHB driver presented HWDATA in the same clock cycle as HADDR. AHB requires a one-cycle offset — HWDATA is valid in the cycle after HADDR. The testbench drove the wrong data on every single transaction.

Response deadlock: The master sequence called get_response() waiting for the driver to call put_response(). The driver never called it. The simulation hung silently at transaction 1.

A controlled taxonomy of eight failure modes from the case study breaks down as follows: one was detectable at compile time (L2: hallucinated sequence item field names), one surfaced at elaboration during VIF port resolution (L1), and six required simulation or waveform analysis to diagnose (L3–L8). The compiler caught one of eight.

Figure 1: Eight LLM failure modes by detection method — 1 at compile time, 1 at elaboration, 6 at simulation.

Three Metrics That Actually Measure the Gap

Repair Efficiency Score (RES)

RES = total compile errors / total repair calls. In the case study, 37 errors resolved in 15 calls gives RES = 2.47. A single repair call that fixed hallucinated sequence item field names collapsed 18 downstream errors simultaneously — demonstrating that errors cluster around shared root causes when an LLM misunderstands a core abstraction.

Verification Gap (VG)

VG is the fraction of functional failures that survive a compile-clean testbench. VG = 0.00 means the testbench is both compile-clean and functionally complete. VG = 0.80 after the automated repair loop means 80% of functional failures remained after full automation — invisible to the compiler throughout. This is the metric the field is not computing.

Specification Coverage Ratio (SCR)

SCR measures what fraction of the protocol specification the testbench actually exercises. A testbench covering only happy-path transactions — missing burst-interrupt termination, error-retry, and maximum-wait-state scenarios — can have SCR well below 1.0 while passing all simulation checks on normal traffic.

Figure 2: VG and SCR progression across configurations. Human expertise closes the gap that automation cannot.

The Fix Is a Better Specification, Not a Bigger Model

The most counterintuitive finding from this study: the highest-leverage investment to improve LLM-based verification automation is not a more capable model. It is a more formal specification schema.

Timing phase failures exist because specifications encode timing in natural language: ‘HWDATA is valid one cycle after HADDR.’ No amount of model scale resolves the ambiguity between that prose and the precise simulator semantics of @(posedge HCLK) sequencing.

A manifest field encoding HWDATA_phase_offset: 1 gives the generation agent an unambiguous directive — the failure becomes preventable rather than debuggable. Role confusion failures become preventable if the manifest classifies interface roles explicitly: apb_slave: {role: reactor, perpetual: true}. In both cases, the fix is upstream specification formalization, not downstream repair.

Eight of approximately 25 generated files required complete expert rewrites to achieve functional correctness. Every one of those rewrites addressed a failure the compiler never flagged.

The Real Bug the Testbench Found

After achieving functional correctness through expert collaboration, 30 randomized AHB transactions detected a previously unknown RTL race condition in the bridge’s xfer_pending clearing logic.

The bridge uses a registered clear that activates one clock cycle too late. The FSM reads stale xfer_pending = 1 and re-enters APB_SETUP, generating a phantom APB transfer with the previous transaction’s latched address. The scoreboard detected 6 PSEL assertions for 5 AHB transfers — a 1:1 AHB-to-APB ratio violation invisible to IP-level simulation.

This is precisely the class of integration bug that protocol-level testbench modeling exists to find — and it is why getting the testbench right matters. A compile-clean testbench with VG = 0.80 would never have run the checks that found it.

What This Means for Your Verification Flow

If you are evaluating LLM-based testbench generation tools, ask the vendor: what is your Verification Gap on a real protocol design? Compile success is not evidence of a working testbench. RES, VG, and SCR are.

If you are integrating LLMs into your verification flow, the eight-failure taxonomy gives you a concrete checklist. Check for role confusion in every driver. Check for timing phase errors at every AHB and APB interface. Check for liveness failures in every sequence that is supposed to run indefinitely. Check the elaboration log — not just the compile log.

If you are writing the specification that feeds the LLM, encode timing constraints, interface roles, and behavioral contracts as structured fields — not prose. The gap between compiles and verifies is the gap that matters. Start measuring it.

About the Author

The author is a Senior Verification Architect at Arm and an IEEE Senior Member, with 15+ years of experience in hardware verification including prior work at Intel. Specializes in subsystem-level verification for chiplet-based designs and protocol verification (AHB, AXI, CHI, PCIe, UCIe). Active in IEEE standards and peer review activities.

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Advanced Architectures for Hybrid III-V/Silicon Quantum Cascade Lasers

Advanced Architectures for Hybrid III-V/Silicon Quantum Cascade Lasers
by Daniel Nenni on 03-10-2026 at 8:00 am
Categories: Foundries

CAE INL 2025

Mid-infrared (MIR) photonic integrated circuits are emerging as a key technology for applications ranging from environmental monitoring and medical diagnostics to defense and industrial process control. The MIR spectral region, often referred to as the molecular “fingerprint” region, exhibits strong absorption features for a wide variety of gases and chemical species. This property enables highly sensitive and selective sensing, provided that compact, efficient, and wavelength-stable laser sources can be integrated with photonic platforms. Among the available MIR sources, quantum cascade lasers (QCLs) stand out due to their broad wavelength coverage, high output power, and room-temperature operation. However, their integration on silicon remains a major technological challenge.

Quantum cascade lasers are unipolar semiconductor devices based on intersubband transitions in III-V heterostructures. Since their first demonstration in 1994, QCLs have undergone continuous improvements, achieving continuous-wave operation at room temperature and wall-plug efficiencies exceeding 20%. Despite these advances, most QCLs are still realized as discrete devices, limiting their scalability and integration with complex photonic systems. Silicon photonics, on the other hand, offers mature fabrication processes, high reproducibility, and large-scale integration capabilities, but silicon itself cannot provide optical gain in the MIR. Hybrid integration of III-V QCL gain regions onto silicon photonic platforms therefore represents a promising route toward compact and functional MIR photonic integrated circuits.

In this work, a high-index-contrast photonic integrated circuit platform is developed to enable the integration of III-V QCLs on silicon waveguides. The proposed architecture relies on molecular bonding of III-V epitaxial layers onto a silicon-on-insulator–based platform, including variants such as SONOI to extend MIR transparency. The platform combines several key functionalities: strong optical confinement for miniaturization, efficient and robust adiabatic coupling between the III-V gain region and silicon waveguides, and high-quality silicon-based distributed feedback structures for wavelength control. This approach enables the realization of distributed feedback (DFB) and distributed Bragg reflector (DBR) QCL architectures directly integrated with silicon photonic circuits.

Efficient optical coupling from the III-V active region into silicon waveguides is achieved using adiabatic tapers. Numerical studies show coupling efficiencies exceeding 95% over a wide range of taper lengths and geometrical parameters, demonstrating robustness against fabrication tolerances. This is a crucial requirement for wafer-scale fabrication and reproducible device performance. The silicon waveguides can further incorporate gratings or couplers for feedback, out-coupling, and on-chip routing toward sensing elements.

The fabrication process is fully compatible with 200-mm silicon wafers and includes silicon waveguide definition, dielectric deposition, III-V/Si molecular bonding, substrate removal, ridge and mesa etching, and metal contact formation. A usable surface ratio above 90% after III-V substrate removal highlights the maturity of the bonding approach. Laser characterization is performed at the wafer level using pulsed electrical injection, Peltier cooling, and automated probing, with optical output collected via grating couplers and analyzed using FTIR spectroscopy.

Experimental results demonstrate laser emission from hybrid DFB QCLs operating around 4.3 µm, a wavelength of particular interest for CO₂ detection. Clear lasing behavior is observed, with a threshold current of approximately 700 mA and a slope efficiency on the order of 0.22 mW/A under pulsed operation. Single-mode emission is achieved in the linear regime, while multimode behavior appears near rollover, mainly due to thermal limitations. These results confirm efficient light transfer from the III-V gain region into the silicon waveguide and validate the distributed feedback approach implemented in silicon.

Beyond DFB and DBR lasers, the platform also enables advanced diffractive and refractive architectures, such as photonic crystal surface-emitting lasers and micro-ring resonator-based QCLs. These concepts offer further reductions in footprint and threshold current, opening the way toward densely integrated MIR photonic systems. Overall, this work demonstrates a versatile and scalable hybrid III-V/silicon platform for quantum cascade lasers, representing a significant step toward fully integrated mid-infrared photonic circuits for sensing and beyond.

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Efficient Bump and TSV Planning for Multi-Die Chip Designs

Efficient Bump and TSV Planning for Multi-Die Chip Designs
by Daniel Nenni on 03-10-2026 at 6:00 am
Categories: 3D IC, EDA, Synopsys

Efficient Bump and TSV Planning for Multi Die Chip Designs

The semiconductor industry has experienced rapid advancements in recent years, particularly with the increasing demand for high-performance computing, artificial intelligence, and advanced automotive systems. Traditional single-die chip designs are often unable to meet modern PPA requirements. As a result, engineers have turned to multi-die architectures, where multiple smaller dies are integrated within a single package. While this approach improves scalability and performance, it also introduces new challenges, especially in interconnect planning. One of the most critical aspects of multi-die integration is the efficient planning of bumps and TSVs that enable communication between different dies.

In multi-die designs, interconnectivity between chips is achieved through microbumps or hybrid bonding pads placed on the surfaces of dies. These bumps act as electrical connection points between dies, interposers, or substrates. Modern designs may require hundreds of thousands or even millions of such connections. As the number of dies and interconnects increases, the complexity of planning and managing these connections also rises dramatically. According to the provided white paper, improper bump planning can negatively affect routability, routing quality, and overall design efficiency.

Traditionally, bump planning was done manually using simple graphical tools such as spreadsheets or diagram software. While this approach worked for earlier single-die flip-chip designs that contained only a few thousand connections, it is no longer practical for today’s large-scale multi-die systems. Manual planning is time-consuming and highly prone to human error. Furthermore, any modification to the bump layout of one die often requires corresponding changes in other dies or the package design. If these updates are not properly synchronized, significant design errors may occur later in the development cycle.

To address these challenges, modern EDA tools provide automated bump planning capabilities. These tools allow designers to define bump regions, which are rectangular or irregular areas on a die where bumps are placed. Within each region, bumps can follow specific patterns based on constraints such as pitch, spacing, and alignment. Once these patterns are defined, the software can automatically generate thousands of bumps quickly and accurately. If the region size or design constraints change, the bump layout automatically updates, saving designers significant time and effort.

Another key aspect of bump planning is signal assignment. Each bump must be connected to a specific signal, power line, or ground network. Designers may assign signals manually or use automated algorithms that optimize placement based on factors such as wire length and routing efficiency. Automatic signal assignment can analyze the entire multi-die system and determine the best possible mapping of signals to bumps, improving overall performance and reducing design complexity.

In addition to bump planning, designers must carefully plan through-silicon vias. TSVs are vertical electrical connections that pass through a silicon die, allowing signals and power to travel from the backside of the die to the frontside routing layers. TSVs are particularly important in 3D stacked chip designs where multiple dies are stacked vertically. However, TSVs are relatively large structures and require significant spacing and keep-out zones to avoid damaging nearby circuitry. Poor TSV placement can reduce the usable area for logic cells and negatively affect timing performance. Therefore, careful planning is necessary to ensure optimal TSV placement without compromising chip functionality.

Modern design platforms integrate bump and TSV planning into a unified workflow. This allows engineers to visualize connections in both two-dimensional and three-dimensional views, track engineering changes, and perform automated design rule checks. By detecting alignment errors, missing connections, or signal mismatches early in the design process, these tools help prevent costly mistakes during later stages of manufacturing.

Bottom line: Efficient bump and TSV planning plays a crucial role in the success of multi-die semiconductor designs. As chip architectures become more complex, manual planning methods are no longer sufficient. Automated design tools and structured planning methodologies enable engineers to manage millions of connections, maintain design accuracy, and accelerate time-to-market. With the continued growth of advanced technologies such as AI and high-performance computing, effective interconnect planning will remain a fundamental requirement in modern semiconductor design.

White Paper Registration

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The Evolution of RISC-V and the Role of Andes Technology in Building a Global Ecosystem

The Evolution of RISC-V and the Role of Andes Technology in Building a Global Ecosystem
by Daniel Nenni on 03-09-2026 at 10:00 am
Categories: Andes Technology, Events, IP

RISC V Now Andes Conference

During my frequent trips to Taiwan as a foundry relationship professional I remember meeting Frankwell Lin, CEO of Andes, in Taiwan 15+ years ago. As I walked to TSMC HQ from the Hotel Royal (my second home for many years) Andes was about mid point and Frankwell’s door was always open. Sometimes just tea, sometimes technology, there was always a reason to talk to Frankwell.

Throughout my career I have always been excited about open standards as a platform to accelerate design starts. The semiconductor industry is all about design starts, right? Having been involved with many different open standard initiatives, some they succeeded but failure was quite common. RISC-V however has been a resounding success and I am honored to be a part of it, absolutely.

The evolution of RISC-V, the rise of Andes Technology, and the emergence of the RISC-V Now! Conference illustrate how open hardware architectures are transforming the semiconductor industry. Together, they represent a shift toward open standards, collaborative ecosystems, and new approaches to building processors for modern computing workloads.

The story begins with the development of RISC-V, an open instruction set architecture (ISA) derived from the principles of RISC. Earlier RISC architectures emerged in the 1980s as a simpler and more efficient alternative to complex instruction set computing. While architectures like ARM became highly successful, they remained proprietary. RISC-V, created in 2011 at the University of California, Berkeley, introduced a new concept: an ISA that is open and free for anyone to implement, modify, and extend. This openness allows companies and researchers to build custom processors without paying licensing fees, accelerating innovation across industries.

Over the past decade, the architecture has rapidly grown from an academic project into a major industry platform used in microcontrollers, embedded systems, AI accelerators, and even data-center research. Analysts estimate the architecture is on track to power tens of billions of chips worldwide and has reached significant market penetration across multiple computing sectors.

A key contributor to this ecosystem is Andes Technology, a Taiwanese semiconductor company specializing in RISC-V processor IP. As a founding premier member of the global RISC-V community, Andes has played a central role in commercializing the open ISA. The company designs 32-bit and 64-bit processor cores that can be integrated into SoC designs for applications ranging from consumer electronics to automotive systems and AI computing. Its processor portfolio includes high-efficiency embedded cores and high-performance multiprocessor clusters, many of which support advanced features such as vector processing, digital signal processing, and customizable instruction extensions. These capabilities allow hardware designers to tailor processors to specific workloads, which is one of the most attractive features of the RISC-V model. Over time, Andes-powered processors have been integrated into billions of chips used around the world.

As RISC-V adoption grew, Andes also began investing in community-building events to accelerate collaboration across the ecosystem. One example is the Andes RISC-V CON, a series of conferences designed to bring together engineers, researchers, and technology companies working on RISC-V platforms. These events typically include keynote speeches from industry leaders, technical sessions on processor design, and discussions on emerging applications such as artificial intelligence, automotive electronics, and communications systems. Conferences often feature multiple tracks, including developer sessions where engineers can learn about debugging tools, vector extensions, and custom instruction development. By providing a space for collaboration and knowledge sharing, these events have helped strengthen the RISC-V ecosystem and encourage wider adoption of the architecture.

Building on the success of these earlier events, Andes launched the RISC-V Now! conference series in 2026. Unlike earlier conferences that focused primarily on the technology and ecosystem of the architecture, RISC-V Now! emphasizes real-world deployment and commercial implementation. The conference brings together system architects, semiconductor executives, and engineers who are already building and shipping products based on RISC-V processors. Topics typically include system-level design trade-offs, strategies for integrating CPUs into complex SoCs, software enablement challenges, and lessons learned from production deployments. The first events in the series were scheduled in several global technology hubs—including Silicon Valley, Hsinchu, Shanghai, and Beijing highlighting the global nature of the RISC-V movement.

The emergence of RISC-V Now! reflects a broader transition within the RISC-V ecosystem. Early adoption focused heavily on experimentation and research, but the current phase is centered on building commercial products and scalable computing platforms. As computing workloads grow more complex—especially in fields like artificial intelligence, automotive autonomy, and edge computing—companies are seeking processor architectures that offer flexibility, efficiency, and control. RISC-V provides these advantages by allowing designers to customize instructions, optimize for power or performance, and maintain full control over their hardware roadmap.

Bottom line: The evolution of RISC-V represents one of the most significant shifts in modern processor architecture. Andes Technology has played an important role in advancing this open hardware movement by providing commercial CPU IP and fostering community collaboration through conferences and ecosystem initiatives. The launch of the RISC-V Now! conference marks the next stage of this journey, focusing on real-world deployment and production systems. Together, these developments highlight how open architectures and collaborative innovation are reshaping the future of computing.

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