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PDF Solutions and the Value of Fearless Creativity

PDF Solutions and the Value of Fearless Creativity
by Mike Gianfagna on 08-18-2025 at 6:00 am

PDF Solutions and the Value of Fearless Creativity

PDF Solutions has been around for over 30 years. The company began with a focus on chip manufacturing and yield. Since the beginning, PDF Solutions anticipated many shifts in the semiconductor industry and has expanded its impact with enhanced data analytics and AI. Today, the company’s impact is felt from design to manufacturing, to the entire product lifecycle across the semiconductor supply chain as shown in the graphic above.

I did a bit of digging to understand the history and impact of this unique company. Along the way, I found a short but informative video (a link is coming). One of the speakers is a high-profile individual that talked about PDF Solutions and the value of fearless creativity. That quote did a great job to set the tone for what follows.

A Memorable Conversation

Dr. Christophe Begue

To begin my quest, I was able to spend some time talking with Christophe Begue, VP of corporate strategic marketing at PDF. Besides PDF, Dr. Begue has a long history of technology and business development at companies such as Oracle, IBM, and Philips Electronics. As Christophe began describing some of the innovations at PDF, he discussed the key role that the PDF data platform plays in the industry. In the cloud, PDF manages over 2.5PB of data, the equivalent of 3 million hours of video. Many customers deploy the PDF database on site which allows them to centrally manage all their massive manufacturing data.

He went on to explain that PDF has always been focused on anticipating the next challenge the semiconductor industry will face to be ahead of the problem. Current challenges include dealing with innovations in 3D, operating through a complex global supply chain, and figuring out how to leverage AI at all levels, from design to manufacturing. He described how PDF’s capabilities are at the intersection of these challenges with a common platform and database to improve collaboration and scale AI to drive operational efficiency.

Christophe went on to describe PDF’s three solution areas that all leverage a common data infrastructure powered by AI. The platform contains several significant capabilities that impact the entire semiconductor industry. This includes systems to help with characterization, including a unique contactless probing system developed by PDF. More on that in a moment.  There are also technologies to help optimize manufacturing and others to integrate and coordinate the worldwide supply chain. The diagram below summarizes how these systems leverage a common data infrastructure powered by AI to impact the entire semiconductor industry.

Christophe also described the broad impact PDF has on the entire semiconductor supply chain. The substantial design and manufacturing challenges the industry is facing can only be addressed with broad-based collaboration. There are many parts of the puzzle and they all must fit together optimally to make progress. PDF Solutions is a significant catalyst for this broad-based collaboration. PDF believes that doing this can only be done through the use of an open platform. With that open platform PDF is able to integrate with other solution providers used across the semiconductor industry. He shared the graphic below to illustrate the breadth of PDF’s impact and partnerships.

A Short but Potent Video

Dr. Dennis Ciplickas

This is the video that inspired the title of this post. It came from a discussion with Dr. Dennis Ciplickas, who spent 25 years at PDF Solutions. He said, “The time I spent at PDF fundamentally changed how I do my job…Being creative and giving yourself the freedom to be creative, even if you don’t really understand everything about the domain can lead to things you didn’t expect. Working at PDF we were always pushing the boundaries…and that led to insights…it’s the value of fearless creativity.” Dennis is now the technical lead manager for silicon product development at one of the leading cloud hyperscalers.

This video also describes the invention by PDF of eProbe, a contactless electrical test system that scans an entire wafer to identify and analyze hot spots. This is one example of how PDF pushes boundaries and improves the quality of semiconductor devices. There are many more such examples.

To Learn More

Dr. John Kibarian

I’ve provided just an overview of how PDF Solutions is changing the semiconductor ecosystem. There is so much more to the story. If advanced design is giving you a headache, you need to know about PDF Solutions. The company can help. You can listen to an informative podcast with Dr. John Kibarian, president, CEO and co-founder of PDF Solutions on SemiWiki here. There’s also a great interview with John on Investment Reports here.

There are a couple of excellent blog posts available on PDF’s website as well:

Secure Data Collaboration in the Semiconductor Industry: Unlocking Innovation Through AI and Connectivity

Perspectives on PDF Solutions Performance in 2024 and Path Forward

And of course, that excellent video I mentioned can be accessed here. And that’s an introduction to PDF Solutions and the value of fearless creativity.


Gartner Top Strategic Technology Trends for 2025: Agentic AI

Gartner Top Strategic Technology Trends for 2025: Agentic AI
by Admin on 08-17-2025 at 10:00 am

Figure 1 Mind the AI Agency Gap

Agentic AI refers to goal-driven software entities—“digital coworkers”—that can plan, decide, and act on an organization’s behalf with minimal supervision. Unlike classic chatbots or coding assistants that respond only to prompts, agentic systems combine models (e.g., LLMs) with memory, planning, tools/APIs, sensing, and guardrails so they can pursue outcomes, not just generate content.

Why now

Vendors are equipping assistants with planning and tool-use. Startups offer agent-building platforms; hyperscalers are weaving agentic capabilities into their stacks. As this matures, AI shifts from advisory to operational—able to analyze data across systems overnight, execute workflows, and report what it finished versus what still needs a human decision.

Opportunity landscape
  1. Performance gains that compound. Agents learn from feedback and environment, so quality and speed improve over time.

  2. Decision acceleration. They scan complex datasets, identify patterns, and take next actions, reducing modeling overhead and time-to-impact.

  3. Workforce augmentation. Natural-language orchestration lets teams manage intricate projects and micro-automations without deep tooling expertise.

  4. Scale and coverage. Multiagent systems coordinate many specialized agents—each perceiving and acting—to tackle goals no single agent could handle.

  5. Experience automation. From purchase to follow-up, agents can personalize outreach, time communications, and launch cross-sell offers, closing the loop without human intermediaries.

Strategic planning assumptions (2028 horizon)
  • One-third of enterprise apps will embed agentic AI (up from <1% in 2024).

  • Machine customers (agentic buyers) will handle about one-fifth of storefront interactions.

  • At least 15% of day-to-day work decisions will be made autonomously.

What changes in practice

Workflows will be designed for agents first, with humans inserted at high-value control points. Collaboration becomes tri-directional: humans→agents, agents→agents, and agents→humans. Software developers feel early impact as coding assistants evolve into agents that open tickets, refactor code, run tests, and submit merge requests. In operations, agents reconcile data, tune campaigns, or remediate incidents while you sleep—escalating only what truly needs judgment.

Risks and pitfalls
  • Governance drift. Without a registry, ownership model, and lifecycle controls, organizations can repeat the RPA “bot sprawl” problem.

  • Data quality & security. Agents act from enterprise data and tool access; poor data or weak identity controls can cause harmful actions.

  • Safety threats. Prompt injection, jailbreaks, data exfiltration, and agent-to-agent adversarial behavior demand new defenses.

  • Customer experience missteps. Autonomy can alienate customers if journeys aren’t intentionally designed.

  • Change management. Employees may resist perceived loss of control; roles must be clarified and upskilling funded.

Design principles
  • Agency is a spectrum. Decide, per workflow, what agents can observe, propose, approve, and execute.

  • User-in-the-loop by default. Start with propose/preview modes; graduate to execute-with-revert once reliability metrics pass thresholds.

  • Guardrails first. Enforce scoped permissions, environment sandboxes, rate limits, and bounded tool catalogs. Require provenance logging for every agent action.

  • Explainability & monitoring. Track goals, plans, tool calls, outcomes, and self-critique notes; alert on drift and unusual chains of actions.

  • Composable architecture. Use an orchestration layer that connects apps, data, identity, EPM/ITSM, and observability—so agents act through governed interfaces.

Near-term actions (next 6–12 months)
  1. Map candidate workflows where scale/latency matter and high-quality data already exists (support ops, marketing ops, finance close, IT service, supply planning).

  2. Define levels of agency for each: observe → recommend → execute with human approval → execute with rollback.

  3. Stand up an “AgentOps” discipline: registry, versioning, policy as code, red-teaming, simulation testing, and automated kill-switches.

  4. Harden identity and access. Give every agent a first-class identity, least-privilege roles, secrets management, and audit trails.

  5. Measure value. Instrument outcomes (cycle time, error rate, SLA adherence, revenue lift) and require business owners for every agent.

  6. Pilot multiagent patterns. Try specialist swarms (planner, tool-user, reviewer) with explicit protocols for delegation and critique.

Bottom line

Agentic AI moves enterprises from “generating insights” to taking action. The advantage goes to leaders who embed agency into architecture and governance—treating agents as Tier-1 digital coworkers with clear scopes, telemetry, and accountability—so performance scales without sacrificing safety, trust, or customer experience.

Access the Gartner whitepaper here.


AMAT China Collapse and TSMC Timing Trimming

AMAT China Collapse and TSMC Timing Trimming
by Robert Maire on 08-17-2025 at 10:00 am

Robert Maire

– AMAT has OK Q but horrible guide as China & Leading edge drop
– China finally chokes on indigestion & export issues -$500M hit
– TSMC trims on fab timing causing leading edge to slow -$500M hit
– Cycle which had slowed to single digits has rolled over to negative

AMAT guides down for big miss on Q4 expectations

Revenue came in at $7.3B and non GAAP EPS was $2.48 however guidance for the current quarter was dismal at best at $6.7B +- $500M and EPS of $2.11 +-$0.20, way below expectations.

China and leading edge will each be off by $500M

China will see a drop of about $500M due to indigestion, slowing, export licensing etc;.

The China slowing was somewhat inevitable as the numbers have been way too high for way too long but the rapidity of the drop is surprising and seems to suggest that management was caught by surprise as it was clearly unexpected.

Leading edge logic/foundry is also going to be off by $500M as management blamed timing of fab projects for the “non-linearity”, a nice way of saying a non expected drop. Management also seems to be caught by surprise by this drop as well.

Taken together this “surprise” drop of $1B was slightly offset by some better performance in AGS but far from enough to offset the large drop.

TSMC likely slowing near term

We have said a number of times that TSMC is so way far ahead of both Intel & Samsung that they can afford to take their foot off the gas of capex.

In addition there may also be some lumpiness of fab timing as indicated by management.

Has the spend cycle rolled over?

It certainly feels like the spend cycle has just unceremoniously rolled over.

We could be seeing the end of the long and strong China capex spend which has kept the semi equipment industry in goods times.

In addition with the bleeding edge consolidating to one player, TSMC, that will likely make the business much more lumpy and likely drive down margins as TSMC wields all the power and can dictate to equipment companies.

Memory is good but only in HBM and only until every manufacturer gets up to speed and oversupplies the commodity market again

The stocks

The stocks have been doing well despite the warning signs that have been cropping up.

Most of the chip equipment companies have seen their valuations at record levels.

AMATs report is not just another warning sign its hard evidence of slower times ahead

The stocks have been caught up in the rising tide of AI and data center capex but they are not 100% correlated to the same dynamic and this may be the point of divergence.

AMAT was off 14% in the aftermarket and we will likely see a lot of investors bail on the stock and the group in general as reality hits home.

We are also somewhat surprised that Applied was so surprised by this “Double Whammy” of slow downs and didn’t see either one coming. It doesn’t exactly give us a lot of faith in prediction capabilities.

Obviously there will be collateral damage on LRCX, KLAC and ASML among others. But Applied likely deserves a bit more of a downside hit due to the lack of foresight.

We don’t see a lot of reason to buy on the dip as it may take a while to find its new support level and we may see a rearrangement of investors in the mean time.

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies.

We have been covering the space longer and been involved with more transactions than any other financial professional in the space.

We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.

We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

Is a Semiconductor Equipment Pause Coming?

Musk’s new job as Samsung Fab Manager – Can he disrupt chip making? Intel outside

Elon Musk Given CHIPS Act & AI Oversight – Mulls Relocation of Taiwanese Fabs


CEO Interview with Russ Garcia with Menlo Micro

CEO Interview with Russ Garcia with Menlo Micro
by Daniel Nenni on 08-17-2025 at 8:00 am

RussGarcia MenloCEO

Russell (Russ) Garcia is a veteran technology executive with over 30 years of leadership experience in semiconductors, telecommunications, and advanced electronics. As CEO of Menlo Microsystems, he has led the commercialization of disruptive MEMS switch technology across RF, digital, and power systems.

Previously, Russ founded the advisory firm nGeniSys, served as an Executive in Residence at GE Ventures, and held senior leadership roles at Microsemi, Texas Instruments, and Silicon Systems. He also served as CEO of WiSpry and u-Nav Microelectronics, where he oversaw the launch of the industry’s first single-chip GPS device. Russ remains active as a board member and industry advisor.

Tell us about your company

Menlo Micro is setting a new standard in chip-based switch technology with its Ideal Switch by addressing the limitations of traditional electromechanical relays (EMRs) and solid-state (SS) switches.

Following the path of other disruptive innovators, our RF products are enabling customers in high-growth markets, particularly AI, aerospace, and defense to miniaturize their systems while enhancing performance, capability, and reliability. Driven by AI-fueled growth in data and the xPUs supporting the expansion, we’re responding to customer demand by delivering best-in-class miniature RF switch products – necessary for testing existing and future generations of high-speed digital data buses – and scaling to support increased adoption among the top semiconductor manufacturers.  We’re also expanding our high speed and high-performance RF switch products into the aerospace and defense sectors with engagements with top defense, radar, and radio OEMs.  With product adoption accelerating in the RF segment, the company is developing and positioning a new smart power control product platform to expand in AC/DC power distribution and control to meet a growing demand in microgrids, data centers, and factory automation.

Our technology overcomes system-level bottlenecks caused by traditional switching, enabling customers to push performance boundaries such as accelerating AI GPU testing, delivering step-function improvements in size, weight, power, and performance for satellite communications beamforming, enhancing filtering in mobile radios, reducing energy consumption in factory automation, and improving fault detection and power distribution in energy infrastructure.

What problems are you solving?

Across industries, engineers face critical limits with traditional switching technologies. EMRs are large, slow, and prone to mechanical wear. SS switches suffer from high on-resistance, leakage, and heat generation, which limits scalability, reliability, and efficiency.

In semiconductor testing, switch performance directly affects test speed, accuracy, and cost. Traditional switches degrade signals and limit bandwidth, increasing complexity and slowing time-to-market. Aerospace and defense systems demand rugged, reliable switches that meet tight size, weight, and power constraints, yet traditional options lack durability or require bulky protection. Power systems, from industrial automation to energy grids, face thermal inefficiencies that drive overdesign, and slow switching speed limits responsiveness to system faults.

Menlo’s technology is unique because as it is a true metallic conductor rather than a semiconductor, it delivers near-zero on-resistance, ultra-low power loss, and minimal heat generation. This eliminates the need for heat sinks and complex cooling, significantly improving thermal and power efficiency.

Built on a MEMS process, it achieves chip-scale integration, enabling up to 10x or more reductions in footprint and higher channel density for compact, scalable designs. It maintains reliable operation across extreme environments, from cryogenic to +150°C, and withstands shock and vibration, making it ideal for mission-critical applications.

With billions of cycles and no mechanical degradation, its long life combined with low power consumption and minimal thermal management reduces total cost of ownership through fewer replacements, simpler designs, and lower maintenance.

By solving the longstanding trade-offs between speed, power, size, and reliability, Menlo enables engineers to build smaller, faster, more energy-efficient, and reliable RF and power control systems.

What application areas are your strongest?

Our platform is strongest in high-performance industries, thanks to its broadband linearity, from DC to mmWave, and ultra-low contact resistance.

While our platform supports a wide range of demanding applications, from RF to power switching, one of Menlo’s fastest-growing areas is high-speed digital test. We’ve built a unique position by enabling high-integrity test solutions for advanced interfaces like PCIe Gen6 at up to 64 Gbps. Our switches offer a rare combination of broadband linearity from DC to mmWave, a compact footprint, and low on-resistance, ideal for both DC and high-speed environments. This dual capability allows customers to consolidate hardware, reduce signal distortion, and improve test density, improving ROI and lowering total cost of ownership. With proven reliability across billions of cycles, our solutions also minimize maintenance and system downtime – driving our growing market share in semiconductor test, especially among companies working on the next wave of AI processors, GPUs, and data center chipsets.

Looking ahead, Menlo is actively developing its next generation of switches to support PCIe Gen7 and Gen8, and scaling data rates of 128 and 256 Gbps. This roadmap is driven in close collaboration with our customers to align with their next-gen test infrastructure needs.

Beyond test, our innovations in high-speed switching are creating leverageable product platforms for adjacent markets. In aerospace and defense, for example, we’re applying this same high frequency control switching capability to ruggedized environments, where high performance, fast actuation, and extreme reliability are critical, such as phased array radar, electronic warfare, and advanced power protection systems.

How do customers normally engage with your company?

Collaboration is core to our approach. Because our technology supports everything from testing to deployment and optimization, we engage early and often, working not just to meet needs, but to anticipate them. Our team strives to “see around corners,” aligning our innovations with where the industry is headed.  To do this we create strong working partnerships with our customers – when our customers succeed through Menlo product integration, we succeed.

A strong example of this model is the development of the MM5620 switch. In 2023, we partnered with leading GPU and AI chip manufacturers to understand the growing challenges in semiconductor testing. As demands on AI chips, xPUs, and custom ASICs surged, legacy switching became a clear bottleneck, resulting in longer test cycles, increased complexity, and delayed time-to-market.

These insights led to the MM5620: a high-speed, high-linearity switch [array] delivering near-zero insertion loss, ultra-low contact resistance, and exceptional linearity from DC to mmWave. This allows next-gen device testing without compromising signal integrity or accuracy. This is a step-change in test efficiency, with customers reporting 2x faster test times, simplified hardware, lower overhead, and reduced consumables, key reasons top semiconductor companies choose to collaborate with us. Building on this success, we continue to partner with AI and high-performance computing leaders to help them stay ahead in a fast-moving, competitive market.

What keeps your customers up at night?

Our customers operate in industries like semiconductor supply chain, aerospace & defense, communications infrastructure and energy infrastructure where any failure or signal degradation can lead to significant financial impact, operational downtime, and safety risks. The increasing complexity and miniaturization of modern electrical systems amplify the vulnerabilities inherent in legacy switching technologies.

As system architectures demand higher bandwidth, faster switching speeds, and tighter thermal budgets, the tolerance for insertion loss, contact resistance, and thermal dissipation issues are rapidly diminishing. Consequently, customers are under significant pressure to mitigate these risks without compromising performance and reliability, while reducing total cost of ownership. This dynamic is driving customers to collaborate with us on current product offering adoption as well as their next-generation electronic systems.

What does the competitive landscape look like and how do you differentiate?

The promise of a true MEMS switch, i.e., a tiny, fast, efficient mechanical conductor, rather than a semiconductor, has long been recognized. However, scalability has been the major barrier. Over 30 companies have attempted to commercialize MEMS switches only to fail due to material and manufacturing challenges. Semiconductor fabs rely on materials like Silicon (a partial conductor) or soft metals, which cannot deliver the durability and reliability required for high-cycle mechanical elements.

Backed by R&D at GE, we developed a proprietary metal alloy system engineered to be highly conductive and mechanically robust for the device actuator and further integrated the alloy with a metal material system for reliable conductive contacts. This breakthrough in metallurgy enables the production of ultra-conductive, highly reliable switches capable of billions of actuations, delivering unmatched linearity from DC to mmWave with the highest power density per chip on the market. Process on glass substrates with metal-filled hermetic vias, our MEMS device delivers best-in-class RF and power performance.  This core construction differentiates us from competitors who either rely on semiconductor switches, limited by non-linearities, high losses and heat, or EMR technologies that lack scalability and ruggedness. It’s the integrated system that delivers the combined best-in-class performance, at both high power and high frequency, in a miniature chip scale package.

What new features/technology are you working on?

In April 2025, we launched the MM5230, a high-performance RF switch developed with key customers to meet the demands of next-gen systems. Combining ultra-high RF performance with manufacturability, it supports advanced military communications and high-density IC parallel testing, delivering the performance, reliability, and versatility critical to today’s most demanding applications.

In June, we followed with the MM5625, engineered to dramatically increase test throughput with increased channel density in high-speed, high-volume environments such as AI GPU testing. It enables faster test cycles, greater parallelism, and improved data processing, empowering leading semiconductor manufacturers to expand testing capacity, accelerate time-to-market, and reduce total cost of ownership.

Looking ahead, Menlo Micro is working with customers on next-gen switches for PCIe Gen7 and beyond, as well as mmWave products up to 80 GHz to support advanced aerospace and defense RF systems. We’re also advancing a robust power control roadmap for AI IC testing, high-voltage DC in data centers, and smart grid and industrial automation.

In parallel, we’re partnering with the U.S. Navy and the Defense Innovation Unit (DIU) to develop 1000VDC/125A modules for 10MWe advanced circuit breaker systems in micro-nuclear reactors. These compact, low-heat modules offer 5–6X reductions in size and weight and will extend to mission-critical commercial sectors like data centers, industrial automation, and EVs.

Also Read:

CEO Interview with Karim Beguir of InstaDeep

CEO Interview with Dr. Avi Madisetti of Mixed-Signal Devices

CEO Interview with Bob Fung of Owens Design


Video EP9: How Cycuity Enables Comprehensive Security Coverage with John Elliott

Video EP9: How Cycuity Enables Comprehensive Security Coverage with John Elliott
by Daniel Nenni on 08-15-2025 at 10:00 am

In this episode of the Semiconductor Insiders video series, Dan is joined by John Elliott, security applications engineer from Cycuity. With 35 years of EDA experience, John’s current focus is on security assurance of hardware designs.

John explains the importance of security coverage in the new global marketplace. He describes what’s needed to perform deep security verification of a design for both known and potentially unknown threats, and why it’s important to achieve good coverage. He also describes how Cycuity’s tools help perform the deep analysis and verification tasks to ensure a design is secure.

Contact Cycuity

The views, thoughts, and opinions expressed in these videos belong solely to the speaker, and not to the speaker’s employer, organization,
committee or any other group or individual.


Podcast EP303: How Lattice Semiconductor is Addressing Security Threats From the Ground Up with Mamta Gupta

Podcast EP303: How Lattice Semiconductor is Addressing Security Threats From the Ground Up with Mamta Gupta
by Daniel Nenni on 08-15-2025 at 6:00 am

Dan is joined by Mamta Gupta, She leads the Security Product Marketing, Datacenter and the Communications Segment Marketing Teams at Lattice. She brings with her over 20 years of FPGA experience in product development with special focus on security, aerospace and defense segments.

Dan explores the growing area of cybersecurity with a focus on silicon-level security with Mamta. She describes the importance of silicon-level security to ensure devices, software and the systems they implement are not compromised in manufacturing or in the field. She explains that attacks can take the form of direct assault on a system but can also be accomplished by corrupting the training data used in AI algorithms and insertion of weaknesses during manufacturing.

She explains how the FPGA technology from Lattice is creating the ability to design for security from the ground up in a proactive way. She describes the move from “bolt on” to “built in” for systems by using Lattice FPGAs. She also discusses how to deal with post quantum security and how nation states are now becoming more involved in this area as a matter of national security.

Contact Lattice Semiconductor

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


Semiconductors Still Strong in 2025

Semiconductors Still Strong in 2025
by Bill Jewell on 08-14-2025 at 2:00 pm

Semiconductor Market Change 2025

The global semiconductor market in 2Q 2025 was $180 billion, up 7.8% from 1Q 2025 and up 19.6% from 2Q 2024, according to WSTS. 2Q 2025 marked the sixth consecutive quarter with year-to-year growth of over 18%.

The table below shows the top twenty semiconductor companies by revenue. The list includes companies which sell devices on the open market. This excludes foundry companies such as TSMC and companies which only produce semiconductors for their internal use such as Apple. The revenue in most cases is for the total company, which may include some non-semiconductor revenue. In cases where revenue is broken out separately, semiconductor revenue is used.

Nvidia remains the largest semiconductor company based on its forecast of $45 billion in 2Q 2025 revenue. Memory companies Samsung and SK Hynix are second and third. Broadcom is fourth and long-time number one Intel has dropped to fifth.

Most companies reported solid growth in 2Q 2025 revenues versus 1Q 2025, with a weighted average increase of 7%. Memory companies showed the largest increases, with SK Hynix up 26%, Micron Technology up 16%, and Samsung up 11%. The healthiest revenue gains among the non-memory companies were Microchip Technologies at 11%, STMicroelectronics at 10%, and Texas Instruments at 9.3%. Five companies saw revenue decline from 1Q 2025.

Almost all the companies providing guidance expect healthy growth in 3Q 2025 revenues versus 2Q 2025. Again, the biggest gains are from memory companies, with Micron projecting 20% and Kioxia projecting 30%. Both companies cited demand form AI applications as the key driver.

STMicroelectronics guided 15% revenue growth with all its end markets up except auto. AMD projects a 13% increase driven by AI. The other six companies providing revenue growth guidance range from 1.7% to 7.7%. The only company expecting a revenue decline is MediaTek, with a drop of 10% in 3Q 2025 due to a weak mobile market.

AI remains the highest grow driver. Many companies are seeing upticks in their traditional markets. Some companies are experiencing growth in automotive revenues while other companies see automotive continuing to be weak. In their conference calls with financial analysts, most companies cited the uncertainties around tariffs and global trade as areas of concern.

The strong semiconductor market growth in the first half of 2025 practically guarantees double-digit full year growth. Recent forecasts are generally in a narrow range of 14% to 16%. WSTS revised its June forecast from 11.2% to 15.4% based on the 2Q 2025 data. We at Semiconductor Intelligence (SC IQ) remain cautious due to the uncertainty about global trade. But based on the strong first half of 2025, we are raising our 2025 forecast to 13% from the May forecast of 7%.

Projecting the impact of U.S. tariffs on global trade is difficult due to the frequent changes in threatened tariffs and implemented tariffs. In the case of China, the Trump administration in April threatened tariffs as high a 145%. In May, the administration put a 90-day pause on the higher tariffs and set tariffs on China at 30%. This week, the pause was extended until November.

Direct tariffs on semiconductors are very uncertain. Earlier this month, President Trump announced the U.S. will impose a 100% tariff on imports of semiconductors. He said companies that commit to building semiconductors in the U.S. will not face tariffs. Details of the plan have yet to be announced.

This month the Trump administration reached an agreement to provide export licenses for Nvidia and AMD to ship certain AI chips to China. The companies will be required to pay 15% of the revenue from these sales to the U.S. government. The legality of this agreement is questionable. The U.S. Constitution prohibits Congress from putting taxes or duties on exports. EE Times describes the deal as “unique”.

One area which has already seen an impact from tariffs is smartphones. As we have noted in previous newsletters, U.S. imports of smartphones have been dropping dramatically in recent months. 2Q 2025 U.S. smartphone imports dropped 58% in dollars and 47% in units from 1Q 2025. Smartphone unit imports from China declined 85%. Although there are currently no tariffs on smartphone imports, the threat of tariffs has had a significant impact. Canalys estimated 2Q 2025 U.S. smartphone sales were down about 20% from 1Q 2025. Many of the 2Q 2025 sales came from existing inventory. However, U.S. smartphone sales should drop significantly in the second half of 2025. Despite the drop in exports to the U.S., China smartphone manufacturing has remained strong, with unit production in 2Q 2025 up 5% from 1Q 2025.

The current semiconductor market is strong. Ongoing global trade disputes are a significant concern, but so far have not had a meaningful impact. The Trump administration tariff threats may become, to quote Shakespeare’s MacBeth, “sound and fury, signifying nothing.”

Also Read:

U.S. Imports Shifting

Electronics Up, Smartphones down

Semiconductor Market Uncertainty


Moving Beyond RTL at #62DAC

Moving Beyond RTL at #62DAC
by Daniel Payne on 08-14-2025 at 10:00 am

beyond rtl min

Hardware designers have been using RTL and hardware description languages since the 1980s, yet many attempts at moving beyond RTL have tried to gain a foothold. At the #62DAC event I spent some time with Mike Fingeroff, the Chief High-Level Synthesis Technologist to understand what his company Rise Design Automation is up to. Mike has two decades of experience in High Level Synthesis (HLS) and even authored a book in 2010 on HLS.

One major theme at DAC this year was using GenAI to create RTL faster. At RISE they support a methodology using several higher-level languages like SystemVerilog, C++ or SystemC. Verilog designers gravitate towards using SystemVerilog with loose timing for control flow designs, while C++ is an appropriate language for dataflow designs. Mike thinks that you should use the best language for each block, then mix abstractions as needed.

All of the popular EDA simulators support multiple languages for design descriptions spanning from RTL to transaction level. Many tier-one companies have proven that HLS flows are more productive than RTL: Google, NVIDIA, Qualcomm. The new challenges are providing a complete tool chain for HLS that use AI agents, instead of requiring experts to run the tools.

With RISE there are AI advisors and agents to help you generate high-level code using LLMs that already understand high-level coding from Python and C repositories. Their AI works with engineers to create the code easily by using chat prompts. Traditional LLMs are being used either on-premise or in the cloud, your choice, and they are pre-trained for you.

An LLM doesn’t really know HW design, so they had to show them how to make HW from C++ code. They have an Agent Orchestrator that calls the RISE tools, views the results, and continues to iterate to explore the design space. This iteration loop can also contain logic synthesis and P&R tools as well.

Rise.ai Adviser is a generative AI advisor aimed at high-level design with natural language input, creating designs in SystemVerilog, SystemC and C++. Test benches are created in both C++ and UVM. You can analyze your design then optimize for area, power or speed. This all runs on a local processor or something larger if you really want to. During design exploration you can call your own tools, like VCS for power numbers, or Open ROAD tools for synthesis and P&R.

Verification speed ups with higher abstraction levels range from 100X to 1,000X faster. RISE verification has automatic channel capture for waveforms, automatic high-level to RTL comparisons, and utilities for sub-system assembly and verification testbenches.

Summary

RISE Design Automation did create a buzz at DAC this year, because their message was something that RTL designers want – becoming more productive by raising the design and verification abstractions, using faster toolchains and benefitting from generative AI integration. You can learn more about RISE by visiting their website and then think about starting an evaluation to produce better design and verification results from your team.

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Streamlining Functional Verification for Multi-Die and Chiplet Designs

Streamlining Functional Verification for Multi-Die and Chiplet Designs
by Daniel Nenni on 08-14-2025 at 6:00 am

Streamlining Functional Verification for Multi Die and Chiplet Designs

As multi-die and chiplet-based system designs become more prevalent in advanced electronics, much of the focus has been on physical design challenges. However, verification—particularly functional correctness and interoperability of inter-die connections—is just as critical. Interfaces such as UCIe or custom interconnects must be rigorously tested to ensure the entire system performs as intended.

Traditional verification methods face serious challenges when applied to multi-die systems. Creating a unified top-level simulation that includes all dies is computationally demanding. Memory utilization often exceeds the capabilities of typical compute servers, which are geared more toward verifying individual IP blocks or subsystems. Although premium emulation and prototyping platforms like Palladium and Protium can manage such large-scale simulations, they are generally reserved for later stages of validation and software bring-up, not early-stage design.

Most early and mid-cycle verification relies on simulators like Xcelium Simulator, which perform power regressions across thousands of runs. These use existing compute farms, but the capacity limitations of typical servers prevent full-system simulations from being practical. Another bottleneck is the time and effort needed to build and debug a new top-level testbench for the integrated system, which can take weeks even when each die has already been verified independently.

A serial approach to interoperability testing is risky. In modern development flows, the goal is always to “shift left”to detect and fix issues as early as possible. Waiting until interposer designs are finalized and all die models are complete delays verification unnecessarily. There’s a better path forward: begin interoperability testing as soon as two or more die models are available, even if other parts of the system are still in development.

This is where the Xcelium Distributed Simulation Verification App offers a game-changing solution. Rather than simulating the entire system as one monolithic design, the Xcelium App enables each die to be simulated in its own process, running independently but connected through Xcelium Virtual Channels that abstract away RTL-level bus interfaces. These distributed simulations use the existing testbenches created for individual dies, significantly reducing the time and effort needed to verify multi-die systems.

Customer experience with the App shows that adapting to this distributed approach typically takes just a few days. Once connected, these simulations enable a wide range of interoperability testing scenarios, including register access, concurrency, die-to-die CRC and retry mechanisms, protocol interactions, and physical-layer behaviors like scrambling and lane repair. These tests are essential for signoff quality assurance in multi-die environments.

Importantly, distributed simulation allows verification activities to begin up to three months earlier than traditional methods well before the interposer layout is finalized. The simulation model is constructed with only minor changes: conditional compile switches to handle traffic generation and memory maps, along with API calls to configure Xcelium Virtual Channels. From there, the Xcelium App handles the distributed communication and synchronization.

Performance is a key concern, but real-world testing has shown distributed simulations to be up to 3X faster than integrated top-level simulations, even with inter-process communication overhead. This is because Xcelium Virtual Channels minimize synchronization needs, allowing each simulation to run at optimal speed except during necessary transaction updates.

The potential of distributed simulation isn’t limited to multi-die systems. As individual dies grow in complexity, the same methodology could be applied to partition large single-die designs into independently simulated blocks, each with its own testbench. With the right communication strategy—favoring asynchronous transaction-based links over tightly coupled cycle-by-cycle synchronization—distributed simulation can scale to manage increasing design sizes efficiently.

Bottom line: Multi-die systems are becoming a foundational part of modern electronics, yet functional verification has struggled to keep pace with physical integration. The Xcelium Distributed Simulation Verification App provides a robust, scalable, and early-deployable solution. It enables full-system functional verification using existing testbenches and compute infrastructure, advancing shift-left strategies and accelerating development cycles without sacrificing quality or confidence in design correctness.

You can view the whitepaper here.

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Chiplets and Cadence at #62DAC

Prompt Engineering for Security: Innovation in Verification

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S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China

S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China
by Daniel Nenni on 08-13-2025 at 10:00 am

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Shanghai, July 19, 2025 — S2C, a leader in functional verification, showcased its latest digital EDA solutions and key partnerships with BOSC, Xuantie, and Andes Technology at RISC-V Summit China 2025, highlighting its contributions to the ecosystem. The company also played a leading role in the EDA sub-forum, with VP Ying J Chen co-chairing and Senior Engineer Dehao Yang delivering insights on accelerating RISC-V adoption through practical strategies.

Showcasing Diverse RISC-V Applications with Ecosystem Partners

Leveraging its comprehensive digital EDA portfolio, S2C delivers matching verification solutions across the RISC-V ecosystem—addressing verification needs ranging from IP validation to system-level verification. Through close partnerships with leading RISC-V vendors, S2C provides high-performance, scalable prototyping solutions that accelerate time-to-market from early design bring-up to full-system deployment.

At the summit, S2C showcased its FPGA prototyping solutions with live demos across multiple RISC-V applications – including the Xiangshan processor running a graphical Linux interface. S2C has collaborated with Beijing Open Source Chip Research Institute (BOSC) since the first-generation Xiangshan CPU. In the recent validation of its third-generation Kunminghu processor – a 16-core RISC-V design with NoC interconnect running on two S8-100Q Logic Systems (each with 4 VP1902 FPGAs) were deployed and achieved a static timing closure at 12MHz. BOSC recognized S2C as a “Strategic Contributor” for its critical role in accelerating Xiangshan’s development cycle.

Additionally, Xuantie R908—a high-efficiency processor designed for real-time performance—was demonstrated live running on S2C S7-19P Logic System. The demo effectively demonstrated its low-latency operation and field-ready reliability.

Equally notable was Andes Technology’s 64-bit RISC-V vector processor IP core, the AX45MPV – running Linux and large language models easily efficiently on S2C’s S8-100 Logic System through the Andes Custom Extension (ACE) framework.

Overcoming Simulation Bottlenecks with Transaction-Based Acceleration

The RISC-V Verification Interface (RVVI) provides a standardized framework to ensure ISA compliance and functional correctness. Yet, as RISC-V designs grow in complexity—especially with custom extensions—traditional simulation methods encounter challenges like slow execution speeds, limited debug visibility, and difficulties scaling to full system-level verification.

To address these challenges, the keynote by Yang Dehao focused on Transaction-Based Acceleration (TBA), a verification methodology that enhances RVVI by decomposing test scenarios into reusable transaction flows. TBA leverages co-simulation between virtual prototyping platforms and hardware emulators—using tools such as S2C’s Genesis Architect and OmniArk/OmniDrive—to significantly improve verification speed and observability at scale, while maintaining RVVI compliance.

This approach exemplifies how advanced verification methodologies, combined with powerful prototyping tools, can accelerate the path from RTL validation to full-chip system verification.

Building on this, VP of marketing Ying J Chen highlighted S2C’s continued commitment to ecosystem collaboration and innovation:

“It is exciting to see thousands of engineers at the summit, and the manifestation of our partners’ RISC-V cores drawing a large crowd to our booth,” stated Ying J Chen, VP of Marketing at S2C. “We don’t just see ourselves as tool providers—we’re also an advocate for innovation and customers’ success. We’re committed to deepening our effort in the RISC-V community and broaden the ecosystem.”

S2C Inc. is a global provider of FPGA prototyping solutions for SoC (System on Chip) and ASIC (Application-Specific Integrated Circuit) designsThey offer hardware, software, and system-level design verification tools to accelerate the development process. S2C’s solutions are used for design exploration, IP development, hardware verification, system validation, software development, and compatibility testing. 

Also Read:

Double SoC prototyping performance with S2C’s VP1902-based S8-100

Enabling RISC-V & AI Innovations with Andes AX45MPV Running Live on S2C Prodigy S8-100 Prototyping System

Cost-Effective and Scalable: A Smarter Choice for RISC-V Development