SemiWiki – Page 48 – The Open Forum for Semiconductor Professionals

November 5, 2024May 1, 2025

The Convergence of Functional with Safety, Security and PPA Verification

The Convergence of Functional with Safety, Security and PPA Verification
by Nicky Khodadad on 11-05-2024 at 10:00 am
Categories: Axiomise, Semiconductor Services

Formal For All!

“Do I need a PhD to use formal verification?”
“Can formal methods really scale?”
“Is it too difficult to write formal properties that actually prove something?”
“If I can’t get a proof, should I just hope for the best?”
“Do formal methods even offer useful coverage metrics?”

…

Discouraging words to say the least, but we don’t have to live in the shadows they create anymore!

AI technologies are getting adopted faster than ever and the implementation of AI algorithms are no longer limited to purely software. In fact, breakthroughs in AI performance and the need to reduce energy consumption footprint are driving crazy innovations in hardware designs. So, for the first time, power, performance and area (PPA) along with functional verification has become a mainstream challenge; not to mention that with the adoption of AI hardware in embedded, IoT and edge – safety & security is now even a bigger challenge!

In a recent keynote at DVCon India given by Dr. Ashish Darbari, founder & CEO of Axiomise, he described how 10³⁰simulation cycles are not finding the bugs causing expensive respins. The respins are estimated to be 76% for ASICS with 84% of FPGA designs going through non-trivial bug escapes – the data coming from the well-known Wilson Research survey, 2022.

Axiomise: Making formal normal through consulting, training and automated IP

At Axiomise, we have been driving a vision of making formal normal and predictable for all kinds of semiconductor design verification. With over 60+ person years of combined formal verification experience in applying formal methods for silicon verification, the Axiomise team has verified over 150 designs covering GPU blocks, networking switches, programmable routers, NoCs, coherent fabrics, video IP components and hyper-scalers implemented with the three major CPU architectures including RISC-V, Arm, and x86. We have been able to achieve this through a combination of consulting & services engagements powered by automation derived from custom IP such as formalISA app for RISC-V and bespoke formal assertion IP for standard bus protocols such as AXI and ACE.

We love bringing in this experience to the masses and we have been delivering training through a unique combination of on-demand and instructor-led courses for the last 7 years at Axiomise. Our trained portfolio of hundreds of engineers now covers some of the Who’s Who of the industry.

Back to the drawing board

While we were training smart engineers in the industry, we learnt what is working for them and what is not and based on this experience we have come out with our most condensed and practical course yet! Learn the essentials of model checking from an industry expert who has pioneered a lot of the methods and abstractions used by experts in the industry today.

With 65 patents, and nearly 3 decades of experience, Axiomise founder and CEO Dr. Ashish Darbari brings this course, Essential Introduction to Practical Formal Verification, to anyone who has the desire to set foot on this journey.

With formal, we can find bugs early in design cycle, accomplishing the shift-left vision as well as prove bug absence through mathematical proofs.

Essential Introduction to Practical Formal Verification

Our goal is to make formal normal. And that’s how we’ve approached making this course, not just in making sure we start from scratch and build up knowledge as we go along, but also ensuring that the complex subject of formal is presented in a way that makes it easy for everyone to get started with formal. The course takes the complex topics of abstraction, problem reduction, design validation, verification and coverage and presents them with examples, and case studies to make it easier to understand the scope of formal for large design verification.

The course is delivered as an on-demand, video based online course, with lots of quizzes to test your understanding, live demos, example code to play with, a certificate at the end, and of course some food for thought to encourage you to go further and not just stop there.

Reaching out to non-English speaking audience

We made a genuine effort to reach out to non-English speaking audience in the world by providing subtitles for every video in 5 languages other than English. We have subtitles in available in French, Spanish, Portuguese, Japanese, and Chinese.

Priced with accessibility in mind, our goal is that with your help we can break free of just-good-enough designs and create a new standard for what we expect the future to look like. When it comes to depending more and more on our electronic devices and all the safety critical aspects, they can be a part of, one bug is enough for a catastrophe!

Every journey begins with a first step

One bug is one bug too many! We can never know when or where the next escaped catastrophic bug will appear, but we do live in a world where it could have been prevented, if the standard was to actually prove bug absence. And who knows, somewhere, maybe even close by, the most obscure and dangerous bug could be in the process of being written within a piece of code right now as you read this text.

Let’s get started in deploying formal for semiconductor design and work collectively to make formal normal!

Authors

Nicky Khodadad, Formal Verification Engineer, Axiomise

Ashish Darbari, Founder and CEO, Axiomise

Also Read:

An Enduring Growth Challenge for Formal Verification

2024 Outlook with Laura Long of Axiomise

RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®

November 5, 2024January 25, 2025

New Product for In-System Test

The annual ITC event is happening this week in San Diego as semiconductor test professionals gather from around the world to discuss their emerging challenges and new approaches, so last week I had the opportunity to get an advance look at something new from Siemens named Tessent In-System Test software. Jeff Mayer, Product Manager, Tessent Logic Test Products brought me up to speed on this new product announcement.

Jeff explained how customers in two markets are converging on the same goals to detect premature device failures, monitor health of aging devices, plus guard against Silent Data Errors (SDE) and Silent Data Corruption (SDC). The two markets and their test approaches are:

Safety & Security – Automotive

Logic BIST for in-system test
Embedded deterministic test for manufacturing quality
Beginning to adopt advanced technology nodes

Quality – Networking, Data Center

Beginning to adopt in-system test
Embedded deterministic test for manufacturing quality
Already using advanced technology nodes

Data centers desire to extend the lifetime of their investments, because it’s just too costly to continuously upgrade the compute infrastructure. An emerging challenge with HPC and data centers is the challenge of Silent Data Errors as reported by Facebook, Google and Intel, because they are related to PVT variations and the workloads being run, which are difficult to reproduce. HPC vendors don’t want to take their servers offline for testing, so they opt to do testing during scheduled maintenance times.

In-system testing is required to ensure reliable electronic operation over the lifetime of a product, by considering semiconductor device issues like:

Incomplete test coverage
Small delay faults
Subtle defects
Test escapes caused by test marginalities
Early-life failures
Random failures
Silicon aging

Failure rates over time

Tessent In-System Test

What Siemens has created is a new In-System Test Controller placed as an IP block inside your SoC, enabling in-system deterministic test with the Tessent Streaming Scan Network (SSN) software.

This new ISTC block supports all Tessent MissionMode features for IJTAG and BIST instruments. Your test data is delivered through the AXI or APB system bus, which connects to functional interfaces like PCIe or USB. This new approach can target specific cell-internal and aging defects using high-quality, deterministic patterns. You can even change your test content in the field, targeting learned defectivity rates through the silicon lifecycle. The Tessent In-System Test (IST) is a superset of Tessent MissionMode, so here’s a more detailed view of how that all connects.

Tessent In-System Test (IST)

Summary

Safety-minded customers are adopting advanced technology nodes, and quality-minded customers want to leverage existing on-chip IP for in-system test, so both markets benefit from in-system test methodologies. Semiconductor device failures can be detected using in-system and in-field monitoring for errors. Combining Tessent In-System Test with Tessent Streaming Scan Network and Tessent TestKompress is a proven way to detect test escapes in-system and in-field.

There’s a live webinar on this topic of applying manufacturing quality test patterns direct to a design, leveraging the benefits of deterministic test over transitional in-system test methods. The webinar is on November 19^th.

At ITC there are customers of this new technology presenting their initial results in a paper and a poster session, and silicon is already out, with more tape-outs underway. Like other Tessent products, there is no royalty for using this test IP. If your team already uses SSN, then you can quickly evaluate adding IST by talking to your local AE and AM team.

Related Blogs

November 5, 2024January 25, 2025

An Illuminating Real Number Modeling Example in Functional Verification

An Illuminating Real Number Modeling Example in Functional Verification
by Bernard Murphy on 11-05-2024 at 6:00 am
Categories: EDA, Siemens EDA

Data stream sine waves 1s and 0s orange Getty 496123972 EXT min

I just read an interesting white paper on functional verification of analog blocks using SV-RNM (SystemVerilog real number modeling). The content is worth the effort to read closely as it elaborates a functional verification flow for RNM matching expectations for digital logic verification, from randomization to functional coverage, assertions and checkers, and integration into UVM. The white paper illustrates for an ADC and a DAC.

The importance of mixed-signal verification

AI may dominate the headlines but outside of cloud and AI PC deployments, real applications must interact with real-world analog inputs, from cameras, radar, lidar, to audio, and drive analog outputs for lighting, speakers, and actuators. (In fact even in the cloud, systems must monitor temperature, humidity, and supply voltage levels. But that’s another story.)

Verifying correct interactions between digital and analog circuits has until recently depended on co-simulation between SPICE (or accelerated SPICE) modeling of analog transistor circuit behavior and logic simulator modeling of digital logic behavior in SystemVerilog. Since circuit simulation runs many orders of magnitude slower than logic simulation, practical testing has been limited to running only simple handoff sequences across the analog/digital interface.

Today analog and digital designs are much more tightly coupled, to control and monitor analog parametrics. Modern DDR interfaces provide a good example of this coupling in their training cycles. Verifying correctness in such cases requires much more extensive sequence testing between analog and digital circuits, often interacting with software-driven control on the digital side. Simulation then needs to run closer to digital simulation speeds to have hope of achieving reasonable coverage in testing.

Real number modeling (RNM)

In digital simulators a signal can be a 0 or a 1; their speed depends on this simplification. Analog simulators model signal values (and times) as real numbers, a signal voltage might be 0.314 at time 0.125 for example. RNM allows for a compromise in analog modeling in which analog signals can be quantized (amplitude and time), allowing for discrete modeling. (Full disclosure, RNM modeling also considers currents and impedances, not essential to this particular set of examples.)

Digital simulators have been adapted to deal with such quantized values and can still run much faster than real number-based SPICE, while also coupling to the regular digital logic simulator. More complex test plans become possible, and with suitable support for RNM compatible with digital verification expectations (randomization, constraints, assertions, coverage props, and UVM support), NVM-based verification can integrate very easily with mainstream verification flows.

Highlighted functional verification features

The first point the paper covers is constrained randomization for a flash ADC. They consider the resistive divider chain providing reference voltages from AVDD down to AGND, in say 8 steps, with comparators at each step. These resistors won’t be perfectly matched, so some randomized error (within constrained bounds) can be attached to each. Equally, testing should allow for (constrained) variation in AVDD – AGND. Finally, the input to the ADC can be defined either through deterministic sequences or as randomized sequences within the allowed range.

Coverage is straightforward. The paper suggests looking for analog signal samples in bins from minimum signal amplitude to maximum signal amplitude. Any uncovered bin indicates the need for more comprehensive testing, described in a SemiWiki article written by this paper’s author.

The section on assertions provides nice examples for how analog/digital assertions are constructed. Nothing mysterious here. For an ADC, the check quantizes the input voltage to an expected digital value and compares that value with the output of the ADC. For the DAC, simply invert this check, comparing the expected output voltage with the DAC output voltage.

UVM integration details will make more sense to UVM experts than to me (a UVM illiterate). I know it’s important and appears to be quite detailed in the examples.

The paper wraps up with a nice discussion on measuring linearity in these devices, a topic you wouldn’t find in logic verification, and a discussion on results of the analysis. My takeaway from the second point is that here is an opportunity to consider the randomization constraints set in the beginning. Overestimating these constraints could lead to more errors than observed in silicon, and, of course, underestimating could be disastrous. I expect getting this right probably requires some level of calibration against silicon devices.

Thought-provoking paper for me. You can read it HERE.

Also Read:

How to Update Your FPGA Devices with Questa

The RISC-V and Open-Source Functional Verification Challenge

Prioritize Short Isolation for Faster SoC Verification

November 4, 2024December 13, 2024

MIPI solutions for driving dual-display foldable devices

MIPI solutions for driving dual-display foldable devices
by Don Dingee on 11-04-2024 at 10:00 am
Categories: IP, Mixel

Flexible LCD technology has spurred a wave of creativity in device design, including a new class of foldable phones and an update to the venerable flip phone. Besides the primary display inside the fold – sometimes taking the entire inside area – a smaller secondary display is often found outside the fold. Introducing the secondary display adds more challenges than meet the eye. One of Mixel’s MIPI IP customers, Hercules Microelectronics, is creating innovative MIPI solutions for driving dual-display foldable devices.

Offloading foldable display tasks from an application processor

Adding a feature to a mobile device often means adding an IP block to the application processor (AP). Driving dual displays reveals subtle integration issues, including always-on requirements, that make a strong case for a different implementation.

The first is the physical interfaces. MIPI interfaces are standard in mobile devices, offering speed and power efficiency for driving displays. MIPI is the unquestioned choice to drive the primary foldable display. Still, power requirements increase if the AP manages the MIPI interface as primary displays move to higher resolutions and increased frame rates. Conventional solutions to save power are well-known: dimming the display, reducing its resolution or frame rate, or powering it down entirely.

Add a secondary display on the outside of the device case, usually smaller and with a lower resolution. Reducing the size and costs of these displays has pushed vendors to an alternative interface – QSPI, a feature often found on pin-count-sensitive microcontrollers but not on most APs. Physically adding QSPI is simple, but keeping portions of the AP on just to drive a small always-on display gets expensive in battery drain. The secondary display power requirements increase with rotation, chewing up computational resources and power to keep the display upright as the device turns.

All this points to what might be a counterintuitive conclusion for mobile device designers: an external dual display controller could achieve overall power savings by offloading foldable display tasks and keeping the AP at minimal power when folded. Using an external controller also reduces the time and risk of modifying an AP for dual-display foldable devices and their always-on nature.

MIPI interfaces integrated into low-power FPGA manages dual displays

This external controller would have to be low power yet have enough performance to take a MIPI stream from the AP host and convert it into a MIPI interface for the primary display with resolution up-scaling and a QSPI interface with the required rotational processing and always-on control. Ideally, it would also quickly adapt to various display configurations to keep costs down while supporting various foldable devices.

Hercules Microelectronics (HME) has a family of low-power SRAM-based FPGA devices that fit this profile. Their HME-H3 combines an Arm Cortex-M3 core and six hard MIPI IP products included: a C-PHY/D-PHY combo Rx with DSI peripheral and CSI-2 Rx controllers and a D-PHY Tx with DSI host and CSI-2 Tx controller cores. Adding the QSPI interface and control to the FPGA logic in the H3 is straightforward for a complete dual-display solution, as shown next.

Mixel provided HME with its MIPI C-PHY/D-PHY Combo IP and MIPI D-PHY IP. Mixel’s MIPI IP supports MIPI C-PHY v2.0 with 3 trios at speeds of up to 2.5G symbols per second per trio and MIPI D-PHY v2.5 with 4 lanes at speeds of up to 2.5Gbps per lane. These lanes provide a total aggregate bandwidth of 17.1Gbps in C-PHY mode and 10.0Gbps in D-PHY mode. HME achieved first-time silicon success with Mixel’s integrated MIPI solutions.

With Mixel’s MIPI IP products deployed in many applications, this was a low-risk, rapid-return solution for HME and its customers. The HME-H3 was already in use in video bridging and embedded vision applications and extending it to dual-display foldable device applications opens more possibilities for designers.

HME-H3 is Hercules Microelectronics’ second-generation product to leverage Mixel’s MIPI IP with first-time silicon success. The first product, HME-H1D03 FPGA, integrated Mixel’s MIPI D-PHY IP and won Best FPGA of the Year Award at the 2020 China IC Design Achievement Award Ceremony.

Flexible LCDs free designers from many physical design constraints, leading to a wide range of foldable and flip devices entering the market. The success of any mobile device in the market continues to rely on a blend of display performance and power efficiency for the experience users expect. MIPI solutions for driving dual-display foldable devices are crucial to achieving the experience.

See what Hercules Microelectronics and Mixel say about this application:

Mixel MIPI C-PHY/D-PHY Combo IP Integrated into Hercules Microelectronics HME-H3 FPGA

To learn more about Mixel’s MIPI IP product solutions in this application, please visit:

Mixel MIPI IP Cores

Also Read:

Ultra-low-power MIPI use case for streaming sensors

2024 Outlook with Justin Endo of Mixel

Automotive-grade MIPI PHY IP drives multi-sensor solutions

November 4, 2024November 4, 2024

Notes from DVCon Europe 2024

Notes from DVCon Europe 2024
by Jakob Engblom on 11-04-2024 at 6:00 am
Categories: Accellera, Events, RISC-V, Semiconductor Services

The 2024 DVCon (Design and Verification) Europe conference took place on October 15 and 16, in its traditional location at the Holiday Inn Munich City Centre. Artificial intelligence and software were prominent topics, along with the traditional DVCon topics like virtual platforms, RTL verification, and validation.

The decorated Lebkuchenherzen are given as gifts to all speakers at the conference.

Keynotes: Infineon and Zyphra

The keynotes provide high-level insights into broader technology industry trends and future directions, complementing the more detailed tutorials and paper presentations. A DVCon Europe keynote is not necessarily so much about how to build IP, chips, and systems, but about what they are being used for and the products they are part of. Not surprisingly, artificial intelligence (AI) has come up in most keynotes from the past few years…

This year started with Thomas Böhm from Infineon talking about “Dependable microcontroller architectures”. Microcontrollers are getting significantly more complex and are adding core clusters and accelerators to handle increases in compute requirements as well as low-latency handling of secured communication.

AI and machine learning (ML) techniques are being used in microcontrollers to implement fundamental control. This requires specialized hardware acceleration at a much smaller scale than what you find in datacenters and even client chips. Traffic on in-vehicle networks is encrypted, requiring security hardware acceleration to maintain low latency.

The second keynote came from Erik Norden from Zyphra, a startup that just went out of stealth in time for Erik to tell us the name of the company at DVCon! His talk was about “Next 10x in AI – System, Silicon, Algorithms, Data” – i.e., AI at datacenter scale. It was particularly interesting to hear Erik’s take on this as he started out on the hardware side and has moved towards the software/algorithm side.

Building an efficient and scalable AI system requires tweaking all aspects. For example, using a better training data set can improve the performance of a same-size model on same-size hardware. Zyphra has also developed new LLM architectures that get more performance out of existing hardware by using it more efficiently.

Software

The panel discussion, “Digital Transformation in Automotive – Expectations versus Reality”, spent a lot of time on software.

Software is becoming increasingly important to “traditional” automotive companies. It used to be specified as part of the functionality of physical components, but with the advent of software-defined vehicles (SDV) it is necessary to transition to a software-first model. Companies like Tesla have totally changed how software is treated and proven the model of delivering incremental value to the same hardware over time by software changes. I really liked the point being made that it has be to be made fun to work with software in automotive.

Software is also showing up in classic design and verification papers – both as part of the device-under-test and as part of the stimuli. More than half of all the papers at the conference addressed software in some way.

Open Source

Open-source software and open-source EDA software have grown in importance over time. There were papers and tutorials about open-source technologies like Qemu and cocotb, and open-source software like Linux is very commonly used in domains like automotive. Having access to hardware design flows based on open-source tools lowers the barrier to entry and brings more enthusiasts into the hardware design field.

Another open-source technology that is seeing major adoption is obviously RISC-V. Thomas Böhm’s keynote mentioned it as the potential future for automotive designs, and it was present in papers and tutorials.

Locally Global

DVCon Europe encompassed two keynotes, one panel, a day of tutorials, and 55 peer-reviewed papers split across an engineering and a research track. The conference takes place in the heart of Europe, but participants from all over the world! Some data was presented in the following slide:

For a deeper dive into what was discussed at the conference, check out https://jakob.engbloms.se/archives/4362 and the DVCon Europe group on linkedIn.

Also Read:

Accellera and PSS 3.0 at #61DAC

An Accellera Functional Safety Update

DVCon Europe is Coming Soon. Sign Up Now

November 2, 2024November 8, 2024

KLAC – OK Qtr/Guide – Slow Growth – 2025 Leading Edge Offset by China – Mask Mash

KLAC – OK Qtr/Guide – Slow Growth – 2025 Leading Edge Offset by China – Mask Mash
by Robert Maire on 11-02-2024 at 8:00 am
Categories: Semiconductor Advisors, Semiconductor Services

KLA put up an OK Quarter & Guide with modest growth & outlook
2025 remains slow growth as leading edge offset by China slowing
China sanctions remain a “great unknown”- impact unclear
Reticle biz getting squeezed from both high & low ends

OK quarter with slight beat as always- Guide is OK as well

KLA reported revenues of $2.84B and EPS of $7.33 (Non-GAAP) slightly above guide an expectation (as always). Guidance was for $2.95B +- $150M and EPS of $7.75+- $0.60.

The slow and steady recovery continues as the fortunes of the semiconductor industry remain mixed with leading edge foundry (read that as TSMC / Nvidia) remains super strong while trailing edge is weak with China moderating.

In memory NAND continues to be very weak while the only bright spot remains HBM-DRAM (again related to AI)

The leading edge strength appears to be strong enough to drag along the weaker sectors into positive growth territory.

Expectations for 2024 WFE spend is now estimated to be in the high $90’sB up from prior views of mid $90’sB.

China moderating as expected

As we heard from Lam last week, China continues to moderate and was down to 42% of business with expectations that China will fall to somewhere in the 30’s in the December quarter with expectations of “digestion” of the binge buying slowing further into 2025

China sanctions remain a “great unknown”

Management did not estimate the potential downside of any expected tightening of China sanctions that would impact the semiconductor industry, taking a more “wait and see” attitude about the potential downside

Leading Edge (TSMC) is strong enough to offset the rest of industry weakness

With Samsung and Intel both moderating spending on the foundry side, the clear winner and big spender remains TSMC which is quickly becoming (perhaps already is ) a monopoly in foundry.

Everyone else continues to fall further behind and the disparity in spend will only increase the gap.

TSMC’s spend is further multiplied by additional locations, such as Arizona, coming up to speed.

Given the revenue they are getting from Nvidia they certainly have the cash flow to keep up the spend rate.

KLA reticle inspection getting squeezed at both high and low ends

Looking at the numbers that KLA reported, wafer inspection grew a whopping 36% year over year and up 17% sequentially.

Reticle inspection (patterning) grew a paltry 6% year over year and coincidentally 6% quarter over quarter.

The disparity has grown huge with wafer inspection for 48% of revenues and reticle inspection (patterning) accounting for a paltry 20%.

For most of KLA’s existence it was a more evenly balanced share of revenues between both segments that grew up as the twin pillars of the business. Indeed, reticle inspection was the first product KLA ever produced.

KLA has lost the technology leadership position, ACTINIC inspection, to Lasertec in Japan. Now we have heard that KLA has lost the low end reticle inspection business in China to a Chinese upstart that has only been in business since 2016.

KLA is losing its China reticle inspection business to a company that is competing with a product that costs a small fraction of KLA’s price offering with good enough performance.

We think KLA will have a solution to compete at the high end with a new approach but it will likely take a few years to come to fruition.

On the low end there really is no solution to a lower price, only a walk away from the business which appears to be the case.

So much as the leading edge (TSMC) business market segment is driving the overall business, from a product perspective it is wafer inspection that is carrying the day for KLA.

The Stocks

Much as we saw with Lam, last week, we would expect a bit of a relief rally in KLAC as the quarter was OK and not a disaster.

Growth and expectation of growth remains modest with 2025 a great unknown, and there is still significant downside in potential sanctions on China that are yet to be accounted for but investors seem to be ignoring that and focusing on the fact that it wasn’t a bad quarter.

We would expect KLAC and other equipment stocks to continue to recover, albeit slowly, from the drubbing they all got on the ASML news.

Investors will likely continue to be more cautious this time around on valuations, however, as most have figured out that this is a long, slow recovery, with many potential pitfalls and issues in front of us

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

LRCX- Coulda been worse but wasn’t so relief rally- Flattish is better than down

ASML surprise not a surprise (to us)- Bifurcation- Stocks reset- China headfake

SPIE Monterey- ASML, INTC – High NA Readiness- Bigger Masks/Smaller Features

Podcast EP258: How Pragmatic Semiconductor Opens New Markets with Non-Silicon, Bendable Technology

Podcast EP258: How Pragmatic Semiconductor Opens New Markets with Non-Silicon, Bendable Technology
by Daniel Nenni on 11-01-2024 at 10:00 am

Dan is joined by Dr. Emre Ozer, Senior Director of Processor Development at Pragmatic Semiconductor. With 67 worldwide patents, and over 60 peer-reviewed publications to his name, he has extensive experience in CPU microarchitecture with particular expertise in performance modelling, fault tolerant CPUs, embedded machine learning, application-specific hardware design, and flexible electronics. Emre spent more than 17 years as Senior Principal Research Engineer at Arm.

Emre provides a comprehensive overview of the unique technology of Pragmatic Semiconductor in this informative discussion with Dan. He describes the non-silicon, flexible manufacturing technology offered by the company and covers some of its advantages regarding cost, cycle time and environmental impact.

Emre then describes the company’s recently announced Flex-RV, an ultralow-cost, bendable, 32-bit RISC-V microprocessor that also includes a programmable machine learning (ML) hardware accelerator. Emre describes a broad array of “extreme edge” applications for the device, such as implantable, wearable and ingestible.

Emre also talks about what’s next at Pragmatic Semiconductor in the area of flexible MCUs.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Podcast EP257: IC Mask Design’s Unique Layout Training with Ciaran Whyte – Always Ask Why

Podcast EP257: IC Mask Design’s Unique Layout Training with Ciaran Whyte – Always Ask Why
by Daniel Nenni on 11-01-2024 at 8:00 am

Dan is joined by Ciaran Whyte, one of the founding members of IC Mask Design. As Chief Technical Officer he is responsible for all technical activity and the development and administration of all training courses. Cíaran has been training layout engineers for over 25 years and has completed layout training with over 600 engineers to date.

Self-paced e-learning training courses delivered through an accessible online portal, empowering learners to progress at their own pace

Dan explores with Ciaran some of the unique attributes of the layout training offered by IC Mask Design. Ciaran explains that “how” to perform various layout tasks is important, but it’s also important to understand “why” tasks are performed a certain way. Being curious can have significant benefits.

In this eye-opening discussion, Cirian uses the changes taking place in technology as examples of the power of understanding why things are done a certain way, For example, he focuses on layout rules to minimize latchup. This continues to be an important item in layout today, but the combination of smaller geometries and lower operating voltage can influence the approaches used.

Ciaran points out that you need to ask “why” to fully understand this.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Self-paced e-learning training courses delivered through an accessible online portal, empowering learners to progress at their own pace

November 1, 2024May 15, 2025

CEO Interview: Dr. Adam Carter of OpenLight

CEO Interview: Dr. Adam Carter of OpenLight
by Daniel Nenni on 11-01-2024 at 6:00 am
Categories: CEO Interviews

Previously, Dr. Carter served as Chief Commercial Officer at Foxconn Interconnect and Oclaro. At Oclaro, he served as a member of the senior executive team from July 2014 to December 2018, when it was acquired by Lumentum Holdings for $1.85B. Prior to that, he served as the Senior Director and General Manager of the Transceiver Module Group at Cisco from February 2007 to July 2014, where he was instrumental in the acquisition of Lightwire, a Silicon Photonics start-up, and released the first internally-designed CPAK 100G transceiver family utilizing a Silicon Photonics Optical engine.

Tell us about your company?
Formed in 2022, OpenLight is the world’s first open silicon photonics platform with integrated lasers. We enable our customers to incorporate photonic building blocks into their designs, making it more like a photonic ASIC (Application Specific Integrated Circuits) rather than an optical subassembly. As part of our broader vision and business model, we do not manufacture products, instead, we provide customers access to a Process Design Kit (PDK) that facilitates the creation of photonic integrated circuits. We deliver custom PASIC design and license our intellectual property (IP) to a variety of customers, which currently includes over 350 patents, with our portfolio expected to grow to 400 patents in the near future.

What problems are you solving?
While silicon photonics was once met with skepticism, its benefits particularly in efficiency and scalability are now well recognized. Despite this progress, the industry still faces significant challenges in design, manufacturing, and deployment. Through our recent partnerships with Jabil, VLC Photonics, Spark Photonics, and Epiphany, we are working to create a more resilient and collaborative ecosystem while driving innovation across various market segments and transforming the manufacturing landscape.

What application areas are your strongest?
OpenLight’s platform enables companies to design and manufacture at scale, which is crucial as the industry faces increasing demand in areas like data centers, AI/ML, and high-performance computing (HPC). As data centers rapidly multiply, they have become the largest consumers of silicon photonics, driven by the need to interconnect servers, switches, and routers at ever-increasing bandwidths while minimizing costs and power consumption.

Meanwhile, the rise of AI and ML has transformed data center architectures, shifting traffic patterns primarily between GPU and CPU clusters, significantly increasing the demand for higher bandwidth and lower latency. Our technology enhances the performance, scalability, and manufacturability of critical photonic components, including waveguides, splitters, modulators, and photodetectors. By facilitating heterogeneous laser integration in silicon, OpenLight enables data rates to scale from 10G to 800G and beyond, effectively replacing traditional copper cables.

What keeps your customers up at night?
One of the most common concerns we notice among our customers is the reliability and scalability of manufacturing processes, especially in light of supply chain disruptions that have affected many industries. Additionally, there is always hesitation regarding the return on investment in new technologies. Customers want to ensure that their investments in silicon photonics will yield tangible benefits. We help alleviate their concerns by providing expert guidance throughout the design and manufacturing journey. We not only facilitate the adoption of new photonic components into existing infrastructures, but we also equip our customers to confidently navigate challenges while staying competitive in a rapidly evolving market.

What does the competitive landscape look like and how do you differentiate?
Unlike traditional silicon photonics processes, OpenLight’s business model provides open access to its PDK, allowing any company to utilize its technology. The PDK, featuring validated components, is accessible through Tower Semiconductor’s PH18DA production process, where companies can either design their circuits independently or seek OpenLight’s assistance. This openness contrasts with earlier models where access to silicon photonics was limited, often requiring acquisitions or significant investment in new startups.

OpenLight’s platform is the only platform that enables the integration of active components such as lasers and amplifiers directly into the silicon within a foundry process — that’s our key differentiator. We enable customers to integrate photonic designs into silicon more easily and support the broader development of the photonics industry, which is still in its early stages of maturity.

What new features/technology are you working on?
We are making significant strides in the development of PICs focusing on both existing and future advancements. Currently, we offer two 800-gigabit PIC reference designs: an 8×100-gigabit (800G-DR8) design and an 800-gigabit 2xFR4 CWDM one. Now, we are expanding our portfolio to include an 8×200-gigabit design, targeting a 1.6-terabit DR8 and a corresponding 1.6-terabit CWDM variant. The 1.6Tb will mark the first product to utilize distributed feedback (DFB) lasers as its light source and will incorporate semiconductor optical amplifiers to compensate for higher optical losses at 200 gigabits, ensuring optimal performance and meeting stringent specifications.

How do customers normally engage with your company?
OpenLight has made remarkable strides since its inception, growing from three to seventeen customers, and demonstrating a tenfold increase in revenue. We work with a diverse range of companies and organizations involved in various sectors that require silicon photonics technology.

We provide two primary services to our customers. The first is design assistance. For those who lack expertise in silicon photonics designs, we develop custom silicon photonics chips and manage the production process. Once designed, these chips are sent to Tower Semiconductor for production, and wafer-level testing on chip prototypes is done before delivery. OpenLight provides the Graphic Data Stream (GDS) file to the customer, detailing the mask set required for ordering the production of the photonic integrated circuit (PIC) from Tower.

Through our second service, we serve companies that have in-house photonic expertise but haven’t been able to use processes involving active components such as lasers, semiconductor optical amplifiers (SOAs), and modulators. These components are a part of PDKs, and companies can choose a PDK that fits their specific designs, allowing the foundry to create the devices. We offer two types of PDKs through Tower Semiconductor: one from Synopsys and another from Luceda Photonics. While we do not make any components, we do offer reference designs.

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October 31, 2024November 4, 2024

Adding an AI Assistant to a Hardware Language IDE

Adding an AI Assistant to a Hardware Language IDE
by Tom Anderson on 10-31-2024 at 10:00 am
Categories: AMIQ EDA, EDA

I’ve been working with AMIQ EDA for several years, and have frequently been impressed by new capabilities in their Design and Verification Tools Integrated Development Environment (DVT IDE) family. They just announced AI Assistant, which leverages large language model (LLM) technology. LLMs are much in the news these days, so I interviewed AMIQ EDA R&D Engineer Serban Ionica to learn more about their solution.

What is AI Assistant?

It’s a new feature of our DVT IDE family that helps hardware engineers be even more productive when developing code for the design and verification of complex chips. The knowledge contained in LLMs, when combined with our own insight into the design and testbench, enables users to generate, modify, and understand code more easily.

We’ve all seen tools like ChatGPT generate code; how is this different?

That’s a great question. Like any LLM-based solution, AI Assistant uses all the knowledge accumulated over the years to generate correct code for specific tasks. One reason that our approach is different is that the generation happens in the context of our DVT IDE, which compiles all the design and verification code. It also builds and maintains a project database that the users can query. They can compose requests including information from the compilation database, and the LLM can leverage sections of code or other design and verification artifacts to improve the accuracy of its responses.

How does users know that the generated code is acceptable for their project?

Any code in the IDE, whether entered manually or generated, is incrementally compiled and checked. In addition, our Verissimo SystemVerilog Linter can incrementally check for any violations of project coding guidelines. Users can type something like “create a SystemVerilog 8-input round-robin arbiter” and the generated code will meet all the same requirements as code written by hand.

Is AI Assistant used only for generating new code?

It can also explain or improve existing code. Often an engineer inherits code from other projects and would like to understand what it’s doing. Typing “explain the highlighted code” or “make the highlighted code faster” leverages the knowledge embedded in the LLM in the context of the user project. This significantly increases code development efficiency.

Is it a lot of work to start using the new feature?

We make usage easier with predefined LLM interactions called blueprints. DVT IDE ships with a set of blueprints that can be used out of the box for performing common coding tasks. Blueprints can be used directly in the editor window or in a chat window. Users can define their own library of blueprints based on the fully transparent predefined blueprints as examples. Thus, reusable LLM interactions in the form of blueprints can be shared across the entire project team.

Did you develop your own LLM or include an existing one?

We do not include an LLM. We found that most users have preferences or even company requirements for using specific LLMs. Instead, we tested extensively to be sure that we support popular LLMs from OpenAI, Github Copilot, Google AI, and locally hosted Ollama as well in-house proprietary LLMs. We are open, flexible, and transparent.

How do you handle concerns about leaking proprietary information to cloud-based LLMs?

That’s where transparency comes in. Users can preview all communication with third-party LLMs to ensure that no confidential information or proprietary IP is being transferred. We are well aware of industry concerns that some AI tools seem to be doing things users cannot control or even understand. We ensure that this is not the case for AI Assistant.

Was this new feature a big step for AMIQ EDA?

It certainly was a significant project that took us in some exciting new directions, but it is a natural extension to features we have had in DVT IDE for years. Auto-correct, quick fix suggestions, code templates, and refactoring all involve some amount of code generation. The power of LLMs enables us to take users to the next level of productivity.

Are you underselling the value of your solution?

Make no mistake: AI Assistant is a real-world, sophisticated application of LLMs and AI technology that is valuable today. However, we’re not draping our show booths in huge banners that say things like “THE AI EDA Company” as some vendors do. We want to focus on the value to users and not trumpet AI for its own sake. We also recognize that the nature of LLMs and generative AI (GenAI) means that their results improve over time. This initial release is powerful, but our capabilities will get even broader with lots of hands-on experience. Developing any advanced EDA technology is really a partnership between a vendor and its users.

Finally, is AI Assistant a new product or feature that users must pay for?

It is included at no extra cost in the latest release of both DVT IDE for Visual Studio (VS) Code and DVT Eclipse IDE. We want all our users to be able to take advantage of this new feature and we want to benefit from their usage as we evolve it further.

Thank you for your time, Serban.

You’re most welcome, and thank you for the opportunity to talk.

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