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Agile Analog at the 2025 Design Automation Conference #26DAC

Agile Analog at the 2025 Design Automation Conference #26DAC
by Daniel Nenni on 06-17-2025 at 10:00 am
Categories: Agile Analog, IP

62nd DAC SemiWiki

See Agile Analog at DAC in the EE Times Chiplet Pavilion (Booth 2308, Level 2)

Learn how to enhance security and performance with our customizable analog IP

Agile Analog is delighted to announce that we will be back exhibiting at the Design Automation Conference (DAC). Come join us in the EE Times Chiplet Pavilion (booth 2308) to learn how our innovative, customizable analog IP solutions are addressing the demands of chip design across a vast range of domains.

Visitors will have the opportunity to dive deep into our expanding portfolio of analog IP, covering essential areas including data conversion, power management, IC monitoring, security and always-on IP. We will be explaining how our IP can empower your designs with optimized performance and efficiency, whether you are looking for precision ADCs, efficient LDOs or robust on-chip PVT monitoring capabilities.

Of particular interest is our anti-tamper security IP. In an ever increasingly connected world protecting sensitive data is critical. Our anti-tamper solutions are designed to provide robust, on-chip security against a wide variety of physical and non-physical attacks, including voltage and clock attacks, safeguarding your devices from malicious intrusions. We will be discussing how our anti-tamper IP can seamlessly integrate with existing Root of Trust (RoT) solutions, enhancing their capabilities to help you meet the latest security standards. This integration offers formidable protection, with a multi-layered approach to chip security that is both flexible and powerful.

What truly sets Agile Analog apart is our groundbreaking Composa™ technology. Composa enables us to automatically generate and customize our analog IP for any process node from any foundry. We have proven this methodology across our IP portfolio on nodes from 180nm to 3nm. This means that we can quickly deliver highly optimized IP that precisely matches your exact specifications, whilst ensuring the best possible Power, Performance and Area (PPA) for your application. No more porting or costly and time-consuming analog re-engineering when moving to a new process or foundry. This unparalleled flexibility extends to our anti-tamper IP as well, allowing for tailored security solutions, delivered fast, regardless of your chosen process node.

We invite attendees to stop by to see us in the EE Times Chiplet Pavilion (booth 2308) at DAC. Our experts will be on hand to discuss your specific design challenges and demonstrate how Agile Analog’s customizable multi-process IP, especially our advanced anti-tamper solutions, can help you achieve your design goals and stay ahead in a competitive landscape. We look forward to seeing you there!

To arrange a meeting to talk with the Agile Analog team at DAC please email info@agileanalog.com

Find out more about Agile Analog at www.agileanalog.com

DAC registration is open.

Also Read:

CEO Interview with Krishna Anne of Agile Analog

Overcoming obstacles with mixed-signal and analog design integration

Podcast EP241: A Look at Agile Analog IP with Chris Morrison

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Altair at the 2025 Design Automation Conference #62DAC

Altair at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-17-2025 at 8:00 am
Categories: 3D IC, Altair, Chiplet, EDA, Events

62nd DAC SemiWiki

Design Perfection from Concept to Tape-out Booth #1617 at DAC25 – June 23-25, 2025

Join us to learn how Altair’s world-class solutions are powering perfect semiconductor design.

The semiconductor industry operates at an accelerated pace, in which every second saved is a competitive advantage. You must rely on solutions that complement each other at every step in the semiconductor design process to beat others to market.

Altair’s solutions empower organizations to design perfection from concept to tapeout. From silicon debugging tools for integrated circuit (IC) designs to multiphysics analysis of 3D IC and chiplet design simulations, Altair offers the complete solutions set. With the fastest high-throughput workload manager available and an advanced workflow analysis tool, designers can trust Altair with every challenge.

Speak with an expert at DAC

Book meeting

Live Presentations

Transform the semiconductor industry

Design perfection from the start with advanced silicon debugging, rapid 3D IC electrothermal-mechanical simulations, and the industry’s only on-demand digital simulator for semiconductor electronic functional verification. Avoid costly dependencies and optimize infrastructure utilization with HPC workload and workflow optimization and bring reliable designs to market faster.

Join us for live presentations throughout the conference featuring industry leaders and technology experts.

 

11:30 am – 12:00 pm | Altair SimLab: Integrated Environment for Multiphysics Modeling and AI-Driven Reliability Prediction in 3D IC Systems

Iyad Rayane, Senior Technical Specialist ESD, Altair

This solution provides a comprehensive environment for modeling and pre/post-processing of 3D Integrated Circuit (3D IC) structures, enabling robust multiphysics analysis including thermal, mechanical, and electrical domains. It interfaces with advanced AI-driven physics capabilities to predict system lifespan rapidly and accurately, significantly reducing simulation runtime. Additionally, the environment supports thermal-aware chiplet floorplanning, optimizing thermal dissipation at the system level to enhance reliability and performance. This integrated approach facilitates early design exploration and informed decision-making for next-generation heterogeneous 3D ICs.

01:00 pm – 01:30 pm | Altair NavOps: Bursting Workload demand to the cloud!

Yohan Bouvron, Support Engineer, Enterprise Computing, Altair

Engineers want as little wait time as possible to run their workloads and management wants the highest possible utilization of the systems. Altair’s NavOps + Accelerator can provide an optimal solution for both.

02:00 pm – 02:30 pm | FlowTracer Refresh – A new era of vendor-agnostic design automation platform

Dee Lin, Lead Principal Solution Architect, Altiar

Since its inception, FlowTracer has become a popular commercial ASIC/SoC design automation platform among the top semiconductor companies. This year, Altair is launching 2025 release with major GUI and feature-rich modernization. We will go through these major features and improvements in this presentation.

DAC registration is open.

About Altair

Altair is a global leader in computational intelligence that provides software and cloud solutions in simulation, high-performance computing, data analytics and AI. Altair enables organizations across all industries to compete more effectively and drive smarter decisions in an increasingly connected world – all while creating a greener, more sustainable future. To learn more, please visit https://www.altair.com.

Also Read:

Tuple Technologies at the 2025 Design Automation Conference #62DAC

Perforce at the 2025 Design Automation Conference #62DAC

Silvaco at the 2025 Design Automation Conference #62DAC

Silicon Creations at the 2025 Design Automation Conference #62DAC

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Tuple Technologies at the 2025 Design Automation Conference #62DAC

Tuple Technologies at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-17-2025 at 6:00 am
Categories: Semiconductor Services, Tuple Technologies

62nd DAC SemiWiki

Tuple Technologies delivers Tropos, a platform automating IT infrastructure across Cloud, Hybrid or On-prem and DevSecOps for semiconductor IC, FPGA, and system design, optimizing costs and cybersecurity.

Attendees who step into the Tuple Technologies booth during DAC (Booth #1237) will see demonstrations of its Tropos Platform and launch of a new product, Omni, that empowers Semiconductor design teams to optimize their budgets to run CPU & GPU workloads.

Tuple Technologies has developed a specialized platform called Tropos, designed specifically to address the needs of semiconductor designers working on integrated circuits (IC), field-programmable gate arrays (FPGA), and system design workloads. The Tropos platform is tailored to optimize semiconductor development processes through automation, cost efficiency, and robust infrastructure management. Below are the key features and solutions provided by Tropos for the semiconductor industry:

  1. Infrastructure-as-Code (IaC) for Customized Setup:

    • Tropos uses IaC techniques to provide out-of-the-box infrastructure setups tailored for IC, FPGA, and system development needs. This allows semiconductor startups and designers to quickly establish optimized environments without extensive manual configuration.

  2. Automation for Workload Management:

    • The platform automates the spawning of IC workload jobs to cost-optimized compute resources across major cloud providers like AWS, GCP and Azure. This ensures efficient resource allocation, reducing operational costs while maintaining performance for compute-intensive semiconductor design tasks.

  3. ECAD Administration and License Management:

    • Tropos includes tools for Electronic Computer-Aided Design (ECAD) license administration, streamlining the management of design software critical to semiconductor development. It also provides license usage analytics, helping companies optimize their software licensing costs and avoid vendor lock-in with CAD tools.

  4. Multi-Cloud Cost Optimization:

    • The platform is designed to optimize semiconductor workloads across multiple cloud environments, ensuring cost efficiency by leveraging the most suitable cloud resources for specific tasks. This is particularly valuable for semiconductor companies managing complex, resource-heavy design processes.

  5. Cybersecurity for Semiconductor Workloads:

    • Tropos incorporates cybersecurity measures to protect sensitive semiconductor design data, ensuring compliance and safeguarding intellectual property during development and deployment. This is critical for semiconductor companies handling proprietary designs.

  6. IT Operations and DevSecOps:

    • Tuple provides comprehensive IT operations (ITOps) and DevSecOps solutions tailored for semiconductor startups. These include Cloud, On-prem or Hybrid environments, ensuring seamless integration of development pipelines with secure, automated workflows.

  7. Scalable and Affordable Solutions:

    • Built on an open-source stack, Tropos is designed to be both scalable and cost-effective, making it accessible for small to medium-sized semiconductor companies. The platform automates cloud infrastructure provisioning (Platform-as-a-Service) and management, simplifying the configuration and operation of cloud resources for semiconductor workloads.

Semiwiki readers are invited to arrange demonstrations or private meetings by sending email to info@tupletechnologies.net or stopping by Booth #1237

DAC Registration is Open

About Tuple Technologies

Tuple Technologies, founded in 2017, is a cloud automation and managed services provider headquartered in New York with offices in New Jersey and San Francisco. The company specializes in delivering solutions, with a strong focus on cloud migration, cybersecurity, DevSecOps, and IT operations, particularly for small to medium-sized businesses in industries like Semiconductors. Tuple employs a team of AWS-certified engineers and has products and services offering a suite of tools built on open-source stacks to ensure affordability and scalability.

Tuple Technologies emphasizes its expertise in supporting semiconductor startups by providing infrastructure setups that avoid the complexities and gaps often found in traditional CAD vendor solutions. The company’s participation in industry events like the Design Automation Conference (DAC) in 2025 highlights its commitment to engaging with the semiconductor community and showcasing its Tropos platform.

Also Read:

Silvaco at the 2025 Design Automation Conference #62DAC

Silicon Creations at the 2025 Design Automation Conference #62DAC

Certus Semiconductor at the 2025 Design Automation Conference #62DAC

Easylogic at the 2025 Design Automation Conference #62DAC

AMIQ EDA at the 2025 Design Automation Conference #62DAC

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Perforce at the 2025 Design Automation Conference #62DAC

Perforce at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-16-2025 at 10:00 am
Categories: EDA, Events, Perforce

62nd DAC SemiWiki

Stop by the Perforce booth to learn about our new partnership with Siemens and get a demo of the latest enhancements in Perforce IPLM, P4, and VersIC. We’re eager to hear about your current challenges and how our semiconductor design and data management solutions can ease your design and development hurdles. Plus, you can try your hand at PLINKO to win some new Perforce swag and scan your badge for your chance to win a pair of Bose QuietComfort headphones!

Find Us at Booth #1227 in the First Floor Exhibitor Hall

Schedule a 1:1 Meeting

DAC attendees can skip the line by pre-scheduling a demo or Q&A session with a Perforce expert. To ensure we connect, schedule your meeting now:

Book my DAC session

Two Key Presentations

Vishal Moondhra, Perforce VP of Solutions Engineering, returns for two informative sessions on the future of chip design:

Building Trust in GenAI for Semiconductor Design: Addressing Data Provenance, Quality, and Traceability Challenges

Monday, June 23 | 3:30pm-4pm PDT | Exhibitor Forum, Level 1 Exhibit Hall

Learn how to establish a secure, compliant, and controlled approach to training AI models to ensure model reproducibility, reliability, and accountability. This session will offer solutions to the critical issues of IP provenance and traceability in order to mitigate risks and foster trust in AI adoption. Learn more

Engineering the Semiconductor Digital Thread

Wednesday, June 25 | 12:00pm-12:30pm PDT | Exhibitor Forum, Level 1 Exhibit Hall

Co-presented with Michael Munsey, VP of Semiconductors and Electronics, Siemens Digital Industries Software, this session will explore the concept of the Semiconductor Digital Thread—a holistic, integrated approach to managing the complete semiconductor lifecycle in the era of software-defined design. Learn more

Happy Hour Networking and Celebration

On Tuesday, June 24th  from 3:00pm to 5:00pm, join us for a beer or two to celebrate our new partnership with Siemens. Come by the Perforce booth thirsty for updates and libations. This is a great opportunity to meet our team, make new connections, and get your questions answered.

Additional Resources

For more about Perforce at DAC 62, visit our event page. On our website, you’ll also find webinars, white papers, and other resources to help you learn more about our unified solution for semiconductor design and data management.

DAC registration is open.

Also Read:

Video EP1: A Discussion of Meeting the Challenges to Implement Gen AI in Semiconductor Design with Vishal Moondhra

The Transformation Model for IP-Centric Design

Chiplets and IP and the Trust Problem

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Silvaco at the 2025 Design Automation Conference #62DAC

Silvaco at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-16-2025 at 8:00 am
Categories: EDA, Events, Silvaco

62nd DAC SemiWiki

Please join us at the Design Automation Conference 2025 where we will highlight the company’s wide range of EDA products and semiconductor IP  targeting, Power Devices, Automotive, Memory, Displays, HPC, 5G / 6G, and IoT applications.

When: June 23 – 25, 2025, Exhibit Hours: 10:00 AM PDT – 6:00 PM PDT

Where: Moscone Center West, Booth 2323, San Francisco, CA

Meet with Silvaco experts to learn about our latest developments and technologies in EDA tools for Analog Custom IC design analysis and verification, automated cell library creation and optimization, and our broad portfolio of design IP.

Theater Presentations

​​​​​​Stop by our booth and attend one of our technical presentations to learn more about our products. Everyone who attends one of our presentations will receive a free gift and a raffle ticket. Prizes include Apple AirPods and the JBL Go 4, an ultra-portable, waterproof, and dustproof Bluetooth speaker. Raffles are held twice daily, so don’t miss your chance to win!

AI Takes EDA to the Next Level – Presented by Dr. Walden “Wally” C. Rhines

Additional presentations by Silvaco experts covering:
– Advanced Memory Compiler Solutions for Your Next SoC
– Accelerate Your SPICE Simulator Performance with Jivaro Pro!
​​​- Boost Productivity with Automated Cell Library Creation and Optimization
– Accelerate Debug, Reduce Cycles with Viso
– Achieve Higher Yield with Smarter Variation Analysis

Click Here to View the Presentation

Schedule: https://go.silvaco.com/SilvacoDAC2025

To schedule a meeting with our experts please contact sales@silvaco.com

Silvaco is looking forward to seeing you at DAC 2025 !!

About Silvaco
Silvaco is a provider of TCAD, EDA software, and SIP solutions that enable semiconductor design and AI through software and innovation. Silvaco’s solutions are used for process and device development across display, power devices, automotive, memory, high performance compute, foundries, photonics, internet of things, and 5G/6G mobile markets for complex SoC design. Silvaco is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Brazil, China, Japan, Korea, Singapore, and Taiwan.

DAC registration is open.

Also Read:

TCAD for 3D Silicon Simulation

CEO Interview: Dr. Babak Taheri of Silvaco

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Silicon Creations at the 2025 Design Automation Conference #62DAC

Silicon Creations at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-16-2025 at 6:00 am
Categories: Events, IP, Silicon Creations

62nd DAC SemiWiki

Silicon Creations provides world-class IP for precision and general-purpose timing (PLLs and oscillators), high-performance multi-protocol and protocol-specific SerDes, high-speed I/Os, and accurate PVT sensors. Applications include high performance computing for AI, smart phones, wearables, consumer devices, network devices, automotive, IoT, and medical devices.

Majority of the world’s top 50 IC companies work with Silicon Creations. Nearly 2,000 chip designs contain the company’s IP, drawn from a portfolio of over 700 unique IP products. The company supports more than 150 production tape-outs annually and has worked with over 500 customers globally. Its IP is in mass production down to 3nm, with N2 IP already taped out on several customer chips.

This year, Silicon Creations is celebrating another banner year of customer SoCs heading to mass production. In 2024 alone, the company’s IP was deployed on 171 tape-outs, helping to produce nearly 1.8 million wafers in collaboration with TSMC, the world’s largest dedicated semiconductor foundry. Silicon Creations continues to expand its advanced portfolio to support GAAFET processes across TSMC, Intel, Samsung, and Rapidus.

Visit Silicon Creations at DAC 2025 Booth #2425

This year at DAC, Silicon Creations will highlight:

  • Innovative temperature sensor IP available in TSMC 3nm and 2nm, with expansion to other nodes underway
  • PCIe SerDes solution
  • Die-to-die PLLs for UCIe PHYs from 2nm and up
  • Reference clock generator PLLs for 112/224G Ethernet and PCIe5/6/7 PHYs
  • All-digital loop control, jitter-optimized LC PLL, now available from 2nm (Samsung) and 3nm (TSMC, Intel) up to 22nm (GF)

Be sure to stop by booth #2425 to see the latest demos and pick up a Silicon Creations wafer coaster. To schedule a private demo or meeting at DAC, reach out here.

You can explore the full lineup of Silicon Creations’ high-performance IP here.

About Silicon Creations

Silicon Creations is a self-funded, leading silicon IP developer with offices in the US and Poland, and sales representation worldwide. The company provides world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), oscillators, low-power, high-performance SerDes and high-speed differential I/Os for diverse applications including smart phones, wearables, consumer devices, processors, network devices, automotive, IoT, and medical devices. Silicon Creations’ IP is proven and/or in high-volume mass production in process technologies up to the most advanced available in the industry.

DAC registration is open.

Also Read:

Silicon Creations Presents Architectures and IP for SoC Clocking

2025 Outlook with Randy Caplan of Silicon Creations

One Thousand Production Licenses Means Silicon Creations PLL IP is Everywhere

Silicon Creations is Fueling Next Generation Chips

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Certus Semiconductor at the 2025 Design Automation Conference #62DAC

Certus Semiconductor at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-15-2025 at 10:00 am
Categories: Certus Semiconductor, Events, IP, TSMC

62nd DAC SemiWiki

Certus Semiconductor Brings High-Performance Custom I/O and ESD IP to DAC 2025

Certus Semiconductor, a trusted leader in custom I/O and ESD solutions, will exhibit at booth #1731 during DAC 2025, June 23–27 in San Francisco. Known for its robust, customer-proven IP tailored for challenging applications, Certus will highlight its extensive portfolio of high-speed, multi-voltage, and specialty I/O libraries that deliver seamless integration and outstanding protection across advanced nodes.

With over 16 years of experience, Certus specializes in developing custom I/O and ESD solutions for a wide range of high-performance interfaces—WiFi, Cellular, HDMI, LVDS, USB, XAUI, and up to 256Gb SerDes—while supporting harsh environments like automotive, industrial, and aerospace.

Certus recently joined the TSMC Open Innovation Platform® (OIP) IP Alliance, enabling the company to apply its custom I/O and ESD technology to TSMC’s advanced process nodes and deliver optimized, foundry-aligned IP to a broader base of SoC developers.

At DAC 2025, Certus will demonstrate how its IP portfolio supports:

  • Multi-protocol and multi-voltage I/O libraries for simplified integration across a wide voltage and protocol range
  • Combo GPIOs supporting interfaces like I²C/I³C/SPI/LVCMOS/HSTL/SSTL/eMMC
  • High-voltage and ultra-high-voltage (10V, 20V+) ESD protection on low-voltage CMOS for analog, RF, and MEMS applications
  • Custom die-to-die and high-speed SerDes I/O solutions with industry-leading low capacitance and robust ESD performance
  • Radiation-hardened and automotive-grade solutions across process nodes from 180nm down to 12nm

Certus’s IP is designed for performance, reliability, and ease of use—backed by expert technical support and a deep understanding of customer integration needs. Whether you’re working on ultra-low-power sensor interfaces or high-speed SoC interconnects, Certus offers IP that’s built to meet your design challenges head-on.

Visit Certus at DAC 2025 (booth #1731) to see how their cutting-edge custom I/O and ESD solutions can streamline your next chip design.

Learn more at www.certus-semi.com

DAC registration is open.

Also Read:

EP177: The Certus Approach to Meeting the Challenges of I/O and ESD with Stephen Fairbanks

The Opportunity Costs of using foundry I/O vs. high-performance custom I/O Libraries

CEO Interview: Stephen Fairbanks of Certus Semiconductor

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Easylogic at the 2025 Design Automation Conference #62DAC

Easylogic at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-15-2025 at 8:00 am
Categories: Easy-Logic, EDA, Events

Easylogic DAC 2025

EasylogicECO Provides Built-In Stage-Based Functional ECO Flows to Reduce Turnaround Time

HONG KONG — June 6, 2025 — EasyLogic proudly introduces a groundbreaking stage-based ECO design environment, built into the EasylogicECO tool, to meet the rapidly evolving functional ECO (Engineering Change Order) demands of today’s ASIC design industry.

These stage-based flows simplify functional ECO operations through built-in modules that address both functionality changes and alignment with the user’s ASIC design flow.  With the inclusion of these new features, EasylogicECO has demonstrated a reduction in ECO turnaround time by more than 50% compared to traditional approaches.

Dr. Sean Wei, CEO of EasyLogic Technology, emphasizes the importance of this new offering: “In any functional ECO scenario, designers face a layered challenge. First comes the complexity of implementing logic changes. Then, each design stage—synthesis, DFT, floorplanning, and place-and-route—requires its own variation of the ECO logic. Finally, every change must be verified before the flow can advance. These challenges accumulate quickly, threatening both the schedule and silicon quality.

By offering flexibility, speed, and deep flow integration, EasylogicECO turns ECO into a manageable, streamlined part of the ASIC design lifecycle — empowering teams to respond quickly to change without compromising quality or design intent.”

Figure 1: An example of the layered challenge in an ECO operation

With a stage-aware architecture designed to align with the user’s ASIC design process, EasylogicECO provides five built-in functional ECO flows, each designed to mirror a common ASIC flow scenario. Each stage in the ECO flow consists of an operation module with embedded functionality and configurable switches, and all modules in the same design flow are tightly integrated. This allows users to further control their ECO results based on specific application needs.

Figure 2: Stage-based ECO design modules built-in into EasylogicECO

From an application perspective, each built-in flow reflects a typical ASIC design flow scenario.  Examples include:

  • 1-stage ECO flow (Blue): Ideal for small digital circuitry, such as mixed-signal ASIC designs.  This flow supports fast-turnaround environments where ECO requests occur frequently but remain localized, and ECO windows are short.
  • 2-stage ECO flow (Green): Designed for streamlined handoffs between traditional front-end and back-end design teams, where the front-end covers RTL design, synthesis, and DFT phases.
  • 2-stage ECO flow (Yellow): This second variant of the two-stage flow supports designs that require an RTL handoff to the implementation team during the design process.
  • 3-stage ECO flow (Orange): Perfect for very large-scale digital ASICs, such as mobile application processors or network switches.  This flow targets a well-defined ECO process involving separate RTL design and DFT teams, as well as back-end implementation.  Result verification is performed at the synthesis and DFT stages before committing back-end changes to minimize risk.
  • 4-stage ECO flow (Purple): Tailored for ultra-large ASIC designs such as GPUs or AI server chips, this flow excels in environments where the chip comprises many replicated or hierarchical blocks. It includes a floorplanning step to adjust the patch logic before place and route (P&R) using physical guidance — particularly when the distance between blocks impacts patch timing.

EasyLogic will showcase its new functional ECO environment at DAC 2025, taking place June 22–25 in San Francisco (Booth # 2521). Visitors are encouraged to schedule detailed discussions in advance to explore how EasylogicECO can be seamlessly integrated into their design environments.  To get in touch, please use our Contact Us form at https://www.easylogiceda.com/en/contact.html.

DAC registration is open.

Also Read:

ECO Demo Update from Easy-Logic

CEO Interview: Dr. Sean Wei of Easy-Logic

 

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AMIQ EDA at the 2025 Design Automation Conference #62DAC

AMIQ EDA at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-15-2025 at 6:00 am
Categories: AMIQ EDA, EDA, Events

62nd DAC SemiWiki

AMIQ EDA is a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis. We’ve been attending DAC for many years now, and it remains one of our most important shows. We love catching up with old friends in the industry, and we always meet lots of engineers who are potential users. We also stay a few extra days before or after the event to meet with our current users at their offices.

DAC is also a great opportunity for us to show off all the new features we’ve added to our products since the last show. This year there’s a lot for us to discuss and demonstrate. The biggest addition to our Design and Verification Tools (DVT) IDE family is AI Assistant. As we discussed in an interview a few months back, this new feature leverages the knowledge in a large language model (LLM) and in our own design and testbench database to make it easier for users to generate, modify, and understand code.

We do have a chat option, but this is way more than a generic chatbot. Our database is specific to the user project and company, so we can use that information to yield better responses. Users can ask AI Assistant to explain or improve code, and to generate new code for desired functionality. All code can be checked for accuracy by the IDE and our Verissimo SystemVerilog Linter. We support whatever LLM the user chooses, and we take multiple steps to ensure that confidential project information does not leak to third-party LLMs.

We support the two major IDE platforms, and we’ve aligned DVT Eclipse IDE and DVT IDE for Visual Studio (VS) Code even closer in terms of functionality. We’ve added more than 30 new code checks within the IDE to ensure code quality. Beyond those big items, we’ve improved testbench elaboration time, expanded debug capabilities, and enhanced our support for power intent files. Although we’ve been shipping DVT IDE since 2008, there’s no shortage of new ideas from our users and our developers. It just gets even better every year.

Speaking of Verissimo, we also add features to our linter all the time. We include around 60 new rules each year, and we’ll be showing the 2024-2025 additions at DAC. We’ve also enabled fast incremental linting, since users want lint checks in addition to IDE checks whenever they add or edit code. They can check their code as they write it without having to open separate windows or jump back and forth. Finally, we’ve added an intuitive ruleset editor to make it easy to customize which rules to run when, including during incremental linting.

Our Specador documentation generator has some new improvements as well. We’ve integrated it more closely with DVT IDE, including the ability to preview the HTML page for a design or verification element interactively. AI Assistant can generate descriptions for user code, and Specador builds high-quality documents including those descriptions. We focus on this type of connection between our products, in addition to adding new features.  We want our users to have the best overall experience possible to produce better code more quickly and easily.

DAC will move to Long Beach next year, so this is a good opportunity to visit San Franscisco. We invite you to stop by our booth to say hello, ask questions, see a demo, or whatever you’d like. We look forward to seeing you there!

Contact AMIQ EDA

DAC registration is open.

Also Read:

2025 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA

Adding an AI Assistant to a Hardware Language IDE

Writing Better Code More Quickly with an IDE and Linting

Podcast EP291: The Journey From One Micron to Edge AI at One Nanometer with Ceva’s Moshe Sheier

Podcast EP291: The Journey From One Micron to Edge AI at One Nanometer with Ceva’s Moshe Sheier
by Daniel Nenni on 06-13-2025 at 10:00 am

Dan is joined by Moshe Sheier, Ceva’s vice president of marketing. Moshe brings with him more than 20 years of experience in the semiconductor IP and chip industries in both development and managerial roles. Prior to this position, Mr. Sheier was the director of strategic marketing at Ceva.

Dan explores the history of Ceva with Moshe and how that history has created a strong force in the industry. Moshe describes the many markets and application areas that Ceva supports for edge computing, including DSP, audio, radar, vision and motion in the sensing area and inference with its scalable NPU architecture. This flexible and scalable architecture allows Ceva to support many customers in the implementation of efficient workloads from low power to safety critical.

Moshe describes the experience Ceva has developed over 10 years with its scalable NPU development, delivering consistent performance and efficiency improvements while also ensuring its hardware and software are future-proof. Its self-contained hardware architecture and broadly adopted software allow Ceva to deliver end-to-end solutions across many markets and customers.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.