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CEO Interview with Brandon Lucia of Efficient Computer

CEO Interview with Brandon Lucia of Efficient Computer
by Daniel Nenni on 11-28-2025 at 2:00 pm

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Brandon Lucia is the CEO and co-founder of Efficient Computer, the company building the world’s most energy-efficient general-purpose processors, and a Full Professor in the department of electrical and computer engineering at Carnegie Mellon University. He is an extensively published author, and his research has appeared in top publications such as IEEE Micro, Computer, Proceedings of the ACM on Programming Languages, and IEEE Computer Architecture Letters.

Brandon earned his Ph.D. in Computer Science and Engineering from the University of Washington in 2013. He received the NSF CAREER Award in 2017, the IEEE TCCA Young Computer Architect Award in 2019, and the Sloan Foundation Fellowship in 2021.

Tell us about your company.

After a decade of research at Carnegie Mellon University, a team of world-leading computer architects, frustrated with the pervasiveness of deeply inefficient computer systems, founded Efficient Computer in 2022 to solve computing’s energy problem. Led by CEO Brandon Lucia, Chief Architect Nathan Beckmann, CTO Graham Gobieski, and founded with SmartThings founder and now BrightAI CEO Alex Hawkinson, the group sought to commercialize key breakthroughs in efficient computation and reshape computing from the ground up, with a focus on extreme energy efficiency.

Today, Efficient Computer has built and launched the world’s most energy-efficient general-purpose processor, Electron E1, and the intuitive, developer-friendly software stack that unlocks orders of magnitude in efficiency gains for entire, complex applications, replacing inefficient legacy architectures and over-specialized accelerator chips with a new efficiency-first design that enables far-reaching innovation through its general-purpose programmability.

With Efficient’s cutting-edge effcc Compiler and software stack, Efficient’s fundamentally new spatial dataflow architecture delivers extreme efficiency to solve computing’s energy challenges across a wide range of scales: the tiniest far-edge systems, high-performance edge devices, and even the datacenter; and for a wide range of application use cases: physical AI, infrastructure observability and industrial automation, robotics and automotive use cases, wearable AR vision systems, satellites, defense, and many more.

Efficient’s patented architecture is an unprecedented alternative to catastrophically inefficient, legacy, “von Neumann” computer architectures. von Neumann architectures are inherently sequential and mired by decades of entrenched design choices and intellectual inertia that have neglected efficiency, while adhering to the status quo. Efficient’s novel spatial dataflow architecture is a clean-slate redesign that offers efficiency, generality, and performance, through hardware/software co-design that achieves an extremely high degree of parallelism, without compromising on the familiar software interface that generations of programmers and infrastructure expect.

What problems are you solving?

Today’s processors waste most of their energy — often more than 99% of the energy for each CPU instruction — moving data around, fetching and decoding instructions, and configuring circuits to ready them for the next operation, which then consumes a vanishingly small fraction of the total energy to perform.For decades, Moore’s Law masked these inefficiencies by delivering steady gains in energy efficiency. But as transistor scaling has slowed, those architectural inefficiencies have become the hard limit on progress. Attempts to reduce power have either specialized away general-purpose programmability or shifted the inefficiency elsewhere in the system.

Efficient was founded to solve this root problem of architectural inefficiency, and to spend a majority of energy on a computation’s actual operations. The careful co-design of Efficient’s Fabric spatial dataflow architecture eliminates the energy overheads inherent in legacy designs. Instructions in Efficient’s Fabric architecture are spatially distributed, avoiding frequent fetch and decode costs, and eliminating costly cycle-by-cycle circuit reconfiguration. A data value produced by one operation flows through a highly efficient on-chip network directly from the output of one instruction to the input of the instructions that consume that data value. The benefits of these key differences in the architecture are unlocked by Efficient’s compiler and software stack, which ingests standard, general-purpose code and readies it for efficient execution on the Fabric. By dramatically reducing the energy required for general-purpose computation, including AI, our approach enables applications that were previously not possible, due to thermal dissipation, power delivery, battery lifetime, or limited performance under a power cap.

With Efficient’s architecture, an application designer has the freedom to spend their energy dividends any way they like. One customer may translate efficiency into longer battery life, another may incorporate more capability at a given power level, and another may opt for a smaller battery form factor at lower cost. The result is a new category of computational use cases and applications — defined by the possibilities created through unprecedented efficiency, not by the limitations of ever-tightening power budgets.

What application areas are your strongest?

Efficient’s Fabric architecture scales from the smallest edge devices to large-scale performance-intensive applications, providing extreme efficiency across the spectrum. Electron E1 is an implementation of Efficient’s Fabric architecture designed for the edge — where efficiency, performance are crucial, and where a wide range of different computational tasks intersect. Electron E1 is especially strong in applications such as physical AI for infrastructure observability and industrial automation, robotics and near-actuator control, automotive sensors, next-gen AR/VR wearables, and space & defense use cases. Electron E1 enables systems to process complex, multimodal data like vision, audio, and vibration directly on-device. These are the kinds of challenges our Electron product line is built to address.

And while the Electron product line targets the edge, our underlying Fabric architecture scales seamlessly — from ultra-low-power devices all the way to the datacenter — bringing the same efficiency and flexibility to every level of computing. Across these domains and scales, Efficient enables developers to spend their energy savings where it matters most: more capability for less power, lower cost, longer lifetime, and all without sacrificing the key advantage of general-purpose programmability.

What keeps your customers up at night?

Up until now, customers have had to make painful trade-offs when designing products — sacrificing features, performance, or intelligence just to meet battery, size, or cost constraints. Take the infrastructure observability space: they’re building devices that must process complex data and make decisions on the spot, often in harsh, disconnected, and power-limited environments. These devices need to deliver real-time intelligence where it’s needed most, without being limited by energy, size, or cost.

Today, many are forced to rely on the cloud for processing — sending massive amounts of sensor data over unreliable networks, constant communication to which drains batteries in just days or weeks. This “data backhaul” strategy is a non-starter for long-lived infrastructure observability applications, making true autonomy in these use cases impossible. There is an urgent need, instead, to efficiently support on-device computation, avoiding the need for data backhauling, but still extracting benefits from valuable sensor data.

Considering legacy compute solutions for these use cases leads to unsatisfying and constant compromise: every milliwatt, millisecond, and square millimeter matters, and designers must forfeit performance for lifetime, degrade intelligence due to inefficiency, and often remain cloud dependent. Efficient eliminates these unsatisfying trade-offs. By making energy efficiency fundamental to general-purpose computing, we give customers the freedom to design for what matters most — capability, autonomy, longevity, form factor, or scale — without compromise.

What new features/technology are you working on?

This year, we launched our first silicon product, the Electron E1 general-purpose processor, which has already been delivered to our early-access customers. We are now ramping toward large-scale volume and broad distribution in 2026, when Electron E1 will be generally available.

Electron E1 leverages the Efficient Fabric architecture, eliminating the energy overhead caused by moving data between memory and compute cores in traditional von Neumann systems. We are seeing strong customer traction in areas such as physical AI for infrastructure and automation, space and defense, automotive, and consumer products. Recently, we celebrated the first real-world deployment of the Electron E1 with physical AI leader, BrightAI. With the E1, BrightAI’s platform can perform the majority of its processing directly at the edge, avoiding the high energy cost of offloading data to the cloud for compute-intensive tasks such as signal processing and AI.

How do customers normally engage with your company?

One of the ways customers typically engage with us is through our Early Access Silicon Program, which provides a pathway to evaluate and integrate our technology. Through this program, customers receive access to our development platforms, documentation, and tools, along with hands-on support from our engineering team. We help them benchmark their applications and provide guidance on how to optimize performance, ensuring they get the most out of our hardware. Early engagements often focus on prototyping and testing, while ongoing collaboration supports larger deployments and integration into production environments.

Also Read:

CEO Interview with Dr. Peng Zou of PowerLattice

CEO Interview with Roy Barnes of TPC

CEO Interview with Mr. Shoichi Teshiba of Macnica ATD


Podcast EP319: What Makes Agile Analog a Unique Company with Chris Morrison

Podcast EP319: What Makes Agile Analog a Unique Company with Chris Morrison
by Daniel Nenni on 11-28-2025 at 10:00 am

Daniel is joined by Chris Morrison, vice president of product marketing at Agile Analog, the customizable analog IP company. Chris has over 18 years’ experience developing strong relationships with key partners across the semiconductor industry and delivering innovative analog, digital, power management and audio products. Previously, he has worked for international companies including Dialog Semiconductor.

Dan explores Agile Analog’s unique custom analog focus with Chris, who describes the company’s agileSecure product line. Tamper prevention and tamper detection are both discussed, along with the benefits of the company’s unique temperature sensor. Chris also discusses significant collaboration in the security space with high-profile companies. Future collaboration as well as new product introduction across a broad array of applications including security and data conversion are also covered.

Contact Agile Analog

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


TSMC Formally Sues Ex-SVP Over Alleged Transfer of Trade Secrets to Intel

TSMC Formally Sues Ex-SVP Over Alleged Transfer of Trade Secrets to Intel
by Daniel Nenni on 11-28-2025 at 6:00 am

TSMC vs Wei Jen Lo

The big semiconductor news this week is the legal action TSMC is taking against former Senior Vice President Wei-Jen Lo. This looks to be a serious game of 3D chess between CC Wei and Lip-Bu Tan so it is worth a look. I got this notice in my inbox early Tuesday morning:

Immediately following, there was an interesting discussion on SemiWiki. Since this story is still unfolding I thought it would be worth while to take a closer look and share perspectives.

Wei-Jen Lo immigrated to the US from Taiwan and earned his PhD in Solid State Physics & Surface Chemistry from U.C. Berkeley in 1979.  He joined TSMC in 2004 after 18 years at Intel in positions including Director of Technology Development and as a Factory Manager running a development facility in Santa Clara, CA.

Joining TSMC after Intel was not uncommon back then. Intel and TSMC did not compete directly and that is how Silicon Valley worked. We changed jobs in pursuit of equity so Wei-Jen Lo only working for two different companies in 40 years is quite remarkable. It also goes to the depth of knowledge he had at both companies.

Here is the TSMC hiring announcement from 2004:

Approved the appointment of Dr. Wei-Jen Lo as Vice President of TSMC Operations II. Both Dr. Wei-Jen Lo and Dr. Mark Liu, who is also a Vice President of TSMC Operations II, report directly to Dr. Rick Tsai, President and Chief Operating Officer for TSMC. Dr. Wei-Jen Lo recently joined TSMC from Intel Corporation where he held various positions in technology development and management. Prior to joining Intel, Dr. Lo served in the IT and semiconductor industries, and he also held teaching and research position in the university in the US.

TSMC and many other semiconductor companies have hired former Intel employees. In fact, you will be hard pressed to find a company that did not have Intel experience inside so this is nothing new. In fact, Dr. Mark Liu also worked for Intel prior to joining TSMC and later became CEO and Chairman of the Board.

The problem as I see it is two-fold:

Wei-Jen Lo told TSMC he was retiring which provided a completely different exit than if he had said he would go to work for a competitor. For example, it was reported that Wei-Jen Lo was allowed to take 20 boxes of hand written notes he had complied over the last 20 years while working at TSMC. That would not have happened if it was known that he was going to work for Intel.

The second problem is that Intel did not publicly announce Wei-Jen Lo’s arrival  which is normally done for the executive staff. This supports the argument of deception. Wei-Jen is said to be a Senior VP at Intel reporting directly to Lip-Bu Tan. He will work in Intel’s manufacturing group and its packaging business which directly competes with TSMC.

On Wednesday morning Lip-Bu Tan sent a message to Intel employees defending the hiring:

“Based on everything we know today, we see no merit to the allegations involving Wei-Jen, and he continues to have our full support. Intel has welcomed back Wei-Jen Lo, who previously spent 18 years at Intel working on the development of Intel’s wafer processing technology before joining TSMC, where he continued his work in their wafer processing technology development.”

On Thursday it was reported that Taiwan prosecutors had raided the homes of the former senior TSMC executive and seized computers after the company accused him of leaking trade secrets. This is both a criminal and civil investigation.

This big question is why?

Wei-Jen Lo is 75 years old and has had a remarkable career working for two semiconductor giants that changed the world. His legacy is one semiconductor professionals like myself honor greatly. Wei-Jen has also worked for some of the most decorated people in the semiconductor industry including Andy Grove, Craig Barrett, Morris Chang, and CC Wei.

Additionally, Wei-Jin Lo owns significant TSMC stock. I found a source that said as of February 28, 2025, Lo held 1,282,328 shares, valued at about US$63 million. Could that be true? And now he risks losing it as a result of a lawsuit? Not to mention the shame of betraying Taiwan’s most valued company? Seriously, why would he do this?

Bottom Line: Hopefully this story has a happy ending. TSMC is still an important supplier to Intel and this will be yet another test of leadership for Lip-Bu Tan. Lip-Bu needs to get in front of this situation before it does irreparable harm to Intel, absolutely.

Also Read:

TSMC Kumamoto: Pioneering Japan’s Semiconductor Revival

Exploring TSMC’s OIP Ecosystem Benefits

TSMC’s Push for Energy-Efficient AI: Innovations in Logic and Packaging


WEBINAR: Revolutionizing Electrical Verification in IC Design

WEBINAR: Revolutionizing Electrical Verification in IC Design
by Daniel Nenni on 11-27-2025 at 10:00 am

Electrical Verification – The invisible bottleneck in IC design 2

In the complex world of IC design, electrical verification has emerged as a critical yet often overlooked bottleneck. Aniah’s upcoming webinar on December 4, 2025, titled “Electrical Verification: The Invisible Bottleneck in IC Design,” sheds light on this issue, introducing their groundbreaking OneCheck® solution. As IC designs grow exponentially per Moore’s Law, schematic size and complexity surges, making electrical errors inevitable. Traditional Electrical Rule Checking (ERC) struggles to keep pace, leading to a widening verification gap. The Wilson Research Group’s 2024 highlights that 86% of IC/ASIC designs require respins due to design flaws, costing millions in re-spins, mask sets, and delayed time-to-market. Late-stage bugs not only waste resources but also risk missing market windows, eroding competitive advantage.

Electrical Rule Checking (ERC) fundamentals involve ensuring designs comply with electrical constraints like connectivity, voltage compatibility, current limits, and biasing. It detects issues such as floating nodes, short-circuits, power-ground errors, and device overstress, validating electrical integrity pre-tape-out to boost reliability and yield. However, traditional methods fall short amid rising transistor counts, design complexity and stagnant verification resources, particularly in headcount for ERC engineers.

Aniah’s OneCheck® represents a paradigm shift: the first static transistor-level ERC tool for “right-on-first-silicon” ICs. Designed for adoption, users benefit from the automated PDK & power setup, fast run time, and advanced cross-probing with Cadence Virtuoso. Independent of foundry tech-files, it empowers designers and CAD teams with unprecedented error coverage, drastically reducing false positives – up to 150x in some cases via propagation path analysis and system-conditional checks. For mature and advanced nodes, it handles billion-transistor designs in minutes.

Breakthrough features include full-chip analysis, across all possible power combinations for a 100% reliable error detection. OneCheck® uniquely identifies errors like conditional HiZ, missing level shifters, bulk/diode leakages, floating gates/bulks/diodes, electrical overstress, and ESD gate-to-supply issues. Its pseudo-DC engine enumerates all DC states for formal proofing, verifying complex isolation on-the-fly and rejecting impossible conditions to minimize noise.

Integrated natively with Cadence Virtuoso, OneCheck® fits early in the flow from post-schematic netlist to full-chip bridging analog, digital, and mixed-signal domains. Users praise its simplicity: “Aniah lets designers achieve excellent design quality with minimum effort”. It “starts at check-and-save, converging to 100% quality by sign-off,” as noted by design managers and verification engineers.

Bottom line: By focusing on root causes, grouping thousands of errors into a limited number of root causes, OneCheck® accelerates debugging, enhances productivity, and cuts costs. Aniah emphasizes 100% error coverage and first-in-class support. In an industry where delays mean millions, adopting OneCheck® ensures zero electrical errors on first silicon spin, fostering confidence from design to tape-out.

Also Read:

Aniah and Electrical Rule Checking (ERC) #61DAC

Electrical Rule Checking and Exhaustive Classification of Errors

CEO Interview: Vincent Bligny of Aniah


Live Webinar: Considerations When Architecting Your Next SoC: NoC with Arteris and Aion Silicon

Live Webinar: Considerations When Architecting Your Next SoC: NoC with Arteris and Aion Silicon
by Daniel Nenni on 11-27-2025 at 8:00 am

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The explosive growth of AI and accelerated computing is placing unprecedented demands on system-on-chip (SoC) design. Modern AI workloads require extremely high bandwidth, ultra-low latency, and energy-efficient data movement across increasingly heterogeneous architectures. As SoCs scale to incorporate clusters of CPUs, GPUs, NPUs, memory subsystems, and domain-specific accelerators, the Network-on-Chip (NoC) becomes the backbone that determines system performance, power efficiency, and overall scalability. This presentation, featuring Arteris and Aion Silicon, explores the key considerations for architecting next-generation NoCs optimized for AI-driven designs.

WATCH REPLAY

We begin with a deep look at AI communication patterns. Unlike traditional compute pipelines, AI workloads exhibit bursty, data-parallel behavior, with strong dependencies between compute engines and shared memory resources. Understanding tensor flow, on-chip bandwidth hotspots, and memory reuse patterns is essential for mapping compute, memory, and accelerator elements onto the SoC floorplan. This analysis directly influences NoC topology, routing strategies, QoS configuration, and buffer sizing.

NoC construction strategies form the core of the discussion. Tree, mesh, and hybrid topologies are evaluated not in isolation but through the lens of physical awareness—how real-world floorplans, die size, and chip aspect ratios dictate the most practical choices. AI-oriented SoCs often employ tiling strategies that replicate compute-memory clusters across the die. The NoC must scale with this modularity while maintaining predictable performance across thousands of concurrent data flows. The tradeoffs between bandwidth, power efficiency, and area become especially acute at advanced nodes, making architectural decisions increasingly consequential.

Another major theme is system complexity. Multi-die integration, enabled by 2.5D and 3D packaging, introduces new layers of NoC design challenges. Cross-die communication must handle longer physical paths, varying thermal conditions, and partitioned power domains. Distributed AI processing elevates the need for robust memory-coherency models—balancing performance with the overhead of maintaining shared state across heterogeneous compute engines. Designers must also account for dynamic voltage and frequency scaling (DVFS), power gating, and isolation across multiple domains, all of which impact NoC behavior.

To manage this complexity, performance simulation and KPI-driven evaluation are essential. The session discusses practical methodologies for modeling throughput, latency, congestion, and power consumption using a combination of transaction-level simulation, trace-based modeling, and workload-driven analysis. These tools allow architects to quantify tradeoffs early, before committing to RTL or physical implementation, ensuring the NoC meets system performance targets.

Finally, the presentation highlights the strategic role of NoC partitioning and restructuring. As designs approach physical limits, achieving timing closure becomes increasingly challenging. Partitioning the NoC into hierarchical or modular segments can simplify routing, reduce wire length, and improve predictability, especially in large AI-focused SoCs.

WATCH REPLAY

With insights from Andy Nightingale, VP of Product Management and Marketing at Arteris, and Piyush Singh, Principal Digital SoC Architect at Aion Silicon, attendees will gain a practical, experience-driven perspective on designing scalable, high-performance NoCs. Their combined expertise—spanning system IP, NoC products, performance modeling, and complex heterogeneous SoC architecture—provides a grounded framework for building the next generation of AI-optimized silicon.

Also Read:

Architecting Your Next SoC: Join the Live Discussion on Tradeoffs, IP, and Ecosystem Realities

The Sondrel transformation to Aion SIlicon!

2025 Outlook with Oliver Jones of Sondrel


From Silos to Systems, From Data to Insight: Keysight’s Upcoming Webinar on EDA Data Transformation

From Silos to Systems, From Data to Insight: Keysight’s Upcoming Webinar on EDA Data Transformation
by Daniel Nenni on 11-27-2025 at 6:00 am

Keysight EDA Webinar

In the fast-evolving world of electronic design automation (EDA), where complexity multiplies with every nanometer shrink and AI integration, data silos are the silent killers of innovation. Keysight Technologies, a leader in design and test solutions, tackles this head-on with their webinar “From Silos to Systems, From Data to Insight” (AM Session), scheduled for December 17, 2025, at 10:00 AM PST. This free, one-hour virtual event promises to equip engineering leaders with actionable strategies to dismantle fragmented data ecosystems and unlock AI-driven efficiencies. With over a decade of expertise guiding the charge, presenter Pedro Pires—Product Manager at Keysight—brings his Master’s in Microelectronics Engineering and passion for MLOps to the forefront.

REGISTER NOW

Targeted at Engineering Directors, VPs of R&D, EDA Managers, CAD Professionals, Design and Verification Leads, IT/Data Governance Executives, and AI/ML Engineers, the webinar addresses a universal pain point: disconnected design data that hampers collaboration, traceability, and reuse. In today’s global R&D landscapes, teams grapple with multi-site workflows, compliance demands, and the explosion of IP blocks—issues that Pires notes amplify “the biggest challenges today… managing complexity, ensuring governance, and preparing data for AI.” Keysight’s solution? Their SOS Enterprise Collaboration platform, positioned as the “backbone for modern engineering enterprises.”

The agenda is laser-focused on transformation. Attendees will explore transitioning from isolated silos—think scattered design files, inconsistent metadata, and siloed tools—to a unified, governed platform that fosters seamless collaboration. Pires will delve into how structured, traceable data becomes the fuel for analytics, machine learning, and AI copilots, slashing rework and accelerating design cycles. Imagine verification engineers spotting anomalies in real-time or data scientists training models on clean, enriched datasets without the drudgery of manual reconciliation. Keysight SOS shines here, offering hybrid deployment for secure, scalable operations across borders, complete with audit-ready governance and AI-ready infrastructure.

What sets this apart are the tangible benefits. Organizations adopting such systems report up to 30% faster time-to-market, reduced IP reuse errors, and empowered cross-domain visibility—critical in an era where AI agents could automate 40% of routine design tasks, per industry forecasts. Pires, drawing from his work connecting Keysight’s global teams, will share practical roadmaps: identifying shadow data in legacy tools, implementing metadata standards, and integrating with EDA suites like Cadence or Synopsys for end-to-end traceability. A standout feature is the platform’s emphasis on “agentic workflows,” where AI not only analyzes but anticipates design bottlenecks, turning raw data into predictive insights.

Beyond the session, Keysight sweetens the deal with an EM session for European audiences on the same day, ensuring global accessibility. Registration is straightforward—simply visit the event page and fill out the form (JavaScript required)—with recordings promised for those who can’t attend live. As Pires emphasizes, “That’s exactly why Keysight SOS becomes critical.” This webinar isn’t just a talk; it’s a catalyst for engineering teams to evolve from reactive data hoarders to proactive insight machines.

REGISTER NOW

In a semiconductor industry racing toward 2nm nodes and beyond, ignoring silos risks obsolescence. Join Keysight on December 17 to bridge the gap from chaos to clarity, and position your organization at the vanguard of AI-accelerated design. The future of EDA isn’t in more data—it’s in making it work together.

Also Read:

An Insight into Building Quantum Computers

Podcast EP317: A Broad Overview of Design Data Management with Keysight’s Pedro Pires

Video EP11: Meeting the Challenges of Superconducting Quantum System Design with Mohamed Hassan


Modern Trends in I/O and ESD Design at TSMC OIP

Modern Trends in I/O and ESD Design at TSMC OIP
by Daniel Nenni on 11-26-2025 at 10:00 am

Introduction to Certus Semiconductor IP

It was very clear at the recent 2025 TSMC OIP Ecosystem Forum that the semiconductor I/O landscape has undergone a profound transformation over the past 25 years, evolving from simple general-purpose input/output (GPIO) cells in 180nm nodes to highly complex, multi-protocol, feature-rich libraries in advanced 16nm and 22nm processes. As Stephen Fairbanks, CEO of Certus Semiconductor, outlines in his presentation, modern I/O design is no longer about basic functionality—it is about adaptability, optimization, and market-specific performance.

Historically, a single foundation I/O library per process node sufficed, offering variants of classic GPIO (push-pull LVCMOS) or open-drain I/O (ODIO) for protocols like I2C or SMBus. These were adequate for early 2000s applications in telecom and consumer electronics. Today, explosive growth in mobile computing, IoT, AI at the edge, automotive infotainment, and autonomous systems demands far greater flexibility. A single ASIC may now serve both automotive (requiring CAN) and cellular (needing I3C) markets without dedicated pins. This convergence has birthed the GPODIO, a hybrid I/O capable of operating in both CMOS and open-drain modes, supporting LVCMOS, SPI, I3C, JTAG, and fail-safe open-drain standards.

The GPODIO exemplifies multi-protocol I/O, a cornerstone of modern design. It features configurable output drivers that switch between high-speed GPIO (Tfall < 5ns, Zout 33–120 Ω) and slow-slew open-drain modes (Tfall 20–1000ns, IOL 3–20mA). Input mode control (IMC) supports multiple VIH/VIL/hysteresis thresholds, while fail-safe operation ensures reliability even with push-pull drivers and on-die terminations. Voltage support has also expanded: modern GPIOs handle VDDIO from 1.2V to 3.3V, core supplies down to 0.65V, and external ODIO voltages up to 5V—all in one cell.

Even more advanced are “Super” I/Os, macro cells combining two single-ended or one differential pair, supporting over 20 standards including LVDS, MIPI, HSTL/SSTL with on-die termination (ODT), and POD. These are essential for high-performance computing (HPC) and 5G infrastructure.

Another major trend is I/O library variants. A single GPIO design in 22nm might spawn five libraries—PM22 (ultra-low power IoT, 0.14nA leakage), MM22 (balanced mobile), OG22 (automotive-grade, 8kV HBM), and EG22/TG22 (HPC with staggered footprints for density). Each optimizes speed, leakage, ESD (2kV to 16kV HBM, 6A to 16A CDM), and interface support (SPI, RGMII, eMMC). Foundry catalogs now offer multiple libraries per node, differentiated by metal stack, voltage, and market focus. Product architects must align library selection with application goals—using a low-power IoT library for HPC would compromise performance.

Analog and RF I/O have also matured. Where once designers built custom pads, modern libraries include pre-characterized cells: low-capacitance RF pads (<75fF, >8kV HBM), matched LVDS/HDMI pairs, and high-voltage analog I/Os up to 20V. This reduces design risk and time-to-market.

Emerging die-to-die interfaces for 2.5D/3D packaging and chiplets introduce ultra-low-power, high-density I/Os (e.g., 4Gbps in 16nm, <0.1nA DC, 10×20µm footprint), critical for multi-die AI and memory stacks.

Verification complexity has skyrocketed. A classic GPIO required ~135 PVT corners; a modern multi-voltage, multi-mode GPODIO demands over 12,000 corners, including zero-volt and power-down modes. Accurate .LIB modeling is now a major engineering challenge.

Bottom line: I/O design has shifted from monolithic, one-size-fits-all libraries to a sophisticated ecosystem of optimized, configurable, and market-tailored solutions. The days of defaulting to the “base” foundry library are gone. Success in 2025 requires deep understanding of application requirements, careful library selection, and robust verification—ensuring performance, power, reliability, and cost align with diverse, demanding end markets.

Certus Semiconductor, with over 30 process node I/O libraries and expertise in ESD, RF, and multi-protocol design, stands at the forefront of this evolution.

Contact Certus for more information

Also Read:

Certus Semiconductor at the 2025 Design Automation Conference #62DAC

The 2024 Design Automation Conference and Certus Semiconductor

2024 Outlook with Stephen Fairbanks of Certus Semiconductor


Podcast EP318: An Overview of Axelera AI’s Newest Chip with Fabrizio Del Maffeo

Podcast EP318: An Overview of Axelera AI’s Newest Chip with Fabrizio Del Maffeo
by Daniel Nenni on 11-26-2025 at 8:00 am

Daniel is joined by Fabrizio Del Maffeo, CEO and co-founder of Axelera AI, a Netherlands-based startup delivering the world’s most powerful and advanced solutions for AI at the edge.

Fabrizio describes the significant momentum Axelera AI has achieved in the market, with over 350 customers. Dan then explores the company’s newest product, Europa with Fabrizio. He discusses the 3-5X performance increase delivered by this new product, along with its cost and power benefits. Fabrizio sees this chip opening new markets and new capabilities for AI and the edge. He believes Europa will have a significant impact in the market

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


Agentic Bug Localization. Innovation in Verification

Agentic Bug Localization. Innovation in Verification
by Bernard Murphy on 11-26-2025 at 6:00 am

Innovation New

Bug localization continues to be a challenge for both bug triage and root-cause analysis. Agentic approaches suggest a way forward. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is LocAgent- Graph-Guided LLM Agents for Code Localization. The authors are from Yale, USC, Stanford and All-Hands AI. The paper was posted in April 2025 and has 25 citations so far.

It’s been a while since we last looked at localization. Agentic activity around debug, growing more popular, prompts another look. The paper’s method is based on building a graph view of a code base, where nodes are functions, found in other objects (classes, files, directories) and edges are relations between nodes like contain, invoke, import, inherit.

One point I find interesting is that this is a purely static analysis of the codebase supported by training against (GitHub) bug and resolution reports. There is no attempt that I saw to probe dynamic behavior to test hypotheses. The authors claim high levels of accuracy at file, module and function levels.

Paul’s view

We look again this month at LLM-based code localization – finding the relevant file/class/function to fix a bug or make an enhancement. Much of the focus for ongoing research, both in academia and industry, is on the retrieval part of the prompt engineering process, where additional information is added to the prompt to help the LLM perform its localization task.

This month’s paper out of Stanford, Yale, and USC, presents a retrieval system, LocAgent, based on a knowledge graph that is essentially the union of file/directory hierarchy on disk (contain, import edges) and class/function relationships based on the elaborated syntax tree for the code (call, inherit edges). Traversing edges in this graph can traverse files and directories as well as function call paths in the code.

The authors also contribute a new benchmark suite for code localization, LocBench. This suite is based on code changes to Python repositories in Github dated October 2024 or later, which is after the training date for all the LLMs benchmarked in the paper. It also has a balance of code changes between bug fixes, new feature requests, and performance issues (around 240, 150, and 140 cases respectively).

The authors benchmark LocAgent vs. other leading code localizers using LocBench, measuring each localizer’s ability to report the correct set of files/modules/functions. Using Claude-3.5-Sonnet, and compared OpenHands, the best alternate tool benchmarked, LocBench scores 6% higher in its ability to report the correct files in its top-10, and about 2% better at reporting the correct methods and functions in its top-10. A solid contribution in probably one of the most actively researched topics in agentic AI today. It’s worth noting however that the absolute top 10 score on function localization is around 60% which is still low, so huge room still for improvement.

As a final contribution, the authors also present a fine-tuned mini-LLM (7B parameter Qwen model) based on around 800 training cases taken from GitHub prior to October 2024 and show that this works reasonably well with LocAgent on LocBench, with about 8% lower top-10 scores. Its inference cost is 15x lower than using Claude-3.5-Sonnet (5 cents vs. 79 cents). An interesting datapoint on cost-outcome trade-off.

Raúl’s view

Where in a code base do you fix a bug, add a feature or address security or performance improvements? This month’s paper proposes LOCAGENT, a framework for code localization — the task of identifying the precise files, classes, or functions in a codebase that need to be modified for a fix. LOCAGENT combines 1) A unified graph representation of an entire code structure and dependencies with four node types (directory, file, class and function) and four relation types (contain, import, invoke and inherit). It is lightweight (takes seconds to build), enables powerful multi-hop reasoning, unifies content search with structural traversal, and is explicitly optimized for LLM consumption. 2) Only three highly optimized tools for search and traversal (SearchEntity, TraverseGraph and RetrieveEntity). 3) Fine-tuned open-source LLMs (Qwen-2.5-Coder 7B and 32B) for localization.

The authors claim that existing benchmarks have two key problems: potential training contamination (LLMs may have seen these repos/issues during pretraining), and overfocus on bug reports, lacking coverage of feature requests, security issues, and performance problems. So, they created a new benchmark, LOC-BENCH collected from modern post-2024 repos to avoid contamination, which includes 560 issues across 4 categories (bugs, features, performance, security), curated to ensure issues require realistic localization. The authors also use SWE-Bench-Lite (300 cases) which was created primarily to evaluate end-to-end bug-fixing capabilities (localization being only an intermediate step) to evaluate their approach.

The experimental evaluation of LOCAGENT includes several dimensions, below my attempt to summarize them:

  • Using fine-tuned open source LLMs (Qwen 2.5) achieves performance comparable to Claude-3.5 at ~86% lower cost.
  • LOCAGENT is correct @ one of the top 1 to 10 predictions in locating file, module and function between 72-94%, outperforming all other methods: embedding-based 40-85%, procedure-based 55-80% and agent-based 46-90%.
  • Cost efficiency is evaluated only against agent-based methods (best of the rest), and LOCAGENT using Qwen beats the best (Moatless using Claude) by .09$ to .46$ for accuracy @ 10 predictions.
  • Evaluating the tools using LOC-BENCH shows LOCAGENT being superior to other agent-based methods by small margins (5-10%, with the exception being security enhancements up to 20%).

Code localization is an important but underemphasized task relative to bug fixing or code generation. The paper convincingly argues that localization is distinct from retrieval, more complex and often the bottleneck in program repair. The approach using a heterogeneous graph, agent tools and fine-tuned LLMs is somewhat novel and empirically effective. LOC-BENCH is well motivated and the breath of empirical analysis and the results are strong. Evaluation is limited to Python, no evidence is provided on non-Python languages, and general applicability is asserted but not demonstrated. Some baselines (SWE-Agent, OpenHands) are not primarily localization systems, so comparisons may overstate LOCAGENT’s advantages.

This is a strong paper with contributions to code localization and agentic software engineering. It is technically sound, well-evaluated, and practically useful. The combination of a unified dependency graph, carefully designed agent tools, and efficient fine-tuning forms an approach that advances the state of the art.

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Why chip design needs industrial-grade EDA AI

Why chip design needs industrial-grade EDA AI
by Admin on 11-25-2025 at 10:00 am

EDA AI consumer vs industrial 72dpi

By Niranjan Sitapure

Artificial intelligence (AI) is reshaping industries worldwide. Consumer-grade AI solutions are getting significant attention in the media for their creativity, speed, and accessibility—from ChatGPT and Meta’s AI app to Gemini for image creation, Sora for video, Sona for music, and Perplexity for web search.

However, adapting these impressive models for high-stakes engineering applications, such as semiconductor chip design, manufacturing, and robotics, is much more complex. In these fields, model results that are incorrect, fabricated (hallucinations), or inconsistent are unacceptable. In consumer AI, a mistake might lead to a funny answer. In chip design, it can cost millions during tapeout and manufacturing. That’s why the EDA industry needs a more industrial-grade AI approach.

Consumer-grade AI versus industrial-grade AI

To understand this challenge, let’s first define the key characteristics of consumer-grade AI and see how they differ from the requirements for industrial-grade AI.

Consumer-grade AI is often optimized for:

  • Creativity: Prioritizing the generation of novel ideas, text, and imagery, even when the results are not perfectly factual or precise.
  • Mobile support: Emphasizing access and ease of use on smartphones and other portable devices.
  • User-specificity and personalization: Adapting its style, recommendations, and memory to an individual’s personal history and stated preferences.
  • Shareability: Integrating tools to quickly post, link, or export generated content to social media or messaging platforms.
  • Voice mode: Enabling hands-free operation through spoken commands and audio responses for maximum convenience.

These principles are fundamentally different from the characteristics required for industrial-grade AI, which are based on the following:

  • Accuracy: Ensuring all outputs are quantitatively correct and conform to strict physical laws and engineering constraints, where even a tiny error can be critical.
  • Verifiability: Providing transparent, traceable decision-making paths so engineers can audit precisely how and why the AI arrived at a specific result.
  • Robustness: Maintaining high performance, reliability, and consistency even when faced with novel, noisy, or incomplete data sets.
  • Generalizability: Successfully applying insights and models trained in one design problem to new, unseen engineering problems.
  • Usability: Seamless integration with established computer-aided design (CAD) and computer-aided engineering (CAE) software tools and engineering workflows, rather than functioning as a separate, standalone app, while also not requiring extensive training for the engineers to utilize these AI solutions.
Figure 1. Consumer-grade AI is different in important ways from industrial-grade AI.

AI for the high stakes of chip design

Now that we understand the key differences between the two paradigms, let’s explore why industrial-grade AI is necessary for the electronic design automation (EDA) tools that power chip design.

Firstly, accuracy is paramount. Every step in the chip design process, from the initial schematic to the final tapeout, demands absolute precision. A single error could substantially harm chip production or critical industrial processes, resulting in significant financial and operational losses in wasted manufacturing costs, complete chip failure, or costly product recalls. That’s high stakes risk the industry simply must avoid.

Secondly, robustness and reproducibility are critical. Today’s general-purpose LLMs are probabilistic models, meaning they may not guarantee the exact same output every time. This variability is problematic for engineering. If a general-purpose LLM is used for a precise task such as RTL generation or high-level synthesis (HLS), it might struggle to achieve complete reproducibility. This could make it difficult to replicate a specific design block or apply the same IP block consistently in a new chip design, creating significant challenges for verification and manufacturing.

Thirdly, verifiability and traceability are essential. Engineers can’t rely on a “black box” that just gives an answer. They need to understand how the AI made its decisions. For example, during placement and routing, an AI might analyze thousands of potential layouts. A verifiable system would log into these different options and the trade-offs associated with them. This allows the chip designer to trace back and see why one layout achieved better power, performance and area (PPA) than another, enabling them to trust and validate the final design.

Examples of AI in EDA

A clear example of these industrial-grade principles in action is seen in Siemens’ Solido Design Environment software. It uses Adaptive and Additive AI technologies to validate designs and IPs through Monte Carlo simulations for mixed-signal designs and custom ICs. This provides orders-of-magnitude speedup for complex tasks, such as variation-aware analysis. These technologies use local machine learning models to predict the results of intensive SPICE simulations from a few initial full-fidelity runs. However, it doesn’t just guess blindly. It constantly checks its own predictions against a confidence threshold, providing SPICE-accurate results. If a prediction falls outside this safe margin, the system automatically reverts to running a full-fidelity SPICE simulation to ensure correctness. This clever hybrid approach perfectly demonstrates the industrial-grade principles:

  • It is accurate because it guarantees all results fall within the user-specified threshold.
  • It is verifiable because it self-checks every single prediction for accuracy.
  • It is robust because this trusted method can be reliably reused across different simulation conditions.

Another example is the recently launched Aprisa AI solution. AI design explorer, a major technology in Aprisa AI, uses machine learning and reinforcement learning algorithms to assist at all major stages of digital implementation and optimize workflows for optimal PPA results. Aprisa AI explores different flows within a targeted design space at each stage, taking into consideration the type of design and the designer’s chosen metrics. Aprisa AI makes decisions automatically on which paths to continue forward to the next stages of exploration, until it arrives to a full flow, and does so utilizing compute core resources more efficiently. While the agent can be launched and automatically make all the decisions to arrive at the best flow solution, Aprisa AI provides verifiability and flexibility to the designers. All databases at each stage are saved for user inspection and interaction with the data and logs. Aprisa AI design explorer also provides a dashboard with all the results of the explorations, allowing the designer to view all the metrics and examine why one approach might have a better PPA than another. Again, as in the above example, the principles of verifiability, robustness, ease of use, and generalizability remain true.

Leading the AI transformation of chip design

This journey for EDA AI is about more than just adopting consumer-grade AI; it is about adopting solutions that are accurate, robust, verifiable, usable, and generalizable. At Siemens EDA, we are committed to driving this transformation into chip design by developing solutions that engineers, managers, and executives can rely on for their most critical semiconductor designs. We believe the future of chip design won’t be built on generic chatbots, but by trusted, explainable, and industrial-grade AI partners fully integrated into every step of the semiconductor workflow. You can learn more about Siemens’ AI efforts here: EDA AI System | Siemens Software

About the author

Niranjan Sitapure, PhD, is the Central AI Product Manager at Siemens EDA. He oversees road mapping, development, strategic AI initiatives, and product marketing for the Siemens EDA AI portfolio. With a PhD in Engineering from Texas A&M University, Niranjan has honed his expertise in advanced AI/ML technologies, including time-series transformers, LLMs, and digital twins for engineering application. He can be reached at Niranjan.sitapure@siemens.com or on LinkedIn.

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