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Full Spectrum Transient Noise: A must have sign-off analysis for silicon success

Full Spectrum Transient Noise: A must have sign-off analysis for silicon success
by Scott Guyton on 01-29-2025 at 10:00 am
Categories: EDA, Siemens EDA

Figure 1

Noise minimization is required for advanced analog and radiofrequency (RF) circuits. Unlike digital circuits, where noise is a second-order effect, system performance metrics such as signal-to-noise ratio (SNR), phase noise, timing jitter, and bit error rate (BER) are directly affected in analog and RF designs. Effective design optimization in the presence of random device noise is challenging because the noise sources are inherent in the circuit elements and cannot be eliminated. Since device noise determines the fundamental limits of circuit functionality, it plays a significant role in analog/RF circuit development.

Noise related issues become particularly critical in circuits with noise-sensitive architectures, tight specifications, and implementation in nanometer CMOS processes with low voltage levels and high frequencies. Most common complex blocks, including analog-to-digital converters (ADC), phase locked loop (PLL), delay locked loop (DLL), transmit chains, receive chains, SerDes, and CMOS image sensors, are highly susceptible to noise.

Measuring and verifying random device noise performance for these circuits can be achieved through a verification hierarchy, starting from smaller building blocks (such as switches, filters) with simple and fast linear noise analysis, to moderate-sized blocks (such as voltage controlled oscillator (VCO), amplifiers, integrators, clocked comparators) using more complex RF noise analysis and sometimes transient noise, and finally, complex blocks (such as ADCs, PLLs, Transmitter, Receiver) using transient noise analysis and in some cases RF noise analysis.

This article will focus on the benefits of full-spectrum transient noise analysis as a must-have for sign-off verification. Full-spectrum transient noise analysis enables engineers to achieve silicon correlation for varied circuit types. It has shown excellent correlation over generations of nanometer process nodes within 1-2 dB of silicon measurements for integer-N PLLs, fractional-N PLLs, and delta-sigma ADCs. In addition, engineers will benefit from the ability to confirm accurate full-spectrum transient noise with proven RF noise analyses (e.g., phase noise of a VCO or input referred noise for a StrongArm Latch).

What is device noise?

Noise in semiconductor circuits is generally divided into deterministic and random sources. Deterministic noise is systematic, bounded, and predictable, while random noise is stochastic, unbounded, and not predictable. Device noise is random and can be categorized into two subtypes: white noise and flicker noise.

White noise

White noise is a random signal with a flat spectral density. The primary sources of white noise are thermal noise and shot noise. The main white noise source in analog/RF CMOS circuits is the MOS device channel thermal noise. Thermal noise results from voltage fluctuations caused by the Brownian motion of electrons in a resistive medium. Thermal noise is found in both passive and active devices. It is broadband white noise that intensifies as temperature increases. Thermal noise has a Gaussian amplitude distribution in the time domain, and its power is evenly distributed across the frequency spectrum. Thermal noise dominates in many applications. Shot noise derives from the discrete quantum nature of electron flow through a potential barrier.

Flicker Noise

Flicker noise, also known as 1/f noise, is caused by traps in semiconductors where carriers that would normally constitute DC current flow are captured for some time and then released. Flicker noise process correlation times are exceptionally long, which makes the power spectral density of flicker noise proportional to 1/f.

What is transient noise analysis?

Transient noise analysis simulates a circuit’s response to random device noise (white and/or flicker). It models transistor noise as current sources with random values based on the noise intensity information from the device model (see Figure 1). Since it is statistical based, the accuracy of transient noise analysis is a function of the number of random samples simulated, i.e., the simulation interval.

Figure 1: Random device noise in resistors and MOSFETs
What is full-spectrum transient noise analysis?

Full-spectrum transient noise directly solves the stochastic differential equations to generate random noise sources at each time step, uses standard device model parameters for white and flicker noise, changes the noise intensity with instantaneous bias, and shows excellent correlation with other noise methods (linear noise, periodic noise, sampled periodic noise, etc.) on a wide range of circuits (such as VCOs, switched-capacitor circuits, clocked comparators, dividers).

Comparison of transient and transient noise signals

Transient analysis is a ubiquitous verification method for a broad range of circuit types, including digital, memories, analog, image sensors, and RF circuits. It is also utilized for measuring deterministic noise, such as power supply-induced noise. However, transient does not include device noise. To account for device noise, we must run transient noise.

The difference between a transient and a transient noise simulation can be dramatic and significant to a design’s overall performance. Both PLLs and ADCs have metrics to compare noise performance. For ADCs it is signal-to-noise ratio (SNR) and for PLLs it is either Phase Noise or timing jitter. Refer to figures 2 and 3 below to note the drastic difference between transient and transient noise.

The ADC Power Spectral Density (PSD) shown in Figure 2 is a 4th order Delta-sigma ADC measuring the SNR, a common metric for noise performance. There is a ~38 dB difference between the transient and transient noise SNR.

Figure 2: 4th order Delta-sigma Analog-to-Digital Converter (ADC) – transient vs transient noise

The PLL phase noise shown in in Figure 3 is from an Integer-N Phased Locked Loop (PLL) with the VCO operating at 10 GHz and used in a wireline transceiver.  There is a 10 dB difference between the transient and transient noise Phase Noise.

Figure 3: Transient vs transient noise of 10 GHz Integer-N PLL
Proper methods to setting up and running transient noise

To achieve accurate noise results running transient noise, it is imperative to properly set the SPICE accuracy, noise parameters (noisefmin, noisefmax), stop time, and apply proper post-processing methods. It is not within the scope of this article to go through a detailed explanation of all the parameters, option settings and post-processing steps. The example below (see Figure 4) shows the steps to setup, simulate, and measure PLL Period Jitter to give you a sense of what the process entails.

Figure 4: Example process from setting up to simulating to post-processing for jitter measurement
Why we need to consider confidence intervals when measuring transient noise results

You will notice a label “PhaseNoise_CI” in Figure 3. This stands for the Phase Noise Confidence Interval. The confidence interval measures uncertainty around the phase noise measurement (-139.34 dBc/Hz) at 100  MHz. While running transient noise, we measure a stochastic or random process. Because of this, we cannot simply measure an output such as signal-to-noise ratio (SNR) or phase noise as a single value and report the results, since it does not include the uncertainty of the measurement. As with Monte Carlo simulations, which deal with random process variations, we must also include a confidence interval and confidence level to give us an idea of the uncertainty of the measurement. The confidence interval or uncertainty can be reduced by varying the noise seed in parallel runs.

Below is a table showing an incorrect reporting of measurements for a PLL and ADC. Note that the correct reporting includes uncertainty.

Building confidence in your transient noise results

Transient noise is broadly adopted for various circuit blocks, architectures, and process technologies. However, for the unfamiliar, although it may seem a reasonable approach,  designers may be uncomfortable or uncertain of its accuracy and methodology. Several whitepapers and presentations show Siemens Analog FastSPICE (AFS) Transient noise correlation to silicon measurements for both PLLs and ADCs over many generations of process nodes, including FinFET process. This is the most convincing approach.

However, as an alternate approach, comparing different and trusted analysis methods (such as linear noise, PNoise, Sampled PNoise, HBNoise) to transient is a viable approach to build confidence in the results.

Using a common Integer-N PLL we can compare various analysis methods and see if they match. This is a useful circuit as we know the VCO dominates the phase noise at higher offset frequencies above the PLL bandwidth. Because of this, we can measure the phase noise for the following

  • VCO Phase Noise – running PSS large signal and PNoise small signal analysis, HB large signal /HBNOISE small signal analysis, and transient noise analysis. PSS refers to periodic steady state, also known as Shooting Newton. HB refers to industry recognized Harmonic Balance.
  • PLL Phase Noise – running transient noise for the closed loop PLL

In figure 5, below we can see all three methods of calculating phase noise for the VCO match very closely. In addition, the closed loop PLL phase noise also matches well with the three phase noise measurements of the VCO. This type of comparison can be achieved for many circuit types including switched-capacitor circuits, clocked comparators, and many others.

Figure 5: Matching phase noise for a closed loop PLL, and VCO
Siemens advances full-spectrum transient noise analysis to its third generation with  SolidoTM Simulation Suite

The foundations and first generation of silicon accurate full-spectrum transient noise analysis were developed by Berkeley Design Automation (BDA) and enabled by directly solving the stochastic differential equations for noise, resulting in silicon correlation for ADCs and PLLs within 1-2 dB.  Because of its high performance, capacity, and accuracy, it was selected as the sign-off solution for many leading semiconductor companies. This trend continued for smaller geometries down to 40nm in the planar FET nodes. Below 40nm, there was a disruption where the design complexity increased due to more sophisticated FET models, increased parasitics, lower voltages, and higher frequencies. However, upon entering the FinFET era (< 16nm), the complexity of the designs increased by 10x-100x as FinFET models were much more complex for analog simulators. It was no longer feasible to run pre-layout and estimated post-layout designs, resistance, and capacitance (RCC) extractions were required, which resulted in simulation runtimes 10x-20x longer for similar designs.

This trend forced a second generation of full-spectrum transient noise with the release of Analog FastSPICE eXTreme (AFS XT) in 2020. This technology addressed the new demands on circuit designers by maintaining accuracy with up to 10x performance boost over the original AFS implementation.

With the acceleration of process technology now pushing 2nm designs, FET models using Gate-All-Around are more complex, metal resistance has increased over 10x compared to 40nm, and simulation runtime increased by 20x. This has forced another step function to innovate and address designers’ needs for performance, capacity, while maintaining noise accuracy for the smallest geometries. Siemens advanced to its next and 3rd generation of full spectrum transient noise technology with Solido SPICE, part of the Solido Simulation Suite that was launched at Design Automation Conference 2024. Solido SPICE is Siemens’ next-generation, feature-rich SPICE simulation technology, providing a 2-30x speedup for analog, mixed-signal, RF and 3D IC verification. With newer convergence, cache efficient algorithms and high multi-core scalability, Solido SPICE provides a significant performance boost for large pre- or post-layout designs. RF IC developers can directly benefit from Solido SPICE’s new RF verification capabilities, while multi-die, 2.5D, 3D and memory interface developers can now experience an efficient capability for full channel transceiver verification that includes equalization, drastically reducing interface assumptions and accelerating verification.

Refer press release – Siemens introduces Solido Simulation Suite | Siemens Software

Summary

This article discusses the significance of full-spectrum transient noise analysis in the design of advanced analog and RF circuits, emphasizing its necessity for achieving silicon success. An introduction of noise in analog and RF circuits set the foundation for understanding device noise and how it is captured when running transient noise. Methods were shown to compare transient noise results to various RF methods achieving excellent correlation. We concluded with the progression through three generations of full-spectrum transient noise, ending in the most advanced implementation available in the Siemens’ Solido Simulation Suite.

Authors:

Scott Guyton – Director of Solutions Architecture, Custom IC Division

Pradeep Thiagarajan – Director of Product Management, Custom IC Division

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PSS and UVM Work Together for System-Level Verification

PSS and UVM Work Together for System-Level Verification
by Bernard Murphy on 01-29-2025 at 6:00 am
Categories: EDA, Siemens EDA

System level testing min

In the early days of the PSS rollout, some verification engineers were suspicious. Just as they were beginning to get comfortable with UVM, here came yet another standard to add to their learning and complexity overhead. Then the fog started to clear; UVM is ideal for block-level testing whereas PSS is ideal for system level testing. And the “P” in PSS is critical. UVM tests are portable into PSS test frameworks as are C tests running on a processor. All that effort put into developing detailed high coverage tests at the block level pays off also at the system level. Of course there should be some interoperability planning between the three test frameworks (PSS, UVM, C) but that was always the intent behind the standard. Siemens EDA have just released a white paper explaining how they recommend such a collaboration.

System-level test scenarios

Why can’t this all be handled in UVM with suitable sequences and randomization? Because what you need to test is simply too high-level and distributed to capture meaningfully in block-centric UVM sequences. Consider for example a multi-core processor cluster supported by coherent cache. Each processor is handling some task, and each is reading from and writing to memory through the cache. Which in turn must ensure a read access to any given logical address must return a consistent current value for that address, even if there is a pending (write) update to the same address from another processor.

Point being that behavior to be tested is distributed across multiple processors, caches (L1s and L2 for example) and a coherent NoC, already a complex state space. And when you build tests for such a system, you must account for factors which are meaningful in this sort of test: checking compliance with the expected coherence protocol (eg MOESI), handling write-through, accumulating stats for cache misses, detecting false sharing and so on. All very feasible in PSS but accommodating this would break your brain in UVM. Then randomization must randomize appropriate scenarios of read and write activity from the cores and cacheline states. While trying to break the protocol and memory consistency by stressing reads from/close to logical addresses for which writes are recent or pending.

There are many other system-level testing requirements: checking IO coherency, power management, interrupt handling, and more. All require modeling and randomizing synthetic or semi-real test scenarios running across distributed functions in a subsystem or system.

Folding in UVM and C

PSS is perfect for building and randomizing scenarios at this level, but these still must be connected to DUT-level testbench components. PSS orchestrates running detailed testing through connections to UVM virtual sequences or high-level C models, allowing you to easily coordinate between UVM and C components and to switch to alternate representations where appropriate as the design evolves. It can also help with testing on hybrid platforms, mixing software simulation, emulation and prototyping.

The white paper illustrates the application of their proposed approach with a couple of examples. The first shows a test methodology to verify writing and reading control/status registers in a block under control of a C routine running on a CPU, observing the interaction of register updates/read from the CPU with block functionality. This would be useful in testing development of a driver for example.

The second example outlines how you might build a VIP to test a DMA. While the previous case can also benefit from PSS randomization, this DMA example is a particularly obvious example of the advantages of a PSS approach. Activity between peripherals, memory and CPUs is unpredictable so randomization is especially important to explore traffic options and potential for collisions, starvation, etc. and to determine whether mechanism to mitigate such problems work effectively.

Nice paper. You can get access to the white paper HERE.

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Heterogeneous 2D/3D Packaging Challenges

Averting Hacks of PCIe® Transport using CMA/SPDM and Advanced Cryptographic Techniques

Reset Domain Crossing (RDC) Challenges

 

 

 

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Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?

Will 50% of New High Performance Computing (HPC) Chip Designs be Multi-Die in 2025?
by Kalar Rajendiran on 01-28-2025 at 6:00 am
Categories: 3D IC, Chiplet, EDA, IP, Synopsys
2 Comments

Synopsys Predictions for Multi Die Designs in 2025

Predictions in technology adoption often hinge on a delicate balance between technical feasibility and market dynamics. While business considerations play a pivotal role, the technical category reasons for the success or failure of a prediction are more tangible and often easier to identify—if scrutinized with care. However, over-exuberance and a tendency to overlook these technical realities frequently lead to inaccurate forecasts.

Abhijeet Chakraborty, Vice President of Engineering at Synopsys gave a keynote talk at the Chiplet Summit 2025. His presentation titled “Accelerating AI Chip Development with 3D Multi-Die Designs” closed with a Synopsys prediction of 50% of new chip designs in the HPC market being multi-die by the end of 2025.

A situational analysis may help us get comfortable with that prediction and why the present moment is uniquely suited for widespread adoption of multi-die design implementations. I chatted with Shekhar Kapoor, Executive Director, Product Management at Synopsys to gain additional insights for this purpose.

The Hurdles of Multi-Die Solutions in the Past

Multi-die solutions have long promised improved performance, efficiency, and scalability over monolithic chip designs, but their adoption was historically constrained by technical and economic challenges. Immature interconnect technologies lacked the high bandwidth and low latency needed for seamless communication, while thermal management struggled with heat dissipation from closely packed high-performance components. Power delivery was another hurdle, as stable, efficient supply systems for diverse die requirements were underdeveloped. Additionally, rising interconnect densities led to signal integrity and electromagnetic interference (EMI) issues.

Standardized chiplet interfaces were absent, limiting design flexibility and cross-vendor compatibility. Economically, advanced packaging methods like interposers and 3D stacking were costly and lacked scalable supply chains. Moreover, testing and validation complexities added to development costs and time-to-market delays.

How the Hurdles Have Evolved

Advancements in technology and industry collaboration have resolved many barriers to multi-die solutions. High-speed interconnects like through-silicon vias (TSVs) and silicon interposers now enable efficient, low-latency communication, while open standards like UCIe enhance interoperability across vendors.

Thermal management has improved with advanced cooling techniques and optimized packaging designs, ensuring reliable operation even in 3D-stacked configurations. Power delivery challenges have been addressed with sophisticated management systems, enabling stable and efficient power for diverse dies.

The Benefits of Multi-Die Solutions

The benefits of multi-die solutions are transformative, addressing many of the limitations of traditional monolithic designs. By integrating multiple dies within a single package, these architectures achieve higher performance through improved interconnectivity and reduced latency. Design flexibility is another key advantage, allowing heterogeneous components such as processors, accelerators, and memory to be combined and optimized for specific workloads.

From an economic perspective, multi-die architectures provide a cost-effective path forward as semiconductor nodes approach their physical and economic limits. Smaller dies manufactured on mature nodes can be combined using advanced packaging, reducing costs while maintaining high performance. This modular approach also improves yield and scalability, facilitating faster development cycles and enabling the rapid adoption of emerging technologies.

Why the Timing Is Right for Multi-Die Solutions

The adoption of multi-die solutions is primed for takeoff, driven by technological advancements, market demand, and economic pressures. Applications like AI, high-performance computing, and data analytics require scalable, energy-efficient architectures, which multi-die designs provide. Mature interconnect, thermal management, and power delivery technologies now enable high-volume production, while standardized interfaces like UCIe foster collaboration and reduce costs.

Rising process node costs further underscore the economic value of multi-die solutions, as demonstrated by industry leaders AMD, Intel, Microsoft and NVIDIA in their flagship products. These architectures align with market demands and sustainability goals, offering a cost-effective path to high performance.

Additionally, ecosystem growth fueled by robust supply chains, tools and IP has simplified design and integration, enabled reduced costs and accelerated time-to-market for multi-die systems. Synopsys’ 3DIC Compiler, 3DSO.ai, and Die-to-Die IP are examples of such tools and IP, to name a few.

Summary

The evolution of multi-die solutions represents a turning point in semiconductor design. With significant advancements in interconnect technology, thermal management, power delivery, and ecosystem development, these architectures are now more feasible, efficient, and cost-effective than ever before. As the demand for high-performance, energy-efficient computing grows, multi-die solutions offer a scalable path forward for the semiconductor industry. Positioned at the intersection of technological innovation, market demand, and economic necessity, multi-die solutions are set to play a pivotal role in shaping the future of computing.

The bold prediction by Synopsys of 50% of new HPC chip designs being multi-die implementations in 2025 looks realistic if not bold enough.

To learn more, visit Synopsys Multi-Die Solution Page.

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A Deep Dive into SoC Performance Analysis: What, Why, and How

Synopsys Brings Multi-Die Integration Closer with its 3DIO IP Solution and 3DIC Tools

Enhancing System Reliability with Digital Twins and Silicon Lifecycle Management (SLM)

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Heterogeneous 2D/3D Packaging Challenges

Heterogeneous 2D/3D Packaging Challenges
by Daniel Payne on 01-27-2025 at 10:00 am
Categories: 3D IC, EDA, Siemens EDA

Innovator3D IC flow min

A growing trend in system design is the use of multiple ICs mounted in advanced packages, especially in high-performance computing and AI. These modern packages now integrate multiple ICs, often with high-bandwidth memory (HBM), resulting in hundreds of thousands of connections that need proper verification. Traditional methods, often relying on manual processes and spreadsheets, simply cannot keep pace with this complexity. This blog post will explore how a new approach using formal verification is transforming the way IC package connectivity is verified, drawing insights from a recent white paper by Siemens EDA detailing the Innovator3D IC tool flow.

The Challenges of Modern IC Package Design

Historically, IC package design was relatively simple, mainly involving fanning out die bumps to connect to a printed circuit board. However, with heterogeneous integration and advanced packaging technologies, the task has become a complex system integration challenge. Substrate designers now juggle multiple inputs, often from multiple engineers developing their components simultaneously, and must ensure both electrical and functional correctness. The sheer number of connections, often exceeding 500,000, makes manual verification impractical, and relying on spreadsheets becomes error prone and tedious. The maximum number of rows in Excel is 1,048,576 which is not enough for many designs.

Limitations of Traditional Verification Methods

Traditional verification methods are struggling to keep up. Functional verification, which simulates the design to ensure it operates correctly, is challenging for package designs. It requires functional models for each die, models for discrete components, and testbenches. When chiplets, such as HBM, are involved, these models may not be readily available, and even if they are, package designers often lack the expertise to adapt and use them.

Layout versus schematic (LVS) verification, while helpful in ensuring the physical implementation matches the source netlist, does not verify the functional correctness of the design. It can catch shorts and opens, but it cannot confirm that the design works as intended. If the source netlist itself has errors, LVS will not catch them, giving a false sense of security.

Formal Verification: A New Paradigm

Formal verification provides an alternative solution by using mathematical analysis to exhaustively verify all interconnections between IC blocks. This method only requires two key pieces of information:

  • The system top module with connectivity information
  • Module port definitions of the dies

Formal verification does not require lengthy testbenches or assertions. It can detect connection errors, ensure the correctness of connections, and identify potential short circuits. Since the method uses mathematical analysis considering all possible stimulus, it can prove connections are correct without any overlooked scenarios.

Innovator3D IC and Check Connect

Siemens EDA’s Innovator3D IC (i3D) tool helps engineers tackle the complexities of modern package design. i3D collects data from various sources, such as die, BGA, and netlist data, and allows the creation of system connectivity. The connectivity can be exported in multiple formats, including Verilog, for verification purposes.

Innovator3D IC flow

Siemens’ Check Connect is a formal verification tool that is used to verify the connectivity of a package design. It uses a golden reference model, often developed by the design team through the design phase and extensive simulation and automatically extracts the connections to verify the design. The tool works with the i3D package design tool to generate Verilog netlists and then verifies the connections. The tool can generate a missing-port report that lists the ports not covered by any connections, helping to identify potential issues in the reference model or the connection specifications. The tool is also very fast and can work on big systems because the design modules are treated as black boxes, focusing only on connections between blocks.

Formal Verification Flow
Benefits of the Formal Approach
  • Exhaustive Verification: Formal methods mathematically analyze all possible scenarios, guaranteeing that connections are correct.
  • Early Detection: Errors can be detected early, right after package prototyping, saving time and money.
  • Automation: The entire flow is automatic, from creating connectivity specifications to verifying packaging output connectivity. The script is simple and can be reused for different projects.
  • Speed: Automatic parallel algorithms on the compute grid can verify huge numbers of connections in minutes or even seconds. Test cases have shown verification times as low as 30 seconds for designs with over 20,000 connections and 56 seconds for designs with over 40,000 connections.
  • Improved Reliability: Formal verification is critical in industries with strict regulatory standards, such as aerospace and automotive, because it can provide an exhaustive analysis of connections, and some tools are ISO 26262 certified.
Conclusion

The white paper demonstrates that formal verification is an effective approach for the challenges of modern IC package design. By automating the verification process, it ensures the correctness of connections early in the process, leading to improved quality and reduced time to market. The learning curve for setting up these formal tools takes only minutes. This approach is poised to become an essential part of the modern IC package design flow.

Read the 13 page white paper online showing how Innovator3D IC uses formal verification.

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Webinar: Achieve Full Flow and Resource Management Visibility to Optimize Cost and Sustainability with Innova

Webinar: Achieve Full Flow and Resource Management Visibility to Optimize Cost and Sustainability with Innova
by Mike Gianfagna on 01-27-2025 at 6:00 am
Categories: EDA, Events, Innova

Webinar Achieve Full Flow and Resource Management Visibility to Optimize Cost and Sustainability with Innova

The lifecycle for complex chip design includes many factors. Traditional systems focus on design tasks, associated schedules and manufacturing logistics. While these are important aspects of the project there is a lot more that can be measured, predicted and tracked. Taking a more holistic view of the project opens new opportunities to optimize not only cost and schedule, but sustainability and ecological impact. This expanded view of the chip lifecycle will help to manage critical trends such as water consumption and CO2 emissions.

Innova presented a comprehensive approach to achieve these results in a recent webinar. A replay link is coming but first let’s take a high-level look at how to achieve full flow and resource management visibility to optimize cost and sustainability with Innova.

You can access the webinar replay here.

The Webinar Presenter

Dr. Chouki Aktouf

Dr. Chouki Aktouf presented the webinar. He is a co-founder of Innova Advanced Technologies. Prior to Innova, he founded Defacto in 2003. Before that, Dr. Aktouf was an associate professor of Computer Science at the University of Grenoble – France and leader of a dependability research group. He holds a PhD in Electric Engineering from Grenoble University.

Chouki has a relaxed and easy-going presentation style. He covers a lot of important material clearly and concisely. You will learn a lot from him during this webinar, which is 30 minutes in length followed by a very useful 10-minute Q&A session.

Some Webinar Details

Chouki presents both the software and methodology that are available to achieve big picture management of complex chip design projects and the broader benefits of cost and sustainability that result. At a high level, Innova covers predicting, reporting, optimization and needs for EDA tool licenses, computing server resources, and IP cores which are involved in complex chip design projects

You can learn more about Innova in this informative 2025 Outlook piece on SemiWiki.

Many benefits of the Innova PDM (Project & Design Management) tool are discussed. In the area of cost reduction, there are two aspects to consider:

Design Flow Management

  • Report optimal usage scenarios per design project, design flow, etc.
  • Predict Design Resources
  • Optimize the usage of computing resources

Design Resource Management

  • Optimize jobs scheduling with the available design resources
  • Make cost-effective the debug, reuse and tracking of complex design flows
  • Correlate between flow execution steps and design resources
  • Track and manage real-time user-defined alarms

The figure below summarizes the data flow of this approach, which aims to reduce cost by 15 to 30 percent compared to ad-hoc methods.

Innova PDM Flow

Many details are discussed on how to integrate the Innova tools into any design flow. Both GUI and script-based approaches are covered. The use of machine learning to enhance predictability is also covered.

Chouki also discusses in detail how the visibility provided by the Innova flow can help with sustainability considerations, such as carbon footprint. An expanded view of the project is used, which includes aspects such as transportation logistics. The goal is to develop an eco-friendly design footprint.

To illustrate the process, here are some of the items considered. Chouki does a great job explaining how all this works.

Metrics

  • Flow complexity
  • Design complexity
  • Resource complexity

Ecological Impact

  • Gas emission kgCO2eg
  • Use of minerals and fossil resources (kgSbeg)
  • Consumption of primary energy (MJ)

Configuration Recommendation

  • Flow
  • Cluster selection according to ecological impact

Chouki illustrates the impact of this type of capability by examining two equivalent design flows with the tool. It turns out the flow that looks more complex on the surface is actually more efficient and significantly more eco-friendly. He points out there is no way to know this without using the kind of detailed management and analysis provided by Innova.

To Learn More

A capability that both optimizes cost and optimizes the eco footprint of a design is critically important for the health of the company and the planet. Innova provides a complete solution, and this webinar explains it very well. I highly recommend you watch the replay. You can access the webinar replay here. And that’s how to achieve full flow and resource management visibility to optimize cost and sustainability with Innova.

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Innova at the 2024 Design Automation Conference

WEBINAR: Reconcile Design Cost Reduction & Eco-design Criteria for Complex Chip Design Projects

2025 Outlook with Dr. Chouki Aktouf of Innova

Podcast EP271: A Tour of SiLC’s LiDAR Technology and Its Broad Impact with Mehdi Asghari

Podcast EP271: A Tour of SiLC’s LiDAR Technology and Its Broad Impact with Mehdi Asghari
by Daniel Nenni on 01-24-2025 at 10:00 am

Dan is joined by SiLC Technologies CEO Mehdi Asghari. Mehdi is one of the early pioneers of the silicon photonics industry with over 25 years of commercialization experience in this space. SiLC is his third Silicon Photonics start-up focusing on advanced imaging solutions. His previous startups, Kotura and Bookham, both enabled successful exits.

In this informative podcast Dan explores the unique LiDAR technology SiLC is developing with Mehdi, who explains the benefits of Frequency Modulated Continuous Wave (FMCW) technology for LiDAR applications. Mehdi describes a broad range of applications for the technology that all help to deliver accurate, intelligent and robust machine vision. Drone tracking and recognition, diverse mobility applications and warehouse automation and robotics are some of the topics discussed.

The special advantages of SiLC’s technology are discussed along with a view of what lies ahead for the company. The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Crosstalk, 2kAmp power delivery, PAM4, and LPDDR5 analysis at DesignCon

Crosstalk, 2kAmp power delivery, PAM4, and LPDDR5 analysis at DesignCon
by Don Dingee on 01-24-2025 at 8:00 am
Categories: EDA, Keysight EDA

Old way of crosstalk analysis

High-speed digital (HSD) designers have long tested the limits of realizable speed. GHz frequencies are now the norm, and multi-level signaling is pushing rates higher while the long-awaited transition to optical signaling and even higher rates looms ever closer. Power density is also climbing, and data-hungry applications like AI unexpectedly create bottlenecks in power delivery with decreasing margins on sub-1V power rails carrying thousands of amps into large chips. The demands of signal integrity, power integrity, and electromagnetic interference (EMI) engineering are fueling a new generation of streamlined EDA workflows looking to deliver a high-fidelity, end-to-end digital twin from one simulation environment.

Keysight’s Advanced Design System (ADS) platform has set the industry standard for high-speed digital and power integrity design workflows with in-situ chip and printed circuit board (PCB) EM extraction and simulation. ADS has always prioritized simulation accuracy, combining classic circuit analysis with high-fidelity EM models in a co-simulation approach. It quickly delivers digital twin levels of accuracy, with more detailed results and design insights than extensive physical measurements, which can be challenging to set up, costly, and time-consuming. ADS R&D teams are now breaking new ground with more capabilities to find, visualize, and solve the root causes of complex design failures – before designers commit to hardware.

Keysight EDA teams previewed DesignCon 2025 and Keysight Education Forum technical talks on four design challenges ADS uniquely targets: advanced crosstalk analysis in wide-bus scenarios, 2kAmp power delivery for massive 3DHI chips, analyzing PCIe links with PAM4 modulation, and system simulation and verification of LPDDR5 designs used in AI applications.

One-pass crosstalk analysis for single-ended buses saves costly respins

A simplified view of crosstalk looks at only adjacent lines and judges the goodness of eye patterns. However, Hee-Soo Lee, HSD Segment Lead at Keysight, says customers indicate that tapeouts of dense, high-speed designs fail more often because of complex crosstalk problems – and identifying the culprits can be challenging. “Designing and laying out a complex board with a very wide single-ended bus can be tough, and designers must be mindful of avoiding unwanted design failures due to crosstalk-related eye closure,” says Lee. “Packages and vias on multi-layer boards can inject crosstalk to any victim line, not only from adjacent transmission lines, and with reduced design margin and higher data rates, even 10mV of crosstalk voltage may affect a system’s performance significantly.” If eye patterns look good, there’s no problem, but where and how does a designer go about fixing things if the eye is closed?

“With a 64-bit wide bus, it can be days just manually setting up crosstalk simulation runs,” continues Lee. “Correctly terminating multiple lines is tedious, and one can’t assume terminations are always 50 ohms – it depends on the drivers and receivers and the signaling conditions. One setup gets an answer for one aggressor and multiple victim lines, and then that process needs to be repeated perhaps 150 or 160 times to analyze the entire data bus.” Lee points out that in chip designs, things get even more complicated and can trigger a million-dollar re-spin of die or packaging if the analysis is not done right.

Keysight’s answer is Crosstalk Analyzer, now in the ADS 2025 release, with three unmatched values. First, it uses the IBIS termination model for the drivers and receivers to model terminations accurately, removing the guesswork. Second is the automated workflow for setting up a bus for crosstalk analysis with all aggressors and victims configured. Third are the versatile aggressor modes available, which include rising and falling steps, single pulses, and continuous signals. After this streamlined setup, ADS Crosstalk Analyzer simulates near-end and far-end crosstalk over the entire bus with the correct termination impedances for the signaling context in one pass directly from a single schematic.

“Tools are tools, and we still need engineers to find and fix issues,” adds Lee. He cites a test case from a customer’s example, a board with a memory interface running at 3200Mbps where crosstalk on a line came predominately not from the adjacent trace but from a via farther away, influenced by the BGA package and other vias in the board layout. “We produce meaningful data from automated crosstalk analysis in a few minutes, whereas other error-prone setups can take days and may not highlight the root cause of eye closure.”

Power integrity analysis in 1000A/nsec PCB power delivery network

Speaking of complex packages and multi-layer board layouts with vias, power integrity is also seeing issues stemming from board structure complexity. “Power delivery isn’t DC. It’s AC,” says Heidi Barnes, Sr. Application Engineer at Keysight. “For years, power delivery network (PDN) impedance typically registered as 10s of milliohms. Now, a server-class AI chip consuming 1600W requires PDN impedance in microohms, and suddenly, intentional structures and parasitics in multi-layer PCB and package layouts make a big difference.”

Barnes teams with Steve Sandler of Picotest and Ben Dannan of Signal Edge Solutions to highlight an interesting specimen – a 2000A, 11-bit programmable transient load stepper. Its claim to fame is slewing 1000A of load in one nanosecond. That figure seems otherworldly until one steps back to think about power management and sequencing, rapid switching of many transistors simultaneously, and inrush currents held up by bypass capacitors. It’s more realistic considering today’s large 3DHI chips and the concept of point-of-load power delivery, where rails must enter on some pins toward the center of a package for power integrity, transferred up from lower layers using vias. Barnes helped create a digital twin of the stepper in ADS PIPro for complete EM and electrothermal analysis.

“People may not realize that 10 microohms of impedance on a power rail is sensitive to parasitic inductances of only 100 pH. Now we’re looking at transmission line effects in the kHz range,” continues Barnes. “Validating a power rail for stability used to imply small-signal AC analysis. But to understand these large dynamic loads, with crosstalk and ripple, and where to place things like sense lines, we’re turning to large-signal AC analysis.” Behavioral models of voltage regulator modules (VRMs) traditionally run in SPICE simulators can migrate to ADS frequency domain harmonic balance analysis for large-signal simulations that jump directly to the time domain steady-state ripple solution.

ADS PIPro simulations for this 2kAmp digital twin with 55 VRM phases run in 77 seconds, uncovering and visualizing a resonance from an impedance peak at 91 kHz. “When expensive devices are on the line, like in defense and aerospace applications, engineers need to look at this kind of power integrity simulation to reduce re-spins and prevent inadvertently exceeding a chip’s voltage or thermal reliability specifications,” concludes Barnes.

Pushing PCIe links faster and helping AI chipsets and systems scale

Two more high-speed digital topics look at the evolution of PCIe and the challenge of distributed LPDDR5 interfaces typical in AI applications. Pegah Alavi, Sr. Application Engineer at Keysight, is in a panel session with Samtec, Amphenol, and others, showing recent work with ADS looking deeper at PAM4 modulation used in PCIe 6.0 and other specifications and the impact of channel length and connectors as data rates increase to 128GT/s in future releases. Alavi emphasizes Keysight’s unified measurement science approach, sharing that PCIe compliance test solutions in Keysight real-time oscilloscopes also appear in ADS for use with simulated waveforms. Initial work on PAM4 simulations with 128GT/s data rates is complete, with equalization and channel characteristic enhancements in discussion for future generations of PCIe.

In a separate Keysight Education Forum technical talk, Alavi shares her collaboration with a partner company to develop promising ADS analysis results on power-aware LPDDR5 implementations, finding accurate target Z impedance values for optimizing eye diagrams. “We have a customer designing large AI chipsets, and the punchline is by using ADS, they spotted problems in simulation before fabricating their board prototypes,” she says. Much of the work analyzes trace spacing for crosstalk improvements, but another exciting result is a significant reduction in bypass requirements. “With data in hand, our customer cut bypass capacitors on the board by a bit over two-thirds, from 79 to 25. The analysis reduces BOM costs for the board and improves confidence in design margins for the LPDDR5 buses.”

“Within a single design platform – ADS – combining memory design, signal integrity, and power integrity analysis, we can explore the LPDDR5 design space much more. That will help AI and other 3DHI chipset designs scale faster while delivering first-pass silicon and board success,” Alavi concludes.

Learn more at DesignCon 2025 and KEF

More details will come in tutorial and panel sessions at DesignCon 2025 and the Keysight Education Forum sessions at the Santa Clara Convention Center. In addition to the speaking slots on the program, exhibitor attendees can see Keysight’s ADS with power and signal integrity solutions and its Chiplet PHY Designer in booth #1039. For more information, please visit the following:

Keysight @ DesignCon 2025

Keysight ADS 2025 Product Release

Keysight Expands Chiplet Interconnect Standards Support in Chiplet PHY Designer 2025

Also Read:

Chiplet integration solutions from Keysight at Chiplet Summit

GaN HEMT modeling with ANN parameters targets extensibility

Keysight EDA 2025 launches AI-enhanced design workflows

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2025 Outlook with Dr Josep Montanyà of Nanusens

2025 Outlook with Dr Josep Montanyà of Nanusens
by Daniel Nenni on 01-24-2025 at 6:00 am
Categories: CEO Interviews

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Dr Josep Montanyà is a Co-founder leading the company, with +18 years of experience in MEMS, patents and the semiconductor industry. Founded Baolab Microsystems prior to Nanusens.

Tell us a little bit about your company.

 We have a patented technology that allows us to build chips with nano-mechanisms inside (called NEMS) using the de facto standard manufacturing for solid state chips (called CMOS). This allows us to have better performance, smaller size and lower cost.

There are many applications for this technology, including sensors, RF tunable devices and even AI processors with higher speeds and less consumption. Our initial focus is on a particular product called RF DTC (Digitally Tunable Capacitor). We have a very clear route to market, with signed LOI, and we will place it into Tier 1 phones (and more) that will hit the market in 4 years.

Beyond this initial product there are more RF devices we can build, and a large variety of sensors. Until now inside each wearable or portable system, you have a digital processor and one or more external sensors chips. We have the capability to change this, by embedding the sensors into the digital processors. Today it is possible to do this by using complex multi-die packages. We don’t need to do that. Instead, at Nanusens, we can build all these sensors monolithically on the same CMOS die where the digital processor is built. And this is done without impacting yield and using minimal additional area. This reduces dramatically the size of the overall system, and it reduces also power consumption to levels that today are unseen.

The company is split between its HQ in Paignton (UK) and a subsidiary in Cerdanyola (Spain).

What was the most exciting high point of 2024 for your company?

This year we got our RF DTC prototype measured by a large corporation. This was a very important milestone, because not only it shows the interest of the industry in our product, but it also validated all our measurements.

These measurements proved the incredible performance that our RF DTC can achieve, and it has helped us to better understand our route to market. Being able to increase by 30% the antenna efficiency of cell phones means that we increase by 30% talk time, we also increase by 14% the range from the base antenna, meaning that many areas of poor reception disappear. And for the smartphone OEM, the size of the PCB can be reduced, given that with our solution there is no need to switch standalone external capacitors. Reducing PCB size inside the phone is a key driver for smartphone OEMs, as this means having more space for battery.

With our chip, we aim to monopolize the +$800m market of smartphone aperture antenna. This is because we have unmatched performance, small size and low cost. And all this comes from the fact that we use our patented technology to build NEMS devices in CMOS.

What was the biggest challenge your company faced in 2024?

Main difficulty for a pre-revenue start-up like Nanusens developing semiconductor and even more MEMS technology is fundraising.  Our goal for 2024 on this front was to raise a £8m Series A to provide prototypes of inertial sensor and RF DTC devices, so that next year we would be in the market with our first products, and we have customers waiting for them. This has been moved to 2025 as we will have achieved more significant milestones by then that will facilitate this process.

How is your company’s work addressing this biggest challenge?

We have decided to focus on the RF products, leaving sensors and other devices in our future roadmap. This has allowed us to reduce costs and be more efficient.

What do you think the biggest growth area for 2025 will be, and why?

I think AI processors will keep being the dominant area in semiconductors. The incredible success of NVIDA, plus all the big techs jumping in, forecasts a very interesting year. At the same time, however, the market is starting to adjust itself, and I believe we will start seeing more start-up failures in this field as well. You need something really different to succeed in such a competitive field, dominated by giant players.

How is your company’s work addressing this growth?

We put a limited effort on studying the possibility to build better AI processors using our NEMS in CMOS technology. We discovered that it is possible for us to build vacuum transistors in CMOS. This has the potential to enable x10 faster AI processors and consuming half of the power.

Vacuum transistors enjoy the terahertz range bandwidths of vacuum tubes, but without their problems of large size, mechanical fragility, low reliability and large power consumption. In fact, given the very small, nano-sized gaps of vacuum tubes, there is not even a need for heating the metals at high temperatures. Instead, a low voltage generates such a strong electrical field with this small gap, that electrons fly between the cathode and the anode by field emission.

There are research papers on vacuum transistors, which have been built using custom NEMS processes. At Nanusens, we have the capability to build them using standard CMOS processing. This has the potential to build AI processors far beyond the state of the art, and with a process ready to produce them in high volumes. This is a project for after the Series A round is completed.

What conferences did you attend in 2024 and how was the traffic?

We did not attend any conference this year.

Will you attend conferences in 2025? Same or more?

I don’t know yet. But most probably we will not attend many conferences, as our focus is in internal R+D.

How do customers engage with your company?

Although technically we can sell IP and have already done so, our business model is to sell product (ICs) directly to our customers or through distributors.

Additional questions or final comments?

It is always difficult to predict the future. But 2025 will be a very interesting year. I will be especially interested to see what happens in this race for dominating the AI digital processor market. But, whoever wins this next year, we have a technology that will overpass them in the next years!

About Nanusens

Nanusens’ patent pending technology enables MEMS nanostructures to be built within the layers of a CMOS chip using standard CMOS processes. This enables us to create both MEMS sensors and MEMS capacitors with the required control circuitry as innovative, single chip solutions that are significantly smaller than their current, multi-component equivalents. They can also be produced in virtually unlimited numbers in standard CMOS fabs, taking advantage of their low production cost.

Also Read:

CEO Interview: John Chang of Jmem Technology Co., Ltd.

CEO Interview: Dr. Zeynep Bayram of 35ELEMENTS

CEO Interview: Subi Krishnamurthy of PIMIC

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2025 Outlook with Samia Rashid of Infinisim

2025 Outlook with Samia Rashid of Infinisim
by Daniel Nenni on 01-23-2025 at 10:00 am
Categories: EDA, Infinisim

2025 Outlook with Samia Rashid of Infinisim

Tell us a little bit about yourself and your company. 

I am Samia Rashid, co-founder and president of Infinisim. My background is quite diverse, spanning product management, manufacturing, sales, and mergers and acquisitions. Before founding Infinisim, I was with iManage, Inc., where I played a pivotal role in growing the company from startup to $20 million in sales and taking it public. My responsibilities included sales, marketing strategy, and building partnerships with major Fortune 500 companies. I hold an MS in Engineering from Duke University and an MBA from the University of Chicago.

At Infinisim, we focus on SoC clock verification solutions for high-performance designs. As technology moves into smaller process nodes, where nanometer effects become critical, our tools empower customers to push the boundaries of clock performance—achieving results that static timing-based solutions simply cannot match. With Infinisim, customers can confidently sign off on designs optimized for peak performance and reliability.

What was the most exciting high point of 2024 for your company? 

Interestingly, it wasn’t a specific product launch or customer win. Instead, it was how the challenges of cutting-edge semiconductor designs drove customers to us. In 2024, the growing demand for AI and data-intensive applications underscored the vital role of clock performance in advanced designs. Factors like timing jitter and reliability aging posed significant challenges, and Infinisim’s solutions emerged as essential for addressing them.

One standout moment involved a high-profile issue from a major semiconductor company. A clock tree circuit within their IA core, particularly vulnerable to aging under high voltage and temperature, became a critical pain point for the industry. This is exactly the type of problem Infinisim is built to solve. It not only demonstrated the importance of our solutions but also significantly increased interest in our company and its capabilities.

What was the biggest challenge your company faced in 2024? 

Remarkably, our most exciting high point also highlighted our biggest challenge. The clock tree aging issue revealed why advanced designs require a shift in design methodologies. However, not all companies are ready to adapt.

Many teams continue to rely on large design margins to manage uncertainties, assuming this approach ensures reliability—until unforeseen problems arise. Unfortunately, these oversized margins leave untapped performance on the table, increase design size, and drive up costs at advanced nodes, ultimately affecting both profitability and competitiveness.

Our biggest challenge has been encouraging companies to rethink these traditional methods. While design margins have long been considered a safety net, they are no longer sustainable at advanced technologies. Addressing this requires not just innovative tools but also a shift in mindset, driven by education and collaboration with the industry.

How is your company’s work addressing this biggest challenge? 

Our approach focuses on both cutting-edge technology and customer education. Infinisim provides industry-leading tools for analyzing and optimizing critical timing challenges like jitter and aging, offering unprecedented accuracy and insight. These solutions enable design teams to reduce excessive margins while maintaining reliability, unlocking better performance and profitability.

Equally important is helping the industry shift its mindset. We actively engage with customers to demonstrate how adopting more precise design methodologies can lead to more competitive outcomes. By bridging the gap between traditional practices and advanced solutions, we empower companies to stay ahead in an increasingly complex market.

What do you think the biggest growth area for 2025 will be, and why?

The biggest growth area for 2025 will be driven by the rapid expansion of AI and other data-intensive applications, which demand unprecedented performance and efficiency from semiconductor designs. The size and complexity of these systems will continue to grow, with the trend toward multi-die design accelerating this evolution.

As technology advances into smaller process nodes, managing clock performance, jitter, and aging will become more critical than ever. Jitter combined with aging will emerge as a key area of analysis, directly impacting the performance and reliability of advanced designs.

This presents a significant opportunity for Infinisim to help the industry address these challenges. By enabling customers to optimize performance, reduce excessive design margins, and deliver more competitive products, we are poised to play a pivotal role in shaping the next phase of semiconductor innovation.

How is your company’s work addressing this growth? 

Infinisim is already at the forefront of these advancements. We provide de facto solutions for comprehensively analyzing and optimizing aging and jitter—two of the most pressing challenges at smaller process nodes. Our tools deliver unmatched accuracy and efficiency, helping customers confidently address these complex demands.

We’re also leading the way in deploying jitter-with-aging solutions at leading-edge companies. By ensuring our technology evolves in line with cutting-edge applications, we enable our customers to create high-performance, reliable, and competitive designs.

How do customers engage with your company?

We invite you to connect with us at the conferences we’ll be attending in 2025— details are available on our website. These events are an excellent opportunity to discuss industry trends and explore how our solutions can address your challenges.

You can also reach out directly through our website to start a conversation. We’re always excited to collaborate and help customers unlock the full potential of their designs while driving greater profitability.

Additional questions or final comments? 

I encourage all design teams working at advanced nodes to critically evaluate their design margins. While these margins were traditionally expanded to manage unpredictable effects, Infinisim’s tools now make it possible to accurately analyze and address these challenges. By embracing innovative solutions, teams can optimize their designs, reduce waste, and build more competitive, profitable products. We’re excited to continue partnering with companies to achieve these goals and shape the future of semiconductor innovation.

About Infinisim

Infinisim, Inc is a privately funded EDA company providing design verification solutions. Founded by industry luminaries, the Infinisim team has over 50 years of combined expertise in the area of design and verification.

Infinisim customers are leading edge semiconductor companies and foundries that are designing high-performance mobile, AI, CPU and GPU chips.  

Infinisim has helped customers achieve unprecedented levels of confidence in design robustness prior to tape-out. Customers have been able to eliminate silicon re-spins, reduce chip design schedules by weeks and dramatically improve product quality and production yield.

Contact Infinisim

Also Read:

My Conversation with Infinisim – Why Good Enough Isn’t Enough

The Perils of Aging, From a Semiconductor Device Perspective

A Closer Look at Conquering Clock Jitter with Infinisim

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2025 Outlook with Randy Caplan of Silicon Creations

2025 Outlook with Randy Caplan of Silicon Creations
by Daniel Nenni on 01-23-2025 at 6:00 am
Categories: IP, Silicon Creations

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Randy Caplan is co-founder and EVP of Silicon Creations. For over 18 years, Randy has helped to grow Silicon Creations into a leading semiconductor IP company with more than 500 customers in over 20 countries, and nearly 100% employee retention. Silicon Creations’ designs have been included in over 1500 mass-produced chips from 3nm to 350nm, from which more than ten million wafers were shipped. Randy’s earlier career includes developing high-speed data transceivers at Agilent Technologies and as a Senior Design Engineer at MOSAID, where he contributed to high-performance silicon IP clocking and interface products.

Tell us a little bit about yourself and your company.

Silicon Creations is a mixed-signal IP provider, specializing in low-risk, high performance clocking solutions (PLLs) and high speed data interfaces (SerDes). We offer designs in every foundry (TSMC, Samsung, GF, Intel, Rapidus, UMC, SMIC, and more…), and every process node (2nm up to 180nm, all inclusive). We were founded in 2006, are ISO9001 certified, and after 18 years, still have close to 100% employee retention.

What was the most exciting high point of 2024 for your company?

Passing ten million (TSMC) wafers shipped using our IP. Also, we passed our 1000th production license of our Fractional SoC PLL IP.

We developed and taped out a portfolio of advanced-node TSMC IP including multiple PLLs, free-running oscillators, low-noise IOs, and temperature sensor IP. We also developed select 2nm PLLs with multiple other foundries including Samsung, Intel, and Rapidus.

What was the biggest challenge your company faced in 2024?

Simultaneously developing IP in all the leading process nodes (TSMC, Samsung, Intel, Rapidus). This required new design techniques to support core-device-only requirements in GAA (gate-all-around) nano-sheet / nano-wire processes.

How is your company’s work addressing this biggest challenge?

Chip development costs in advanced nodes have gone up exponentially. We provide a substantial portfolio of low-risk, proven, foundational IP which helps enable our customers to get their designs right the first time. Our advanced design and verification flow enables fast iteration and re-verification in processes where PDKs are frequently changing. This ensures we’re not the bottleneck in our customers’ development schedule.

What do you think the biggest growth area for 2025 will be, and why?

We’re seeing growth in many parallel market segments including AI accelerator chips, crypto mining, and automotive. Customer tapeouts in advanced nodes (5nm and below) are picking up. We’re even seeing early interest in sub-2nm nodes. Due to long chip development schedules and fab times in advanced nodes, our IP sales tend to be a strong leading indicator of chip sales one to two years in the future. We don’t have first-hand knowledge of the end market forces, but we can infer from our IP sales which semiconductor market segments are seeing increased investment now.

How is your company’s work addressing this growth?

We use an advanced IP design flow, leveraging the latest EDA flows from Siemens, Synopsys, Cadence, Silvaco, and others. This helps to reduce IP development time, improve simulation-to-silicon correlation, and ensure our customers have the foundational blocks they need to build their high-performance chips.

What conferences did you attend in 2024 and how was the traffic?

All TSMC shows, ICCAD (China), DAC and many other foundry and EDA events (Samsung, GF, Intel, Siemens U2U, CadenceLive). Traffic was especially strong at TSMC and ICCAD, but we also had a good turn-out at our booth for the other events as well.

Will you attend conferences in 2025? Same or more?

Silicon Creations attended over 30 trade shows / conferences in 2024, and expects to attend a similar number in 2025…

How do customers engage with your company?

We already work with 16 of the top 20 TSMC customers, and over 500 companies overall. For new inquiries, please send an email to sales@siliconcr.com, or come to our booth at any trade show.

About Silicon Creations

Silicon Creations is a self-funded, leading silicon IP provider with offices in the US and Poland, and sales representation worldwide. The company provides world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), oscillators, low-power, high-performance multi-protocol and targeted SerDes and high-speed differential I/Os for diverse applications including smart phones, wearables, consumer devices, processors, network devices, automotive, IoT, and medical devices. Silicon Creations’ IP is proven and/or in high-volume mass production in process technologies up to the most advanced available in the industry.

Also Read:

One Thousand Production Licenses Means Silicon Creations PLL IP is Everywhere

Silicon Creations is Fueling Next Generation Chips

Silicon Creations is Enabling the Chiplet Revolution