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KLAC – OK Qtr/Guide – Slow Growth – 2025 Leading Edge Offset by China – Mask Mash

KLAC – OK Qtr/Guide – Slow Growth – 2025 Leading Edge Offset by China – Mask Mash
by Robert Maire on 11-02-2024 at 8:00 am

KLAC 2024
  • KLA put up an OK Quarter & Guide with modest growth & outlook
  • 2025 remains slow growth as leading edge offset by China slowing
  • China sanctions remain a “great unknown”- impact unclear
  • Reticle biz getting squeezed from both high & low ends
OK quarter with slight beat as always- Guide is OK as well

KLA reported revenues of $2.84B and EPS of $7.33 (Non-GAAP) slightly above guide an expectation (as always). Guidance was for $2.95B +- $150M and EPS of $7.75+- $0.60.

The slow and steady recovery continues as the fortunes of the semiconductor industry remain mixed with leading edge foundry (read that as TSMC / Nvidia) remains super strong while trailing edge is weak with China moderating.

In memory NAND continues to be very weak while the only bright spot remains HBM-DRAM (again related to AI)

The leading edge strength appears to be strong enough to drag along the weaker sectors into positive growth territory.

Expectations for 2024 WFE spend is now estimated to be in the high $90’sB up from prior views of mid $90’sB.

China moderating as expected

As we heard from Lam last week, China continues to moderate and was down to 42% of business with expectations that China will fall to somewhere in the 30’s in the December quarter with expectations of “digestion” of the binge buying slowing further into 2025

China sanctions remain a “great unknown”

Management did not estimate the potential downside of any expected tightening of China sanctions that would impact the semiconductor industry, taking a more “wait and see” attitude about the potential downside

Leading Edge (TSMC) is strong enough to offset the rest of industry weakness

With Samsung and Intel both moderating spending on the foundry side, the clear winner and big spender remains TSMC which is quickly becoming (perhaps already is ) a monopoly in foundry.

Everyone else continues to fall further behind and the disparity in spend will only increase the gap.

TSMC’s spend is further multiplied by additional locations, such as Arizona, coming up to speed.

Given the revenue they are getting from Nvidia they certainly have the cash flow to keep up the spend rate.

KLA reticle inspection getting squeezed at both high and low ends

Looking at the numbers that KLA reported, wafer inspection grew a whopping 36% year over year and up 17% sequentially.

Reticle inspection (patterning) grew a paltry 6% year over year and coincidentally 6% quarter over quarter.

The disparity has grown huge with wafer inspection for 48% of revenues and reticle inspection (patterning) accounting for a paltry 20%.

For most of KLA’s existence it was a more evenly balanced share of revenues between both segments that grew up as the twin pillars of the business. Indeed, reticle inspection was the first product KLA ever produced.

KLA has lost the technology leadership position, ACTINIC inspection, to Lasertec in Japan. Now we have heard that KLA has lost the low end reticle inspection business in China to a Chinese upstart that has only been in business since 2016.

KLA is losing its China reticle inspection business to a company that is competing with a product that costs a small fraction of KLA’s price offering with good enough performance.

We think KLA will have a solution to compete at the high end with a new approach but it will likely take a few years to come to fruition.

On the low end there really is no solution to a lower price, only a walk away from the business which appears to be the case.

So much as the leading edge (TSMC) business market segment is driving the overall business, from a product perspective it is wafer inspection that is carrying the day for KLA.

The Stocks

Much as we saw with Lam, last week, we would expect a bit of a relief rally in KLAC as the quarter was OK and not a disaster.

Growth and expectation of growth remains modest with 2025 a great unknown, and there is still significant downside in potential sanctions on China that are yet to be accounted for but investors seem to be ignoring that and focusing on the fact that it wasn’t a bad quarter.

We would expect KLAC and other equipment stocks to continue to recover, albeit slowly, from the drubbing they all got on the ASML news.

Investors will likely continue to be more cautious this time around on valuations, however, as most have figured out that this is a long, slow recovery, with many potential pitfalls and issues in front of us

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

LRCX- Coulda been worse but wasn’t so relief rally- Flattish is better than down

ASML surprise not a surprise (to us)- Bifurcation- Stocks reset- China headfake

SPIE Monterey- ASML, INTC – High NA Readiness- Bigger Masks/Smaller Features


Podcast EP258: How Pragmatic Semiconductor Opens New Markets with Non-Silicon, Bendable Technology

Podcast EP258: How Pragmatic Semiconductor Opens New Markets with Non-Silicon, Bendable Technology
by Daniel Nenni on 11-01-2024 at 10:00 am

Dan is joined by Dr. Emre Ozer, Senior Director of Processor Development at Pragmatic Semiconductor. With 67 worldwide patents, and over 60 peer-reviewed publications to his name, he has extensive experience in CPU microarchitecture with particular expertise in performance modelling, fault tolerant CPUs, embedded machine learning, application-specific hardware design, and flexible electronics. Emre spent more than 17 years as Senior Principal Research Engineer at Arm.

Emre provides a comprehensive overview of the unique technology of Pragmatic Semiconductor in this informative discussion with Dan. He describes the non-silicon, flexible manufacturing technology offered by the company and covers some of its advantages regarding cost, cycle time and environmental impact.

Emre then describes the company’s recently announced Flex-RV, an ultralow-cost, bendable, 32-bit RISC-V microprocessor that also includes a programmable machine learning (ML) hardware accelerator. Emre describes a broad array of “extreme edge” applications for the device, such as implantable, wearable and ingestible.

Emre also talks about what’s next at Pragmatic Semiconductor in the area of flexible MCUs.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


Podcast EP257: IC Mask Design’s Unique Layout Training with Ciaran Whyte – Always Ask Why

Podcast EP257: IC Mask Design’s Unique Layout Training with Ciaran Whyte – Always Ask Why
by Daniel Nenni on 11-01-2024 at 8:00 am

Dan is joined by Ciaran Whyte, one of the founding members of IC Mask Design. As Chief Technical Officer he is responsible for all technical activity and the development and administration of all training courses. Cíaran has been training layout engineers for over 25 years and has completed layout training with over 600 engineers to date.

Self-paced e-learning training courses delivered through an accessible online portal, empowering learners to progress at their own pace

Dan explores with Ciaran some of the unique attributes of the layout training offered by IC Mask Design. Ciaran explains that “how” to perform various layout tasks is important, but it’s also important to understand “why” tasks are performed a certain way. Being curious can have significant benefits.

In this eye-opening discussion, Cirian uses the changes taking place in technology as examples of the power of understanding why things are done a certain way, For example, he focuses on layout rules to minimize latchup. This continues to be an important item in layout today, but the combination of smaller geometries and lower operating voltage can influence the approaches used.

Ciaran points out that you need to ask “why” to fully understand this.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Self-paced e-learning training courses delivered through an accessible online portal, empowering learners to progress at their own pace


CEO Interview: Dr. Adam Carter of OpenLight

CEO Interview: Dr. Adam Carter of OpenLight
by Daniel Nenni on 11-01-2024 at 6:00 am

Adam Carter OpenLight CEO

Previously, Dr. Carter served as Chief Commercial Officer at Foxconn Interconnect and Oclaro. At Oclaro, he served as a member of the senior executive team from July 2014 to December 2018, when it was acquired by Lumentum Holdings for $1.85B. Prior to that, he served as the Senior Director and General Manager of the Transceiver Module Group at Cisco from February 2007 to July 2014, where he was instrumental in the acquisition of Lightwire, a Silicon Photonics start-up, and released the first internally-designed CPAK 100G transceiver family utilizing a Silicon Photonics Optical engine.

Tell us about your company?
Formed in 2022, OpenLight is the world’s first open silicon photonics platform with integrated lasers. We enable our customers to incorporate photonic building blocks into their designs, making it more like a photonic ASIC (Application Specific Integrated Circuits) rather than an optical subassembly. As part of our broader vision and business model, we do not manufacture products, instead, we provide customers access to a Process Design Kit (PDK) that facilitates the creation of photonic integrated circuits. We deliver custom PASIC design and license our intellectual property (IP) to a variety of customers, which currently includes over 350 patents, with our portfolio expected to grow to 400 patents in the near future.

What problems are you solving?
While silicon photonics was once met with skepticism, its benefits particularly in efficiency and scalability are now well recognized. Despite this progress, the industry still faces significant challenges in design, manufacturing, and deployment. Through our recent partnerships with Jabil, VLC Photonics, Spark Photonics, and Epiphany, we are working to create a more resilient and collaborative ecosystem while driving innovation across various market segments and transforming the manufacturing landscape.

What application areas are your strongest?
OpenLight’s platform enables companies to design and manufacture at scale, which is crucial as the industry faces increasing demand in areas like data centers, AI/ML, and high-performance computing (HPC). As data centers rapidly multiply, they have become the largest consumers of silicon photonics, driven by the need to interconnect servers, switches, and routers at ever-increasing bandwidths while minimizing costs and power consumption.

Meanwhile, the rise of AI and ML has transformed data center architectures, shifting traffic patterns primarily between GPU and CPU clusters, significantly increasing the demand for higher bandwidth and lower latency. Our technology enhances the performance, scalability, and manufacturability of critical photonic components, including waveguides, splitters, modulators, and photodetectors. By facilitating heterogeneous laser integration in silicon, OpenLight enables data rates to scale from 10G to 800G and beyond, effectively replacing traditional copper cables.

What keeps your customers up at night?
One of the most common concerns we notice among our customers is the reliability and scalability of manufacturing processes, especially in light of supply chain disruptions that have affected many industries. Additionally, there is always hesitation regarding the return on investment in new technologies. Customers want to ensure that their investments in silicon photonics will yield tangible benefits. We help alleviate their concerns by providing expert guidance throughout the design and manufacturing journey. We not only facilitate the adoption of new photonic components into existing infrastructures, but we also equip our customers to confidently navigate challenges while staying competitive in a rapidly evolving market.

What does the competitive landscape look like and how do you differentiate?
Unlike traditional silicon photonics processes, OpenLight’s business model provides open access to its PDK, allowing any company to utilize its technology. The PDK, featuring validated components, is accessible through Tower Semiconductor’s PH18DA production process, where companies can either design their circuits independently or seek OpenLight’s assistance. This openness contrasts with earlier models where access to silicon photonics was limited, often requiring acquisitions or significant investment in new startups.

OpenLight’s platform is the only platform that enables the integration of active components such as lasers and amplifiers directly into the silicon within a foundry process — that’s our key differentiator. We enable customers to integrate photonic designs into silicon more easily and support the broader development of the photonics industry, which is still in its early stages of maturity.

What new features/technology are you working on?
We are making significant strides in the development of PICs focusing on both existing and future advancements. Currently, we offer two 800-gigabit PIC reference designs: an 8×100-gigabit (800G-DR8) design and an 800-gigabit 2xFR4 CWDM one. Now, we are expanding our portfolio to include an 8×200-gigabit design, targeting a 1.6-terabit DR8 and a corresponding 1.6-terabit CWDM variant. The 1.6Tb will mark the first product to utilize distributed feedback (DFB) lasers as its light source and will incorporate semiconductor optical amplifiers to compensate for higher optical losses at 200 gigabits, ensuring optimal performance and meeting stringent specifications.

How do customers normally engage with your company?
OpenLight has made remarkable strides since its inception, growing from three to seventeen customers, and demonstrating a tenfold increase in revenue. We work with a diverse range of companies and organizations involved in various sectors that require silicon photonics technology.

We provide two primary services to our customers. The first is design assistance. For those who lack expertise in silicon photonics designs, we develop custom silicon photonics chips and manage the production process. Once designed, these chips are sent to Tower Semiconductor for production, and wafer-level testing on chip prototypes is done before delivery. OpenLight provides the Graphic Data Stream (GDS) file to the customer, detailing the mask set required for ordering the production of the photonic integrated circuit (PIC) from Tower.

Through our second service, we serve companies that have in-house photonic expertise but haven’t been able to use processes involving active components such as lasers, semiconductor optical amplifiers (SOAs), and modulators. These components are a part of PDKs, and companies can choose a PDK that fits their specific designs, allowing the foundry to create the devices. We offer two types of PDKs through Tower Semiconductor: one from Synopsys and another from Luceda Photonics. While we do not make any components, we do offer reference designs.

Also Read:

CEO Interview: Sean Park of Point2 Technology

CEO Interview: Dr. Mehdi Asghari of SiLC Technologies

CEO Interview: Tobias Ludwig of LUBIS EDA


Adding an AI Assistant to a Hardware Language IDE

Adding an AI Assistant to a Hardware Language IDE
by Tom Anderson on 10-31-2024 at 10:00 am

dvt ai assistant

I’ve been working with AMIQ EDA for several years, and have frequently been impressed by new capabilities in their Design and Verification Tools Integrated Development Environment (DVT IDE) family. They just announced AI Assistant, which leverages large language model (LLM) technology. LLMs are much in the news these days, so I interviewed AMIQ EDA R&D Engineer Serban Ionica to learn more about their solution.

What is AI Assistant?

It’s a new feature of our DVT IDE family that helps hardware engineers be even more productive when developing code for the design and verification of complex chips. The knowledge contained in LLMs, when combined with our own insight into the design and testbench, enables users to generate, modify, and understand code more easily.

We’ve all seen tools like ChatGPT generate code; how is this different?

That’s a great question. Like any LLM-based solution, AI Assistant uses all the knowledge accumulated over the years to generate correct code for specific tasks. One reason that our approach is different is that the generation happens in the context of our DVT IDE, which compiles all the design and verification code. It also builds and maintains a project database that the users can query. They can compose requests including information from the compilation database, and the LLM can leverage sections of code or other design and verification artifacts to improve the accuracy of its responses.

How does users know that the generated code is acceptable for their project?

Any code in the IDE, whether entered manually or generated, is incrementally compiled and checked. In addition, our Verissimo SystemVerilog Linter can incrementally check for any violations of project coding guidelines. Users can type something like “create a SystemVerilog 8-input round-robin arbiter” and the generated code will meet all the same requirements as code written by hand. 

Is AI Assistant used only for generating new code?

It can also explain or improve existing code. Often an engineer inherits code from other projects and would like to understand what it’s doing. Typing “explain the highlighted code” or “make the highlighted code faster” leverages the knowledge embedded in the LLM in the context of the user project. This significantly increases code development efficiency.

Is it a lot of work to start using the new feature?

We make usage easier with predefined LLM interactions called blueprints. DVT IDE ships with a set of blueprints that can be used out of the box for performing common coding tasks. Blueprints can be used directly in the editor window or in a chat window. Users can define their own library of blueprints based on the fully transparent predefined blueprints as examples. Thus, reusable LLM interactions in the form of blueprints can be shared across the entire project team. 

Did you develop your own LLM or include an existing one?

We do not include an LLM. We found that most users have preferences or even company requirements for using specific LLMs. Instead, we tested extensively to be sure that we support popular LLMs from OpenAI, Github Copilot, Google AI, and locally hosted Ollama as well in-house proprietary LLMs. We are open, flexible, and transparent.

How do you handle concerns about leaking proprietary information to cloud-based LLMs?

That’s where transparency comes in. Users can preview all communication with third-party LLMs to ensure that no confidential information or proprietary IP is being transferred. We are well aware of industry concerns that some AI tools seem to be doing things users cannot control or even understand. We ensure that this is not the case for AI Assistant.

Was this new feature a big step for AMIQ EDA?

It certainly was a significant project that took us in some exciting new directions, but it is a natural extension to features we have had in DVT IDE for years. Auto-correct, quick fix suggestions, code templates, and refactoring all involve some amount of code generation. The power of LLMs enables us to take users to the next level of productivity.

Are you underselling the value of your solution?

Make no mistake: AI Assistant is a real-world, sophisticated application of LLMs and AI technology that is valuable today. However, we’re not draping our show booths in huge banners that say things like “THE AI EDA Company” as some vendors do. We want to focus on the value to users and not trumpet AI for its own sake. We also recognize that the nature of LLMs and generative AI (GenAI) means that their results improve over time. This initial release is powerful, but our capabilities will get even broader with lots of hands-on experience. Developing any advanced EDA technology is really a partnership between a vendor and its users.

Finally, is AI Assistant a new product or feature that users must pay for?

It is included at no extra cost in the latest release of both DVT IDE for Visual Studio (VS) Code and DVT Eclipse IDE. We want all our users to be able to take advantage of this new feature and we want to benefit from their usage as we evolve it further.

Thank you for your time, Serban.

You’re most welcome, and thank you for the opportunity to talk.

Also Read:

Writing Better Code More Quickly with an IDE and Linting

AMIQ EDA Integrated Development Environment #61DAC

Handling Preprocessed Files in a Hardware IDE


PQShield Demystifies Post-Quantum Cryptography with Leadership Lounge

PQShield Demystifies Post-Quantum Cryptography with Leadership Lounge
by Mike Gianfagna on 10-31-2024 at 6:00 am

PQShield Demystifies Post Quantum Cryptography with Leadership Lounge

Post-Quantum Cryptography, or PQC provides a technical approach to protect encrypted data and connections when quantum computers can cost-effectively defeat current approaches. Exactly when this will occur is open to much discussion, but the fact is this day is coming, some say in ten years. One of the imperatives is to deploy quantum-resistant algorithms before this happens. That process can also take a long time, so the time for action is now. The National Institute of Standards and Technology, or NIST is an agency of the United States Department of Commerce that promotes American innovation and industrial competitiveness through measurement science, standards, and technology. NIST is deeply involved in developing PQC standards and you can get a view of the whole process here.

PQShield is a company that delivers hardware, software, firmware and research IP to enable post-quantum cryptography. Recently, the company started a series of videos to help the industry understand the PQC world and what to do. Let’s look at how PQShield demystifies post-quantum cryptography with Leadership Lounge.

NIST Standards – the PQC Turning Point

There are several short and very informative videos on Leadership Lounge. A complete list and a link is coming. First, I’d like to focus on the second installment, entitled NIST standards – the PQC turning point. Each video features a dialogue between Ben Packman, Chief Strategy Officer and Dr. Ali El Kaafarani, Founder & CEO at PQShield. These gentlemen have a natural and easy-to-watch style. You are essentially listening in on an information-rich dialogue.

In this video, Ben and Ali discuss the publication of the first NIST PQC standards. This is certainly cause for celebration. It represents a substantial achievement for the whole collaborative PQC community. The long road to get to this point is discussed as there were many delays and frustrations along the way. Despite this, Ali points out that the NIST team was always there to provide timely support and clarification. It was indeed a broad collaboration.

He also points out that in recent months, even NIST was anxiously awaiting the publication of the new standards along with the rest of the community. The work has been done, and now the government needs to publish the standards. Ben states that “even NIST wound up in the same boat as the rest of us.”

Even with the long wait, it is pointed out that everyone really appreciated the thorough process, and the communication, clarification, and input from everyone involved. The community will now move to implementation and testing of the new standards, a long and complex process that will continue to require communication and collaboration.

The Leadership Lounge Library

These videos cover a lot of ground, with more on the way. Here is a list of the current topics.

Video 1: Algorithms are just recipes. The release of the new NIST standards is a great achievement, but how do you apply them? At PQShield, this is a question that drives the company towards mature products, solving real-world problems. Ali and Ben come to realize that algorithms are really only recipes – the key is how you use them. 

Video 2: Summarized above.

Video 3: How to think crypto agile. Cryptography is about risk mitigation. It’s a question of how you value your business, and it might well be the last line of defense when it comes to protecting what’s important to you. Ali and Ben talk about the way we each think about our business, and how that impacts decisions we make.

Video 4: Celebrating the cryptography community. Ben and Ali reflect on the origins of PQShield as part of the wider cryptographic community and how great it is to be part of a brilliant but genuinely down-to-earth group of cryptographers.

Video 5: No can to kick down the road – it’s all about compliance. Release of the standards has definitely shifted the focus – it’s now time to talk about how we deploy post-quantum cryptography, and where to start in the supply chain.

Video 6: Post-quantum is an era. The term ‘post-quantum’ defines an era when public key cryptography needs to be replaced with new technology. Ali and Ben discuss some of the wider pieces of cryptography, many of which are not vulnerable to the quantum threat, but form essential components nevertheless, in the ‘post-quantum’ era.

Video 7: Is it time to stop talking about PQC?  Ben and Ali discuss moving into an era when the focus has shifted from the nature of the threat, to talking about compliance with the next generation of standards in public key cryptography.

Video 8: PQC in silicon. Ben and Ali talk about PQShield’s silicon implementation of PQC – the company hasn’t just designed PQC solutions, it’s built hardware IP onto a physical chip.

Video 9: Standardization – what’s next? Ben and Ali discuss NIST’s timeline, including FALCON, Round 4 KEMs, the necessary mix of lattice, code-based and hash algorithms, as well as the ongoing effort to select digital signatures.

To Learn More

You can learn more about PQShield and its unique focus and charter on SemiWiki here. And you can browse all the great videos on Leadership Lounge here. PQC is a challenge that will impact everything. Getting ahead of the game is the best strategy. PQShield is the best partner to do that. And that’s how PQShield demystifies post-quantum cryptography with Leadership Lounge.


Datacenter Chipmaker Achieves Power Reduction With proteanTecs AVS Pro

Datacenter Chipmaker Achieves Power Reduction With proteanTecs AVS Pro
by Kalar Rajendiran on 10-30-2024 at 10:00 am

Alphawave Using proTeanTechs

As semiconductor technology advances and nodes continue to shrink, designers are faced with increasing challenges related to device complexity, power consumption, and reliability. The delicate balance between high performance, low power usage, and long-term reliability is more critical than ever. This growing demand calls for innovative solutions that can dynamically adapt to real-time operating conditions, ensuring devices meet performance standards while minimizing unnecessary power consumption. In conventional chip design, operating voltages are typically set higher than the minimum required to account for variables like temperature changes, signal noise, and process aging. While this safety margin helps prevent performance issues, it often leads to inefficient power consumption due to a one-size-fits-all approach, resulting in over-provisioning.

Demo at the TSMC OIP Ecosystem Forum

At the recent TSMC OIP Ecosystem Forum, proteanTecs showcased their AVS Pro solution with a live demo that highlights how their adaptive voltage scaling (AVS) technology can revolutionize power management in semiconductor chips. The solution can achieve up to 14% in power savings.

The demo showed how AVS Pro effectively minimizes power consumption by dynamically adjusting the chip’s operating voltage using embedded margin agents and dedicated algorithms. In this case, hundreds of agents were spread across the chip’s logic paths, to continuously monitor the timing margins—an indicator of how close a path is to experiencing a timing failure. This real-time data was fed into the AVS Pro application, which adjusted the voltage based on the current needs of the chip, ensuring that performance was maintained without excessive power usage. Initially, the chip’s supply voltage was set at 650 millivolts—higher than the minimal operating voltage, or VDD Min, of 580 millivolts. The extra voltage is applied as a safeguard against potential issues like aging, environmental noise, and workload variations. However, this guard band leads to over-provisioning, which wastes valuable power.

When AVS Pro was enabled, the system reduced the voltage based on real-time feedback from the agent measurements. This careful scaling resulted in significant power savings—up to 12.51% in the demo—without sacrificing performance or stability. AVS Pro continues to adjust the voltage until the timing margins reach a safe minimum. If a sudden workload spike or voltage drop threatens to push the timing margins below a critical threshold, the system instantly increases the voltage to maintain stability and avoid potential failures. Once conditions stabilize, AVS Pro resumes voltage reduction, ensuring the chip operates at its most efficient power level.

This kind of solution is essential for industries such as AI, high-performance computing (HPC), data centers, mobile telecom, and automotive electronics.

How AVS Pro Works: Real-Time Monitoring and Adaptation

At the core of AVS Pro is its ability to monitor millions of logic paths in a chip in real time, providing a highly granular picture of each path’s proximity to a timing failure. The system continuously analyzes these margins and dynamically adjusts voltage levels to prevent failures caused by environmental factors, process variation, latent defects, noise, application stress, and aging effects. In contrast to traditional methods, which apply broad voltage guard bands for worst-case scenarios, AVS Pro tailors its response to the chip’s real-time conditions. By doing so, it optimizes power usage while ensuring that performance remains reliable even under challenging conditions, such as high temperatures or heavy workloads. When conditions are favorable, AVS Pro safely lowers the voltage, reducing power consumption and extending the device’s lifespan, by pushing out device wearout.

The system also accounts for process variations, ensuring each chip is calibrated individually to operate at its optimal voltage. Moreover, it monitors aging effects that slow down transistors over time, continuously adjusting voltage to compensate for degradation, thus preventing performance degradation or premature failure.

A Holistic, Closed-Loop Solution

The power of AVS Pro lies in its closed-loop integration of hardware and firmware. This tightly coupled system continuously monitors, analyzes, and adjusts voltage levels in real time, ensuring the chip remains within its optimal operating parameters. The system not only responds to current conditions but also learns from historical data, enabling it to predict future trends and make proactive voltage adjustments.

Fast-Response Protection and Adaptation

Another key feature of AVS Pro is its fast-response safety net. In dynamic environments where conditions can change rapidly, it is crucial for the system to make quick adjustments to avoid timing failures. AVS Pro’s closed-loop architecture provides real-time feedback between the hardware and firmware, allowing the system to instantly react to voltage fluctuations or workload spikes. By detecting potential failures early and taking corrective action immediately, AVS Pro ensures that even minor performance fluctuations are addressed before they escalate into more serious problems. This type of capability is essential for applications that demand high reliability, such as cloud computing, AI/HPC, and critical infrastructure.

Summary

The combination of real-time monitoring, adaptive voltage scaling, and a closed-loop architecture makes AVS Pro an ideal solution for designers and manufacturers looking to optimize their products for the next generation of computing technologies, where performance, power efficiency, and reliability are paramount.

The proteanTecs AVS Pro solution pushes the boundaries of adaptive voltage scaling and power optimization, delivering tangible benefits across a wide range of applications, from data centers to consumer devices. By ensuring each chip operates at the most efficient voltage level, AVS Pro maximizes performance while minimizing power consumption, paving the way for the future of high-performance semiconductor design.

Play with a Power Reduction ROI Calculator. (you have to scroll down a bit on the page)

Learn more about chip power reduction and data center economics.

Access a whitepaper on Power Performance Optimizer.

Visit proteanTecs.com to learn more about their various technology offerings.

Also Read:

proteanTecs Introduces a Safety Monitoring Solution #61DAC

proteanTecs at the 2024 Design Automation Conference

WEBINAR: Navigating the Power Challenges of Datacenter Infrastructure


The Next LLM Architecture? Innovation in Verification

The Next LLM Architecture? Innovation in Verification
by Bernard Murphy on 10-30-2024 at 6:00 am

Innovation New

LLMs have amazing capabilities but inference run times grow rapidly with the size of the input (prompt) sequence, a significant weakness for some applications in engineering. State space models (SSMs) aim to correct this weakness. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is Mamba: Linear-Time Sequence Modeling with Selective State Spaces. This was published in arXiv in 2023. The authors are from CMU and Princeton.

Judging by recent publications there is growing interest in a next step beyond transformer architectures, using an architecture building on state space models (SSMs). State space modeling is not a new idea; studies date back to the 1960s (Kalman filters) and are applied to time series analysis in many disciplines. In essence the method builds a model of internal state for a system based on equation-based constraints or statistical observations.

Research in SSMs for LLMs is quite recent, based on the idea that it should be possible to generate statistical models to mirror a more compact representation. Using such a model, inference can predict next items in a sequence faster than using brute-force attention recalculation on each next step. Research is already looking at applications in speech generation, DNA sequence analysis, computer vision, and of course LLM methods. While I haven’t yet found research on verification applications, it seems reasonable to assume that if ‘traditional’ LLMs can play a role in a verification problem, then SSM-based LLMs can play a more efficient role.

Paul’s view

The potential for LLMs to dramatically improve verification productivity is clear. How long it will take to and what kinds of tools will achieve it is actively debated. All EDA vendors including Cadence have significant investments in LLM-based tools.  This month we’re blogging about Mamba, a state space model (SSM) rather than an LLM. SSM research has been active for many years, but Mamba puts it in the spotlight as a serious contender to replace LLMs. While ours is not a blog for AI experts, if SSMs are to replace LLMs it would be a big deal for all of us, so we figured we should respect the moment and blog on Mamba!

As a simple teaser here, I like to compare LLMs and SSMs to control and datapath in chip design. Think of an LLM as a massive multi-billion node datapath. The inputs are every word in the prompt concatenated with every word that has been output so far. The output is the next word inferred. The width of the datapath explodes internally as very complex math is used to map numbers denoting each input word into scores for every possible output word, literally the entire English dictionary.

Alongside a datapath is control logic that gates and guides the datapath. In our world, control logic is highly sequential – state machines and control registers. Control logic up-levels datapath from a calculator into a reasoning thing that can take actions and make decisions.

In LLMs the control logic is not sequential. It’s a combinational “attention” weighting function that weights input words with other input words. In SSMs the control logic is a generic programmable (through training) state machine. Sure, it can do attention, but it can do many other things as well.

One key benefit of SSMs is that they don’t have limits on the size of input prompt. LLMs have an n-squared size/runtime problem since the attention function must compare every input word with every other input word. Inference blows up if the context window is too big. SSMs have no hardwired requirement to compare every input word to every other input word. Conceptually they just remember something about words input so far and use this memory to project weightings on the current input word.

The math and innovations behind SSMs go deep. If you are want to zoom in, this blog is a great place to start. Either way, let’s all stay tuned – dramatic improvements in verification productivity may well come through SSMs rather than LLMs. Imagine what we could do if the RTL and testbench for a full chip SOC and a full wavedump from its simulation could be passed as input to an SSM?

Raúl’s view

Inference in transformers has quadratic complexity arising from the self-attention mechanism: each token in the input sequence must compute its relevance (attention score) to every other token. This means that for an input sequence of length n the attention mechanism requires O(n2) computations. This makes inference expensive, and in practice a state-of-the-art LLM like OpenAI’s GPT-4 reportedly manages sequences of up to 32,000 tokens, while Google’s Gemini can handle up to 8,192 tokens. State Space Models (SSMs) have been developed to address transformers’ computational inefficiency on long sequences, but they have not performed as well as attention on important domains such as language.

The paper we review this month introduces Mamba, an architecture which incorporates a structured SSM to perform context-dependent reasoning while scaling linearly in sequence length, matching or outperforming transformers in many cases. Here is how it works.

A Structured SSM maps an input sequence xt to an output yt through a state ht as follows (discretized): ht = Aht-1 + Bxt, yt = Cht, where A, B, and C are matrices (to electrical engineers this is reminiscent of a Moore finite state machine). Such recurrent models are efficient because they have a finite state, implying constant-time inference and linear-time training. However, their effectiveness is limited by how well the state has compressed the context. This shortcoming is addressed by selection, which means making B and C also functions of the input and thus time varying. (*)

Mamba is an architecture that integrates a selective SSM with a Multi-Layer Perceptron (MLP) block. It achieves state-of-the-art results, often matching or surpassing Transformer models, in some cases using 3-4x fewer parameters (which is nice but not game changing). Additionally, it can handle longer context up to sequences of one million in length (this may allow to process very long strings, useful in EDA where design data is large). It certainly makes the point that Transformers are not the end of the road.

The paper, cited over 1000 times, spans 36 pages with 116 references and requires AI expertise to read. It covers various aspects of SSMs like architectures, dimensions, use of complex vs. real numbers, discretization, RNN gating mechanisms, and selection effects. Mamba is evaluated on synthetic tasks such as Selective Copying (filter out irrelevant tokens) and Induction Heads (retrieving an answer based on context, e.g., predict Potter after Harry), and on Language, DNA, and Audio modeling. Mamba is compared to other SSM architectures such as Hyena, SaShiMi, H3 and Transformer models such as Transformer++. The number of parameters is in the range of hundreds of thousands to one billion. The authors finish by suggesting that “Mamba is a strong candidate to be a general sequence model backbone”.

(*) The paper uses an overbar to indicate discretized A and B matrices, which I could not translate successfully from my Mac to the SemiWiki site. I used an underbar instead.


Defect-Pattern Leveraged Inherent Fingerprinting of Advanced IC Package with TRI

Defect-Pattern Leveraged Inherent Fingerprinting of Advanced IC Package with TRI
by Navid Asadizanjani on 10-29-2024 at 10:00 am

Article 1 figure 1 (1)

In the quest to secure the authenticity and ownership of advanced integrated circuit (IC) packages, a novel approach has been introduced in this paper that capitalizes on the inherent physical discrepancies within these components. This method, distinct from traditional strategies like physical unclonable functions (PUFs) and cryptographic techniques, harnesses the unique defect patterns naturally occurring during the manufacturing process. Counterfeiting involves unlawfully replicating authentic items for unauthorized advantages or financial gain, affecting diverse sectors such as automotive components, electronics, and consumer goods. Counterfeit integrated circuits (ICs) if sold in open market present a substantial risk due to their deviations in functionality, material composition, and overall specifications.

These illegitimate micro-electronic products, which might be mislabeled, reused, or cloned, fall into two primary categories: those with functional differences (like incorrect labeling or false specifications) and those that mimic the original function yet differ in technical aspects such as circuit timing or stress tolerance. Incorporating such counterfeit ICs into electronic devices can lead to significant adverse effects, undermining the devices’ quality, reliability, and performance. The stakes are especially high in military contexts, where the reliability and security of electronic systems are of paramount importance. According to a report from the International Chamber of Commerce , counterfeit trading globally is valued at up to 1 trillion USD each year, with the electronics sector making up a substantial share of this market.

The rise in counterfeit ICs has been linked to practices like outsourcing production to untrusted entities or due to the absence of proper life cycle management or traceability framework. Detection of counterfeits is perceived to be a more viable approach than prevention. Prevention requires extensive collaboration across borders, industries, and legal frameworks. Given the global nature of supply chains and the sophistication of counterfeit operations, prevention efforts can be difficult to implement and enforce consistently. However, the approach of detection offers flexibility, cost-effectiveness, and the ability to adapt to the changing tactics of counterfeiters. Despite extensive research into methods for detecting counterfeit ICs over the past decade, differentiating between new and used ICs, as well as spotting illegally produced or altered ICs, continues to be a significant challenge.

The introduction of sophisticated multi-die packaging technologies further complicates the issue of counterfeiting. These technologies which combine multiple chiplets into a single package increases the likelihood of counterfeit components being introduced into the system. The complexity of these systems  where chiplets from various sources are integrated into one package, makes verifying the authenticity of each component more challenging, raising the potential for counterfeit chiplets to affect the system’s overall functionality and security.

This new landscape of IC packaging necessitates a new direction for enabling reliable provenance. Provenance allows for the authentication of components at any stage of the supply chain. Buyers can verify whether an IC matches its documented history, ensuring its authenticity which reduces the risk of counterfeit ICs being accepted and used in critical systems. Provenance requires a method of identification in the die level, package level or board level. Historically, this is achieved by embedding some form of hardware identifier into the IC. These identifiers can be as simple as placing physical markers on the IC package or the die or storing manufacturing data in a non-volatile memory inside the chip or inserting additional circuitry to serve as an electrical watermark which makes it possible to trace the batch or wafer number of origin of a particular IC.

Hardware fingerprinting has emerged as a potent method for achieving provenance in the fight against counterfeit electronics. For example, physical unclonable functions (PUF) leverages the unique, manufacturing process variation of hardware components to provide a means of identifying and authenticating genuine devices throughout their lifecycle. However, despite being in spotlight for more than two decades, PUF based fingerprinting is yet to be widely adopted in industry. This can be attributed to a number of reasons including sensitivity to environmental conditions, risk of physical degradation over time, scalability and integration challenges within manufacturing processes, challenges in enrollment and response provisioning, high resource demands for error correction, susceptibility to advanced security attacks, reliability concerns across the device’s lifespan, and issues with standardization and interoperability.

In this work, the authors visit the existing challenges and limitations of traditional embedded fingerprinting and watermarking approaches and propose the notion of inherent hardware identifiers using Thermo-reflectance Imaging (TRI) as a new frontier of opportunity for effective security assurance of advanced IC packaging supply chain as categorized in Figure 2.

The key contributions of this work are summarized as follows: 1. Review existing embedded fingerprinting and watermarking. 2.Highlight the limitations and challenges of the existing approaches when applied in the context of security of chiplets and multi-chiplet systems or SiP. 3.Introduce the concept of inherent identifiers for fingerprinting and watermarking.4. Demonstrate TRI to harness inherent uniqueness to create fingerprints and watermarks.

Navid Asadizanjani
Associate Professor, Alan Hastings Faculty Fellow, Director, Security and Assurance lab (virtual walk), Associate director, FSIMEST, Department of Electrical and Computer Engineering, Department of Material Science and Engineering, University of Florida

Nitin Vershney
Research Engineer, Florida Institute for Cybersecurity Research

Also Read:

Electron Beam Probing: The New Sheriff in Town for Security Analyzing of Sub- 7nm ICs with Backside PDN

Navigating Frontier Technology Trends in 2024

PQShield Builds the First-Ever Post-Quantum Cryptography Chip


Podcast EP256: How NoC Tiling Capability is Changing the Game for AI Development with Andy Nightingale

Podcast EP256: How NoC Tiling Capability is Changing the Game for AI Development with Andy Nightingale
by Daniel Nenni on 10-29-2024 at 8:00 am

Dan is joined by Andy Nightingale, VP of product management and marketing at Arteris. Andy has over 37 years of experience in the high-tech industry, including 23 years in various engineering and product management positions at Arm.

Dan explores with Andy the significance of the recently announced tiling capabilities and extended mesh topology support for the Arteris network-on-chip (NoC) IP products. Andy provides an extensive overview of the benefits and impact of this new capability across a very broad range of markets and products.

He explains that that huge increase in AI development has put tremendous pressure on chip development across system scalability, performance, power and design productivity. Andy explains how Arteris NoC IP with the new tiling capabilities will have a substantial impact in all these areas across many applications and markets, in both the data center and the edge.

How specific market challenges are met with Arteris NoC IP is explained in detail in this informative discussion.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.