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The Intel Common Platform Foundry Alliance

The Intel Common Platform Foundry Alliance
by Daniel Nenni on 12-27-2024 at 6:00 am

Common Platform Alliance

When I do a root cause analysis of Intel’s problem it is very simple. If Intel wants to continue to be a leading-edge semiconductor manufacturer, they need to fill their fabs, all of their fabs. Clearly several things need to happen in order to do that but the one that most interests me is on the foundry side.

I think we can all agree that it is important for Intel to succeed. The United States needs to stay in semiconductor manufacturing and the world needs a second trusted foundry. After the formal Intel Foundry launch the first thing I thought of was for Intel to acquire GlobalFoundries to buy a channel and accelerate the business of filling fabs. GF is stuck at 14nm (which they licensed from Samsung) so it seemed like a good fit. Instead, Intel tried to buy Tower Semiconductor which I felt was a good move as well. The semiconductor foundry business is a marathon not a sprint, but this would have sped things up for sure.

Unfortunately, the sale of Tower Semiconductor to Intel did not go through due to regulatory hurdles. The acquisition was blocked by antitrust regulators in multiple jurisdictions, including the U.S. Federal Trade Commission (FTC) and Chinese authorities. To me this was political nonsense. The sale should have been approved to add a third horse in a two-horse race (TSMC and Samsung Foundry) for the greater good of the semiconductor industry.

Meanwhile, TSMC is racing forward with new fab partnerships that have changed the foundry business. In November of 2021 TSMC announced a partnership with the Japanese government, Sony, and DENSO (automotive) for fabs in Japan. The first one opened in February of 2024, making 28nm wafers. A second FinFET fab will be added for production in 2027.

TSMC also announced a partnership with Robert Bosch GmbH, Infineon Technologies AG, and NXP Semiconductors N.V. to establish the European Semiconductor Manufacturing Company (ESMC) in Dresden, Germany. A 28nm fab is being built with production starting in 2027 and I would guess more fabs will follow.

The other noteworthy foundry partnership is Rapidus in Japan. Rapidus was founded with backing from eight major Japanese companies: Denso, Kioxia, MUFG Bank, NEC, NTT, SoftBank, Sony, and Toyota. It is scheduled to be a 2nm fab, in partnership with IBM, with production starting in 2027. To me this was a missed opportunity for Intel.

I do not have high hopes for this partnership since it involves IBM technology. I remember back in 2004 when the Common Platform Alliance was launched. It was a partnership between IBM, Samsung, and Chartered Semiconductor (later acquired by GF). The goal was to standardize process technologies (PDKs) across their fabs so a customer could take one design to multiple manufacturing sources. This also enabled a shared ecosystem of EDA and IP which as we know is a big deal.

TSMC was rising in prominence with increased market share at 40nm, so this was a NOT TSMC competitive move at 28nm. Unfortunately, it used the IBM process recipe which historically is not high yielding technology. This was the HKMG gate-first versus gate-last controversy. Common Platform used IBM’s gate-first technology and did not yield. TSMC followed Intel with gate-last and won the 28nm node by a large margin and that was the end of the Common Platform Alliance.

As I have said before Intel needs to pivot. Fabs are getting more expensive to build and filling them has never been harder. Independently building the required ecosystem to compete with TSMC is another major financial challenge. Launching an Intel Common Foundry Platform Alliance and providing other foundries (Samsung, UMC, Tower Semiconductor, GlobalFoundries, etc…) unified access to Intel manufacturing can fill the Intel fabs and packaging facilities, absolutely.

Also Read:

What would you do if you were the CEO of Intel?

Intel Presents the Final Frontier of Transistor Architecture at IEDM

Intel – Everyone’s Favourite Second Source?


CEO Interview: Marc Engel of Agileo Automation

CEO Interview: Marc Engel of Agileo Automation
by Daniel Nenni on 12-26-2024 at 10:00 am

Marc Engel CEO Agileo Automation

Marc Engel has served as the CEO of Agileo Automation for the past 15 years. Agileo specializes in software solutions for controlling semiconductor production equipment and connecting tools to MES systems using SECS/GEM and OPC-UA standards. Marc started his extensive 25-year engineering career in software development on the ground setting up production machines in wafer fabs in Germany, Taiwan, and China. He has worked for companies such as RECIF Technologies, Motorola Mobile Services, Akka Technologies, and Atos Origin. Marc holds a degree in engineering and industrial automation from the Institut National des Sciences Appliquées (INSA, National Institutes of Applied Sciences) in Toulouse, France.

Tell us about your company

Founded in Poitiers, France, in 2010, Agileo Automation specializes in software solutions for controlling production equipment in the semiconductor industry and connecting tools to the company’s manufacturing execution system (MES) using widely adopted industrial standards. Our expertise lies in guiding customers—whether start-ups or established manufacturers—through the phases of increasing the production readiness level of their equipment, helping them reduce time-to-market while maintaining high standards of efficiency and reliability. At the heart of Industry 4.0, our A²ECF-SEMI framework provides a robust foundation for developing equipment controller software, leveraging SEMI’s SECS/GEM and GEM300 standard suites and a portfolio of drivers for off-the-shelf semiconductor equipment, such as wafer handlers or load ports from multiple vendors. As a member of SEMI and the OPC Foundation, Agileo Automation is a key contributor to the development and integration of industry standards, such as SEMI standards and OPC Unified Architecture (OPC-UA).

What problems are you solving?

Think of us as the automated version of a Windows operating system for a computer. We develop the brain behind semiconductor production equipment. We help start-ups embrace the world of automation for their fab equipment, a world unfamiliar to them, as they often come from the research lab community. They develop innovative and complex production equipment, but they have limited knowledge of automation technologies needed to integrate it into the operational environment of a real-world manufacturing wafer fab. We help them prepare the machines to connect with commercially available robots, manage the operator interface, integrate with the company’s IT systems like MES, etc., ensuring a much faster time-to-market.

What application areas are your strongest?

The semiconductor industry is our primary application market. Original equipment manufacturers (OEMs) work with a wide variety of clients, wafer sizes, and carrier types found in advanced packaging facilities. We provide flexible software solutions to their complex integration challenges, including specialized advice on selecting robotic systems. We have done this kind of work for a French company, UnitySC, which works with a wide variety of semiconductor materials and diverse wafers formats. Their loading process requires specific equipment front-end modules (EFEMs), traditionally controlled using manufacturer-developed software. With our A²ECF-SEMI framework, we simplified the integration of EFEMs into UnitySC’s process modules, reducing their dependency on subsystem suppliers, automating the loading process and fab host interface, and solving complex integrations. For Soitec, by leveraging the built-in architecture of our A²ECF-SEMI framework, we developed a digital twin for the integration of a new automated SOI wafer loading robot into its production lines based in France and Singapore.

What keeps your customers up at night?

Our clients are often on tight deadlines, which can be easily disrupted by material sourcing delays or unforeseen internal process challenges. Our team is used to developing software in parallel to production machines being designed and built. A key aspect of our value proposition is minimizing the time spent on software development within the critical path of overall equipment planning. We develop our own digital twins and decouple hardware and software. Remember that some of this manufacturing equipment is shipped to the other side of the world where it not only has to be installed but also has to be maintained. Our software solutions take this kind of use case into account from the very beginning to solve issues remotely, ensuring full confidence in the quality of the software modifications made.

What does the competitive landscape look like and how do you differentiate?

There are a handful of competitors on the global scene who provide offerings similar to ours. I think what sets us apart is the overall customer experience we provide – our 20 years of global experience, our combined equipment manufacturing and software development expertise, our deep integration track record, our comprehensive suite of customizable solutions, and our service excellence. The world’s most reputable semiconductor companies trust Agileo Automation to solve their production equipment control and connectivity challenges. Our global installed product base includes over 900 controlled/connected equipment of more than 60 different types by two of the top 10 semiconductor OEMs, five in the top 50, and across more than 65 wafer fabs worldwide. A large part of our business actually comes from client referrals within the industry.

The make-or-buy decision is a particularly challenging dilemma for many of our customers. Some software solutions can certainly be developed internally, but they will likely end up being more expensive and take significantly longer to implement. Developing software at this level takes a high level of experience and maturity. Outsourcing complex software development will eventually be cheaper and lead to a faster time-to-market.

What new features/technology are you working on?

In November 2024, we launched our E84 PIO Box, a new handheld device that offers a new lightweight interface for fab staff to test semiconductor equipment software for compliance with SEMI’s E84 and GEM300 standards suite for automatic carrier delivery. It improves the readability, identification, and validation of E84 signal exchanges and functional aspects in cleanrooms or workshops. Integrated with our Speech Scenario software that emulates the fab host and validates the SECS/GEM interface with predefined test scenarios, the E84 PIO Box can easily emulate automated carrier delivery systems such as overhead hoist transport (OHT) or automated guided vehicles (AGV). It can detect non-compliance and other functional issues thanks to its close alignment with SEMI’s E84 standard.

Coming up next are new developments on the SEMI Equipment Data Acquisition (EDA) standards front. We are proud to have recently achieved a significant milestone. Our team – one of only four worldwide – successfully conducted its first SEMI EDA Freeze 3 standards interoperability tests focusing on connectivity and data acquisition with our semiconductor industry peers, including software vendors and OEMs. Our team validated key functions such as gRPC metadata usage, security administration, and data collection plan management. EDA Freeze 3 brings a substantial leap in semiconductor equipment performance through the adoption of gRPC instead of SOAP/XML, enabling reduced latency and increased data collection throughput.

What is the best advice you would give to semiconductor OEMs and equipment manufacturers when it comes to their fab automation systems?

Don’t underestimate the crucial role software plays in the deployment of production equipment. Just like the mechanical components, software requires thorough preparation, particularly regarding interfaces with operator and IT systems, to ensure the machine performs as promised within the highly complex and expensive fab manufacturing process. For example, moving a wafer from point A to point B for processing may seem straightforward at first glance; however, it involves integrating several systems from multiple suppliers, ensuring compliance with international standards, accounting for the future maintenance of equipment worldwide, ensuring scalability across the equipment family’s lifecycle, and addressing numerous other factors. These requirements demand a robust software architecture, a deep understanding of the equipment use cases, as well as qualified and experienced staff capable of simplifying complex processes to deliver peace of mind to customers.

How can customers engage with your company?
Agileo Automation – https://www.agileo.com/en
References:
SECS/GEM – https://secsgem.eu/
OPC Foundation – Home Page – OPC Foundation
Also Read:

CEO Interview with Dr. Dennis Michaelis of GEMESYS

CEO Interview: Slava Libman of FTD Solutions

CEO Interview: Caroline Guillaume of TrustInSoft


CEO Interview with Dr. Dennis Michaelis of GEMESYS

CEO Interview with Dr. Dennis Michaelis of GEMESYS
by Daniel Nenni on 12-26-2024 at 6:00 am

Dr. Dennis Michaelis, CEO of GEMESYS

Dr. Dennis Michaelis is the founder and CEO of the AI chip start-up. With a Ph.D. in Bio-Inspired Computing at the Purdue University in Indiana and a background in electrical engineering, he brings a unique blend of technical expertise and social commitment to the company. His previous role as Regional Director for Anonymous for the Voiceless highlights his leadership skills and dedication to ethical causes, as he was responsible for over 100 local groups in DACH, each with hundreds of members.

His professional expertise is underpinned by a large number of scholarships, his Cum Laude dissertation and the award of the “VDE Prize for Outstanding Academic Achievement” from the German Association for Electrical, Electronic & Information Technologies (VDE) for his Master’s thesis.

Tell us about your company?

GEMESYS is a cutting-edge technology company based in Bochum, Germany, focused on revolutionizing AI hardware. We’ve developed a novel analog chip architecture using memristive functionality, which enables ultra-efficient, real-time neural network processing directly on edge devices.

Our technology is designed to address some of the biggest challenges in the industry, like energy efficiency, performance at the edge, and data privacy. By processing AI workloads natively in hardware, we achieve dramatically lower power consumption and latency compared to traditional digital solutions. This makes our chips ideal for applications in industries like consumer electronics, automotive, healthcare, and IoT.

We’re backed by a strong combination of investors from Europe (Amadeus APEX Technology Fund, Atlantic Labs, NRW.Bank), Silicon Valley (Plug and Play Tech Center), and Japan (Sony Innovation Fund), and have recently secured an $9.1M pre-seed round, including government support. At our core, GEMESYS is about creating intuitive, sustainable technology that simplifies and enhances everyday life. Our vision is to lead the shift toward smarter, more connected edge devices, enabling our customers to innovate faster and more effectively.

What problems are you solving?

At the moment, training a single complex AI model, such as ChatGPT, consumes as much electricity as a coal-fired power plant produces. This is also reflected in the huge data centers that are constantly in operation. If this trend continues, the cost of training a single neural network could exceed the economic power of entire countries as early as 2026. GEMESYS is developing a new type of hardware solution for decentralized AI applications. At its heart is an analog AI chip that is modeled on the human brain and processes data directly at the source, the so-called edge devices. For the first time, this enables local training of AI models in addition to the local execution of AI, which reduces network loads, improves data protection and promotes scalability. Thanks to its analog approach, the GEMESYS chip offers unparalleled energy efficiency and opens up new possibilities for Internet of Things applications and the networking of numerous devices.

What application areas are your strongest?

Our technology is particularly strong in application areas where energy efficiency, real-time performance, and data privacy are critical. In consumer electronics, for instance, our chips power wearables and smart home devices, enabling real-time AI processing without draining batteries.

In automotive, we support advanced driver-assistance systems and autonomous vehicles, delivering low-latency AI capabilities that enhance safety and performance while meeting strict energy and reliability demands.

In healthcare, our chips enable portable medical devices and diagnostics tools to process data securely on-device, ensuring privacy and reliability, especially in remote environments.

We’re also making a significant impact in industrial IoT, powering factory automation, predictive maintenance, and edge monitoring systems where energy efficiency and local decision-making are essential.

Finally, in smart cities, our technology supports applications like environmental monitoring, reducing cloud dependency while providing fast, localized AI.

These diverse areas highlight how GEMESYS is driving smarter, more sustainable edge solutions across multiple industries.

What keeps your customers up at night?

Many of them are kept up at night by the need to achieve more with less—delivering high-performance AI capabilities while staying within strict power and cost constraints. For those working on edge devices, power efficiency is critical, especially for battery-powered applications where every milliwatt counts. They also need real-time AI processing without relying on cloud connectivity, which introduces latency, security risks, and compliance challenges.

Beyond that, cost pressures are a constant concern. Scaling AI capabilities while managing manufacturing costs and maintaining competitive pricing is a balancing act. Add to that the growing focus on sustainability—companies are under immense pressure to reduce their carbon footprints and meet ESG goals. AI solutions that aren’t energy-efficient simply won’t align with these priorities.

What does the competitive landscape look like and how do you differentiate?

On one side, we face established players in the semiconductor and AI hardware space, that focus on both inferencing and training of AI models in data centers such as NVIDIA, Qualcomm, and Intel. On the other, a wave of emerging startups is exploring alternative approaches like spiking neural networks or crossbar-arrays to enable inferencing on the edge.

What sets GEMESYS apart is our fundamentally different approach. Most competitors are focused on squeezing incremental gains from digital architectures that were never designed for the inherent demands of AI at the edge. These architectures struggle with energy efficiency and latency while relying heavily on cloud processing.

At GEMESYS, we’re rewriting the rules with our analog chip architecture, leveraging memristive functionality to process neural networks natively in hardware. This allows us to achieve ultra-low power consumption and real-time performance—ideal for edge devices. While many competitors are optimizing traditional solutions, we’re offering a breakthrough technology that aligns perfectly with the industry’s future needs for energy-efficient, scalable, and secure AI processing.

What new features/technology are you working on?

While our core technology—an analog chip architecture with memristive functionality—already sets us apart, we’re working on several advancements to further enhance its capabilities.

One key area of focus is expanding the adaptability of our architecture to support more diverse AI models and applications. This involves optimizing our chips to handle increasingly complex neural networks while maintaining the same ultra-low power and high-speed performance that define our technology.

We’re also developing features that improve on-device learning. Traditionally, AI models are trained in the cloud and then deployed to devices, but this approach has limitations in dynamic environments. With on-device learning, our chips can adapt to new data in real-time (continuous learning), opening up possibilities for smarter, more personalized edge devices.

Another exciting development is in the area of robust and secure AI. As data privacy becomes an ever-greater concern, we’re enhancing our architecture to ensure secure, local data processing without compromising performance. This is especially critical in industries like healthcare, automotive, and industrial IoT.

Finally, we’re exploring ways to integrate our chips into broader ecosystems, ensuring seamless compatibility with existing software frameworks and enabling end-to-end solutions for our customers. These advancements reflect our commitment to not only delivering cutting-edge hardware but also enabling our customers to stay ahead in an increasingly connected and intelligent world.

How do customers normally engage with your company?

We design and develop cutting-edge analog chips with memristive functionality, which we license to device manufacturers and system integrators. This licensing model allows us to scale efficiently, enabling our customers to integrate our technology into their products across industries like consumer electronics, automotive, healthcare, and industrial IoT.

Additionally, we generate revenue by providing tailored solutions and support for our first pilot customers, including co-development partnerships for custom applications and optimization services. This ensures our technology meets the specific needs of our customers’ use cases while also fostering long-term collaboration.

Also Read:

CEO Interview: Slava Libman of FTD Solutions

CEO Interview: Caroline Guillaume of TrustInSoft

CEO Interview: Mikko Utriainen of Chipmetrics


What would you do if you were the CEO of Intel?

What would you do if you were the CEO of Intel?
by Daniel Nenni on 12-24-2024 at 10:00 am

Intel BSPD Power Via

One of the most enduring threads in the SemiWiki forum is What would you do if you are the Intel CEO? There are currently 128 responses and more than 45,000 views. It was originally posted March 13th, 2015, after Brain Krzanich was given the CEO position. A different time for sure but an interesting read and the responses keep on coming.

One thing that struck me while watching the keynotes at IEDM is that Intel made a big change in the last few years in regard to transparency. I remember back when Intel 14nm brought FinFETs to market, we were all pleasantly surprised. Intel kept that secret like many other technology leaps that made Intel a semiconductor legend. It took the rest of the industry years to catch up and even today Intel 14nm is one of the best 14nm implementations the industry has to offer.

After the IEDM presentations by Intel and TSMC, the transparency differences were quite obvious. TSMC releases just enough information and Intel releases much more. While we all scream for transparency, in this ultra-competitive market it may not be a great idea.

The latest example is Back Side Power Delivery (BSPD). Intel first announced it at the 2022 IEEE VLSI Symposium in great detail.  PowerVia was highlighted as a critical innovation to complement Intel’s gate-all-around transistor architecture (RibbonFET) and will be used first for internal products then offered to foundry customers. Here is the paper summary:

[T6-1] Intel PowerVia Technology: Backside Power Delivery for High Density and High-Performance Computing.

This paper presents a high-yielding backside power delivery (BPD) technology, PowerVia, implemented on Intel 4 finFET process. PowerVia more directly integrates power delivery to the transistor as compared to published buried power rail schemes, enabling additional wiring resources on front side for signal routing. A fabricated E-core with >90% cell utilization showed >30% platform voltage droop improvement and 6% frequency benefit compared to a similar design without PowerVia. Transistor performance, reliability, and fault isolation capability is detailed.

The problem of course is that TSMC is a fast follower. Not only are they a fast follower, TSMC has the support of the largest ecosystem known to the semiconductor industry.

At the 2024 North America Technology Symposium TSMC announced Super Power Rail for delivery in 2026 with the A16 node. The Super Power Rail, not unlike Intel PowerVia, enhances power efficiency and signal routing by dedicating front-side resources specifically for signals, aiming to improve logic density and performance for HPC applications. This is from the TSMC website:

TSMC A16™ technology is the next nanosheet-based technology featuring Super Power Rail, or SPR.

SPR is an innovative, best-in-class backside power delivery solution. It improves logic density and performance by dedicating front-side routing resource to signals. SPR also improves power delivery and reduces IR drop significantly. Most importantly, the novel backside contact scheme we developed preserves gate density, layout footprint, and device width flexibility, thus achieving best density and performance simultaneously, and we believe it is a first in the industry.

A16 is best suited for HPC products with complex signal routes and dense power delivery network, as they can benefit the most from backside power delivery. Compared with N2P, A16 offers 8%~10% speed improvement at the same Vdd, 15%~20% power reduction at the same speed, and 1.07~1.10X chip density.

Who Will Win?

It will be another battle of the technology titans: Intel PowerVia versus TSMC Super Power Rail. I have no doubt that Intel will be first with PowerVia on internal 18A products. I do believe that TSMC Super Power Rail will be the overall winner with foundry customers.

Which implementation will be best? We really won’t know until the chips fall but my guess is that they will be competitive. Intel should have the lead since they are designing PowerVia with specific chips in mind while TSMC’s Super Power Rail will have a broader application. I do believe, however, that in time the TSMC BSPD implementation will surpass Intel’s due to the driving force of the TSMC ecosystem.

Had Intel waited for chips to be in production before bragging about BSPD it would be a much different race, absolutely.

In 1996 former Intel CEO Andy Grove published the renowned book Only the Paranoid Survivewhich is an inside look at Grove’s management style and experiences at Intel. The key theme for me was that Andy believed in a healthy amount of paranoia to keep leaders vigilant, proactive, and prepared for the many disruptions of the semiconductor industry. Hopefully the new Intel CEO will have a healthy amount of paranoia.

Also Read:

Intel Presents the Final Frontier of Transistor Architecture at IEDM

Intel – Everyone’s Favourite Second Source?

An Invited Talk at IEDM: Intel’s Mr. Transistor Presents The Incredible Shrinking Transistor – Shattering Perceived Barriers and Forging Ahead


Stochastic Pupil Fill in EUV Lithography

Stochastic Pupil Fill in EUV Lithography
by Fred Chen on 12-24-2024 at 6:00 am

Exposing EUV

Pupil fill tradeoff again

EUV lithography continues to be plagued by its stochastic nature.

This stochastic nature is most clearly portrayed by the random fluctuation of the absorbed photon number at a given location. For example, consider an absorbed dose of 10 mJ/cm2 amounts to 6.8 photons of energy 92 eV absorbed in a square nanometer of EUV resist. The standard deviation of the absorbed photon number in that area, according to Poisson statistics, is 2.6 photons, basically 38% of the dose. This “shot noise” leads to locally reduced or increased dose, which in turn can lead to defects. This frequently limits the allowed dose range in EUV lithography.

An alternative way to visualize the stochastic imaging is to realize that each location is being illuminated differently. EUV lithography systems project images from a mask onto a wafer after undergoing demagnification. Rather than consistently illuminating every location with a prescribed set of angles incident onto the mask, there is a randomness in the angle prescription itself.

Figure 1 shows that even when the targeted set of incident angles forms two leaf shapes in the pupil plane, corresponding to a certain number of photons for each angle channel, the actual photon distribution among the channels is stochastic, with some channels getting no photons, others getting an excessive number. The absorbed dose here is 8.36 mJ/cm2, corresponding to the 14% absorption of a 60 mJ/cm2 dose by a 30 nm thick resist with an absorption coefficient of 5/um.

Figure 1. Stochastic view of the dipole leaf illumination shape targeted for 30 nm pitch on an 0.33 NA EUV system. 8.36 mJ/cm2 absorbed into a 3 nm x 3 nm area. The source is divided into 152 points, each corresponding to 1/11 of the NA, each channeling 0.055 mJ/cm2 to be absorbed. The plotted numbers are the number of 92 eV EUV photons channeled at the particular incident angle targeting the 3 nm x 3 nm pixel. Left: targeted pupil shape. Right: example of actual distribution of absorbed photons corresponding to each incident angle.

Thus, although the uniform dipole leaf illumination is prescribed for 30 nm line pitch, the actual illumination is effectively a randomly fluctuating subset of this shape, with some angles getting excessive brightness. This results in random image shifts.

Those familiar with using a lithography system may realize that the number of illuminator angle channels affects the degree of fluctuation at a given dose. Hence, reducing the number of channels, or reducing the pupil fill, should be able to alleviate this effect. Through Figures 2 and 3, we get an idea of this improvement.

Figure 2. Stochastic view of the double slot illumination shape targeted for 40 nm pitch on an 0.33 NA EUV system. 10.9 mJ/cm2 absorbed into a 4 nm x 4 nm area. The source is divided into 76 points, each corresponding to 1/11 of the NA, each channeling 0.143 mJ/cm2 to be absorbed. The plotted numbers are the number of 92 eV EUV photons channeled at the particular incident angle targeting the 4 nm x 4 nm pixel. Left: targeted pupil shape. Right: example of actual distribution of absorbed photons corresponding to each incident angle.

Figure 3. Stochastic view of the small dipole illumination shape targeted for 40 nm pitch on an 0.33 NA EUV system. 10.9 mJ/cm2 absorbed into a 4 nm x 4 nm area. The source is divided into 12 points, each corresponding to 1/11 of the NA, each channeling 0.906 mJ/cm2 to be absorbed. The plotted numbers are the number of 92 eV EUV photons channeled at the particular incident angle targeting the 4 nm x 4 nm pixel. Left: targeted pupil shape. Right: example of actual distribution of absorbed photons corresponding to each incident angle.

With the much lower (~3%) pupil fill shown in Figure 3, there is less obvious stochastic distortion of the illumination shape from the target prescription. However, such a low pupil fill means much of the light from the source is cut out by the EUV illuminator itself, forcing the stage to slow down to accumulate the correct dose per unit area. This limits the system throughput severely. While a higher pupil fill had the traditional advantage of imaging a less restricted variety of pitches and shapes, stochastic considerations once again force yet another tradeoff.


Consumer memory slowing more than AI gaining

Consumer memory slowing more than AI gaining
by Robert Maire on 12-23-2024 at 10:00 am

Micron Idaho Fabs
  • Consumer memory slowing more than AI gaining causing weakness
  • HBM sold out for 2025- HBM is most of Capex- NAND near zero
  • Big miss on Q1 guide crushes stock on disappointment
  • Positive for Nvidia- Negative for Broadcom/Qualcomm
Micron – AI is wonderful & growing out of bounds while consumer sucks

Micron reported in line results of $8.7B in revenues with $1.79 in EPS which met expectations. However, guidance was poor at $7.9B+-$200M and EPS of $1.43+-$0.10.

Compared to street expectations $8.97B and EPS of $1.97, this is a large disappointment dropping the stock by 14% on the day

Dichotomy between AI and everything else grows

AI is nothing short of fantastic, great margins, super growth, fantastic outlook with expectations of quadrupling over the next several years, Micron sold out for all of 2025 (much like Nvidia)

However, consumer facing memory applications such as PCs and mobile phones are weak, and NAND is absolutely trashed with severe cuts in capex and technology increases in an attempt to slow bloated inventories that trash pricing.

So, very simply put its a race between the declining fortunes of consumer memory and the increasing fortunes of AI memory and unfortunately consumer memory is declining faster than AI is increasing as AI memory, HBM is still a relatively small percentage of overall business. Thus, even though as a percentage, AI is growing faster it is an overall smaller percentage of business.

HBM business doubled for Micron in the quarter but that was still far from enough to offset other memory declines expected.

Server was up 46% sequentially while mobile was down 19% sequentially and embedded down 10% sequentially

Weak Auto and China add to woes

On top of general consumer weakness there was weakness in increasing inventories in auto related sales.

China which has been an ongoing issue will worsen as Chinese competitors take more of the low end of the memory market in both NAND and DRAM for the domestic market leaving Micron with a smaller overall share

2025 capex will be $14B +- $500M

Capex was $3B in the quarter with the “vast majority” of spend focused on the winner, HBM and what sounds like near zero dollars on the loser, NAND.

Micron is slowing NAND wafer starts and slowing technology enhancements that add to bit growth to try and reign in bloated inventories that crush prices

Seasonality doesn’t help

Adding to the weakness is the normal seasonal weakness of the Q1 postpartum depression after the Christmas & Holiday season of peak consumer business. Not only does the current holiday season not look so hot but the slowness after the holidays will likely make matters worse.

The Stocks

Frankly, we think Micron’s stock deserves to get a bit trashed as expectations had grown way out of proportion with reality. AI fever had taken over even though we continue to point out that AI is not big enough to offset the weakness in the largest part of the business.

Maybe in a few years’ time if HBM becomes a significant portion it may help more but by that time it will also become more of a commodity.

We think that there is perhaps more of a lesson for collateral stocks.

We would think of a pair trade like going long Nvidia (which is on sale recently) while shorting Broadcom and Qualcomm.

Micron’s report points out that there is zero weakness, only strong, sold outgrowth in AI while consumer and auto related are weaker and likely getting weaker with bloating inventories in the near term.

Our view is that Micron being down 15% to 20% is not unreasonable as reality sets in.

In other collateral concerns, we see less of an impact on the semiconductor equipment stocks as Microns Capex is still strong at $30B just shifted 180 degrees to focus solely on HBM at all costs.

The “tale of two cities” between “the best of times and the worst of times” gets bigger as consumer slows more. We are somewhat surprised that Micron management missed this somewhat obvious shift in sentiment that has been going on for a while.

Unlike in France this disregard of reality only winds up in the guillotine for the stock price.

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies.
We have been covering the space longer and been involved with more transactions than any other financial professional in the space.
We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.
We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

AMAT has OK Qtr but Mixed Outlook Means Weaker 2025 – China & Delays & CHIPS Act?

More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay


Intel Presents the Final Frontier of Transistor Architecture at IEDM

Intel Presents the Final Frontier of Transistor Architecture at IEDM
by Mike Gianfagna on 12-23-2024 at 6:00 am

Intel Presents the Final Frontier of Transistor Architecture at IEDM

IEDM was buzzing with many presentations about the newest gate-all-around transistor. Both Intel and TSMC announced processes based on nanosheet technology. This significant process innovation allows the fabrication of silicon RibbonFET CMOS devices, which promise to open a new era of transistor scaling, keeping Moore’s Law alive. It seems fitting that Intel should be leading this charge and the company’s innovation was on display at IEDM. The company presented “Silicon RibbonFET CMOS at 6nm Gate Length”. A summary of these results are shown in the graphic above. This technology was referred to as the last innovation for current transistor design. So, let’s examine how Intel presents the final frontier in transistor architecture at IEDM.

The Presenter

Dr. Ashish Agrawal

The work presented was a collaboration of many folks from Intel Foundry Technology Research and Intel Foundry Technology Development, both in Hillsboro, Oregon. The presentation was given by Dr. Ashish Agrawal, senior device engineer.

Ashish has been with Intel for over 10 years. His areas of focus include R&D in semiconductor front-end materials and physics, electrical characterization using his background in device physics and material science and design-technology co-optimization (DTCO). The DTCO work includes analysis of novel materials, devices, and architectures for future scaled technology nodes.

Ashish presented a lot of results for this new transistor architecture. Let’s examine some of what was presented.

Some Results

To accurately characterize true behavior of the RibbonFET at extreme gate length scaling, a novel, single nanoribbon (1NR) flow was developed in which source/drain are disconnected from the subfin. This ensures accurate knowledge of transistor dimension data and precise probing of NR characteristics.

TEM micrograph

A TEM micrograph the device is shown to the right. With Si/SiGe Epi stack innovation, the subfin is disconnected successfully from S/D epi in addition to healthy and uniform inner spacer above and below the NR.

Ashish explained that gate length scaling below 10nm was achieved by innovation in gate lithography and a dummy polysilicon etch process. He went on to say that source drain junctions and their doping profiles carry a new meaning and new implications at the small gate lengths being used in this work. Intel has done substantial work on the source/drain junctions to optimize for engineered short-channel effects and achieve the best performance possible from this highly scaled device.

Ashish also pointed out that, at a 6nm gate length you don’t have enough room to put in Hi-K, and di-pole and a work function to achieve the Vt target. So, for this technology, a work function was optimized and engineered to achieve a low Vt close to the target. Process innovation was critical to achieve effective scaling below a 10nm gate length.

As the gate length is scaled below 10nm, the source/drain doping profile in the tip region needs to be carefully examined. Highly diffused junctions not only degrade short channel effects but also result in remnant doping in the channel which degrades performance due to poor mobility from ionized impurity scattering. In the figure below, (a) shows peak Gmlin for LG=18nm and LG=100nm, highlighting a 34% gain in Gmlin with optimized junction Process B at short LG whereas long LG transconductance is matched. (b) shows drain induced barrier lowering (DIBL) vs. process indicating improved short channel effects with an optimized Process B junction profile. (c) shows Rext vs. process showing matched Rext for both processes and a very low value indicating no penalty from junction optimization.

Measurements across process

Ashish presented many more results that demonstrated effective scaling all the way down to a gate length of 6nm and nanoribbon thickness of 1.5nm. He concluded by saying that this work paves the path for continued gate length scaling, which is a cornerstone of Moore’s Law. And that’s how Intel presents the final frontier in transistor architecture at IEDM.

Also Read:

Intel – Everyone’s Favourite Second Source?

An Invited Talk at IEDM: Intel’s Mr. Transistor Presents The Incredible Shrinking Transistor – Shattering Perceived Barriers and Forging Ahead

What is Wrong with Intel?

 


Podcast EP267: The Broad Impact Weebit Nano’s ReRAM is having with Coby Hanoch

Podcast EP267: The Broad Impact Weebit Nano’s ReRAM is having with Coby Hanoch
by Daniel Nenni on 12-20-2024 at 10:00 am

Dan is joined by Coby Hanoch, Coby joined Weebit Nano as CEO in 2017. He has 15 years of experience in engineering and engineering management roles, and 28 years of experience in sales management and executive roles.

Coby describes the impact Weebit Nano’s ReRAM technology is having for: Embedded non-volatile memory, in many markets and applications including superior speed and endurance, lower power, a less expensive manufacturing process and the ability to scale well with the rest of the design on-chip. Power management, automotive, AI and edge-based inference and even aerospace applications.

Coby also describes some of the work underway at Weebit Nano to continue to move ReRAM technology into the mainstream.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


If you believe in Hobbits you can believe in Rapidus

If you believe in Hobbits you can believe in Rapidus
by Robert Maire on 12-20-2024 at 6:00 am

Rapidus Fab Japan

– Semicon Japan super crowded but outlook still uncertain/muted
– Slow analysts finally capitulate on weakening 2025 WFE outlook
– Article confirms our view on chip equip lobbying for China sales
– TSMC continues dominate, China slows, Samsung/Intel weak

Semicon Japan crowded but muted

We attended Semicon Japan last week and it was super crowded, however the overall tone was muted as most companies were concerned about overall spending weakening especially at Samsung and Intel.

Semicon Japan is more like what Semicon West used to be. Actual tools and vendors on the show floor rather than ensconced in hotel rooms away from the public. Plenty of meaningful conversations about technology and tools.

Everyone wants to be linked to AI in some way even though the semiconductor equipment tools have zero to do with whether they are building an AI chip or a video game chip, just microscopic manipulation of materials.

Seems like China continues to slow as they have enough equipment in warehouses to last for years. Whatever sanctions are on the way, they are too little and too late to be effective.

Rapidus de minimis

Rapidus, the Japanese government sponsored plan to bring Japan back into the semiconductor race had a large booth with lots of conceptual drawings of the planned fab.

Rapidus looks like a giant-sized Hobbit House, with a rolling, grassy, environmentally friendly roof, obviously to try to disguise what is an otherwise an ugly giant factory.

Much as the Hobbit World is a fantasy, we think Rapidus is quite the fantasy. IBM is one of the main partners and they haven’t been a commercial producer of chips in decades. Most of the other main players are close to retirement and haven’t been deep in the industry since Japan was a power player, also decades ago.

The bigger issue we see is that both Samsung and Intel which are several generations behind TSMC are struggling not to fall too far behind, yet Rapidus is many times further behind and will somehow miraculously jump over Samsung and Intel to catch up with TSMC? Good luck with that. Sounds a lot like the 5 nodes in 4 years we heard before.

But maybe if you believe in Hobbits you can believe in Rapidus.

Big, slow, investment house analysts finally capitulate on slowing 2025 WFE

Analysts from Citibank, Deutsche Bank and Bernstein finally got the memo that semiconductor spending in 2025 will be weak at best. They are all finally cutting 2025 outlooks after reality dawned on them.

This is something we have been saying for well over a year as the majority of the industry remains weak with a weakening China. We have pointed out time and again that only the bleeding edge, and most specifically AI is strong, both in logic and memory.

In our note a month ago we said “There had been an initial, more positive view by many analysts which now appear too optimistic and will have to be trimmed to be more conservative, to the view we have long held, of a slower recovery with more lumps and bumps along the way”

We remain very concerned about all the Chinese capacity coming on-line in the middle and trailing edge of the chip market flooding capacity and driving down pricing.

China has yet to have a significant impact on memory, but that’s coming too as they come up the technology curve very quickly

Chip equip companies lobby congress to help China advance chips

We have mentioned in many of our notes that US semiconductor equipment companies spend tens of millions of dollars lobbying US lawmakers to keep their lifeline of China sales flowing.

The New York times recently affirmed our view of the very strong lobbying on the part of the three major US semiconductor equipment makers: Applied Materials, Lam and KLA.

Link to NY Times article

We find its obviously hugely hypocritical to dilute or prevent sanctions on China, based on the lobbying of equipment firms yet support the CHIPS act whose aim is to prevent China’s dominance of the semiconductor industry.

It would a very interesting study to see which members of the house and senate took money from the equipment companies to prevent sanctions on China yet supported the opposite position by voting for the CHIPS Act which does the opposite.

Obviously, politicians are almost always hypocritical and some of the equipment companies are also hypocritical by lobbying to sell more to China while holding out their hand for CHIPS Act funding. Not surprising behavior.

The Stocks

Obviously, the stocks have been a bit unstable and will likely remain so given the downgrades from the larger sell side analysts who are capitulating.

Micron is a focus that may determine some near-term sentiment. Nvidia is somewhat stuck in the mud for a while now, waiting to break free but the broader negative tone appears to be holding it back.

We may be going into a wait and see period waiting to see what the new administration does with tariffs and other potential restrictions.

In our view, it’s still very much unclear which way the new administration will go and if semiconductors will be a priority.

We also remain unclear about the incoming administration and the CHIPS Act. Even though the current administration has rushed to finalize deals before they leave town, we think that this doesn’t mean that chip companies will actually get paid. We must remember that Trump revels in stiffing contractors he owes money to and views debts as optional donations.

In addition, circumstances are changing enough that some companies may not make the milestones needed to get paid. In short, the CHIPS Act likely will not do all of what was intended, as it couldn’t all get done in the short four years of the administration that started it.

We are not motivated to buy any of the equipment stocks given the near-term negative news of WFE spend reductions now happening.

We are also not happy about the broad semiconductor industry. We remain very enthusiastic about Nvidia and all things AI. Those memory makers who have an HBM product will also see benefit as well.

We may be in a holding pattern of uncertainty until Nvidia starts to move up again when the certainty of the incoming administration starts to take shape.

With the holidays coming up, this uncertainty will likely persist for a while during what will be a slow news period

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies.

We have been covering the space longer and been involved with more transactions than any other financial professional in the space.

We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.

We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

AMAT has OK Qtr but Mixed Outlook Means Weaker 2025 – China & Delays & CHIPS Act?

More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay

KLAC – OK Qtr/Guide – Slow Growth – 2025 Leading Edge Offset by China – Mask Mash

 


TSMC Unveils the World’s Most Advanced Logic Technology at IEDM

TSMC Unveils the World’s Most Advanced Logic Technology at IEDM
by Mike Gianfagna on 12-19-2024 at 10:00 am

TSMC Unveils the World’s Most Advanced Logic Technology at IEDM

There was a lot of discussion at IEDM about the coming shift to gate-all-around (GAA) transistor structures. This new device brings many benefits to continue device scaling, both at the monolithic device level as well as for multi-die design. The path to GAA is not simple, there are new material, process and design considerations to tame. TSMC has devoted a substantial amount of effort here. Let’s look at some of the details disclosed when TSMC unveils the world’s most advanced logic technology at IEDM.

About the Presenter

Dr. Geoffrey Yeap

Dr. Geoffrey Yeap presented 2nm Platform Technology featuring Energy-efficient Nanosheet Transistors and Interconnects co-optimized with 3DIC for AI, HPC and Mobile SoC Applications on Monday at IEDM. He is Vice President, TSMC R&D Advanced Technology. Geoffrey has been at TSMC for almost nine years and has also led advanced work at Qualcomm, Motorola Mobility, AMD, and the University of Texas System Center for Supercomputing.

Geoffrey explained that the work he was presenting spanned four years and involved many staff members in TSMC’s Global R&D Center.

Presentation Overview

According to the IEDM press kit, this late news paper presents the world’s most advanced logic technology. As the title says, the work is focused on a leading edge 2nm CMOS platform technology (N2) that has been developed and engineered for energy-efficient compute in AI, mobile and HPC applications. Geoffrey explained that since the generative AI break-through in Q1’23, AI together with 5G-advanced mobile and HPC have created a huge appetite in the semiconductor industry for best-in-class energy-efficient logic technology and this work responds to that need.

Geoffrey described the state-of-art TSMC N2 technology and its successful transition into NS platform technology with acceleration of >140x energy-efficient compute from 28nm to N2, as depicted in the graphic at the top of this post. The N2 logic technology features energy-efficient gate-all-around nanosheet transistors, middle-of-line and backend-of-line interconnects with the densest SRAM macro of ~38Mb/mm2. N2 delivers a full node benefit from the previous 3nm node in offering 15% speed gain or 30% power reduction with >1.15x chip density increase.

The N2 platform technology is equipped with new copper scalable RDL interconnect, flat passivation and TSVs. It co-optimizes holistically with TSMC’s 3DFabric™ technology enabling system integration/scaling for the target AI/mobile/HPC product designs.

Geoffrey reported that N2 has successfully met wafer-level reliability requirements and passed 1,000 hours of HTOL qualification with high yielding 256Mb HC/HD SRAM, and logic test chip (>3B gates) consisting of CPU/GPU/ SoC blocks. N2 is currently in risk production. N2 platform technology is scheduled for mass production in the second half of 2025. N2P, a 5% speed enhanced version of N2 with full GDS compatibility, is targeted to complete qualification in 2025 and go to mass production in 2026.

Some More Details

From a platform perspective, Geoffrey provided some details about the N2 NanoFlex™ technology architecture. System technology co-optimization (STCO) was utilized with smart scaling features rather than brute-force design rule scaling which can drastically increase process cost and inadvertently causes critical yield issues. Extensive STCO coupled with smart scaling of major design rules (e.g., gate, nanosheet, MoL, Cu RDL, passivation, TSVs) was performed in optimizing the technology to achieve the target PPA.

He pointed out that co-optimization with 3DFabric SoIC 3D-stacking and advanced packaging technology (INFO/CoWoS variants) was done, thereby accelerating system integration/scaling for AI/mobile/HPC product designs. N2 NanoFlex standard cell innovation offers not only nanosheet width modulation but also a much-desired design flexibility of a multi-cell architecture.

This capability delivers N2 short cell libraries for area and power efficiency. He explained that selective use of tall cell library elements lifts the frequency to meet design targets. With six Vt offerings spanning 200mV, N2 provides unprecedented design flexibility to satisfy a wide spectrum of energy-efficient compute applications at the best logic density. The figure below illustrates some of the benefits of this approach for an Arm-based design.

N2 NanoFlex HD cell benefits

Geoffrey explained that N2 nanosheet technology exhibits substantially better performance/Watt than FinFET at the low Vdd range of 0.5V- 0.6V. Emphasis is placed on low Vdd performance/Watt uplift through process and device continuous improvements resulting in a 20% speed gain and 75% lower stand-by power at 0.5V operation. N2 NanoFlex coupled with multi-Vt provides unprecedented design flexibility to satisfy a wide spectrum of energy-efficient compute applications at the most competitive logic density.

Geoffrey went into more details on the SRAM, logic test chip and qualification and reliability. This was an impressive presentation. The N2 technology platform brings a lot of new capability to the table for future innovation. And that’s some of the details about how TSMC unveils the world’s most advanced logic technology at IEDM.

Also Read:

IEDM Opens with a Big Picture Keynote from TSMC’s Yuh-Jier Mii

Analog Bits Builds a Road to the Future at TSMC OIP

Maximizing 3DIC Design Productivity with 3DBlox: A Look at TSMC’s Progress and Innovations in 2024