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Silicon Creations is Fueling Next Generation Chips

Silicon Creations is Fueling Next Generation Chips
by Mike Gianfagna on 11-21-2024 at 6:00 am

Silicon Creations is Fueling Next Generation Chips

Next generation semiconductor design puts new stress on traditionally low-key parts of the design process. One example is packaging, which used to be the clean-up spot at the end of the design. Thanks to chiplet-based design, package engineers are now rock stars. Analog design is another one of those disciplines.

Not long ago, analog design had a niche place in semiconductor design for the small but important part of the system that interfaced to the real world. Thanks to the performance demand of things like AI, analog design is now a critical enabling technology for just about every system. Data communication speed and latency as well as ubiquitous sensor arrays are prevalent in all advanced designs. These technologies now rely on analog design. At a recent Siemens event, substantial details were presented about this change in system design. Let’s dig into how Silicon Creations is fueling next generation chips.

The Event

Siemens EDA held its Custom IC Verification Forum recently on August 27 in Austin. The event aimed to present a comprehensive view of leading-edge AI-enabled design and verification solutions for custom ICs.  Topics such as circuit simulation, mixed signal verification, nominal to high-sigma variation analysis, library characterization, and IP quality assurance were all covered.

You can check out more details about this event here. What you will see is most of the presentations are given by Siemens folks, with one exception. They keynote address is delivered by Silicon Creations. I’d like to cover the eye-opening insights presented in that keynote.

The Keynote

Randy Caplan

Randy Caplan, Principal and Co-Founder of Silicon Creations presented the keynote, entitled Increasing Analog Complexity is a Reality for Next Generation Chips. For nearly 18 years, Randy has helped to grow Silicon Creations into a leading semiconductor IP company with more than 450 customers in over 20 countries, with a remarkable statistic of nearly 100% employee retention.

Silicon Creations’ designs have been included in over 1,500 mass-produced chips from 2nm to 350nm, from which more than ten million wafers were shipped. The company is known for award-winning analog mixed-signal silicon intellectual property that lowers risk. You can learn about this unique company on SemiWiki here.

Randy’s keynote presented a great deal of information about how chip/system design is changing. He presented many trends, backed-up with detailed data to illustrate how growing complexity is enabled by high-performance analog IP. Below is one example that surprised me. We are all aware of the growth in MOS logic and memory. However, shipments of analog chips are actually growing much faster, indicates how ubiquitous analog IP is becoming across many markets.

Unit forecasts

Randy covered many other relevant and interesting topics in his keynote, including the evolution from monolithic to multi-die design, process technology evolution, multi-core trends, the growth of analog functions required for advanced designs, reliability considerations, and a broad overview of design and process challenges. The unique demands of SerDes and PLL design are also explored.

There are examples presented, along with several architectural options to consider. The collaboration between Silicon Creations and Siemens is discussed, along with details around the use of Siemens Solido, Calibre and Questa solutions are presented.

To Learn More

I have provided a high-level overview of the topics covered in Randy’s keynote. There is much more detail and many more insights available in the slides. If analog content is becoming more important to your chip projects, you should get your own copy of this important keynote address. You can download it here and learn more about how Silicon Creations is fueling next generation chips.


I will see you at the Substrate Vision Summit in Santa Clara

I will see you at the Substrate Vision Summit in Santa Clara
by Daniel Nenni on 11-20-2024 at 10:00 am

Soitec Substrate Vision Summit

WIth packaging being one of the top sources of traffic on SemiWiki, I am expecting a big crowd at this event. A semiconductor substrate is a foundational material used in the fabrication of semiconductor devices. Substrates are a critical part of the manufacturing process and directly affect the performance, reliability, and efficiency of 3D IC based semiconductor devices.

I will be moderating a panel at this event and you certainly do not want to miss that!

AI’s impact on the semiconductor value chain is profound, enabling faster, more efficient, and more innovative approaches across all stages, from material discovery to design, fabrication, and testing. By leveraging AI technologies, the semiconductor industry can address the challenges of scaling, complexity, and demand for high-performance chips in emerging fields like AI, IoT, 5G, and beyond. Panelists will discuss this challenge. 

Panel discussion (Intel, Meta Reality Lab, Samsung Foundry Soitec, moderated by Daniel Nenni).

Register Here

Substrate Vision Summit, organized by Soitec, gathers leading engineers and industry professionals to explore the cutting-edge developments in semiconductor materials that are shaping the future of technology. This event provides a platform for the exchange of ideas, research findings, and technological advancements that are driving the evolution of the semiconductor industry.

As the demand for faster, smaller, and more efficient electronic devices continues to surge, the role of advanced semiconductor materials becomes increasingly critical. This conference will delve into topics such as the latest breakthroughs in silicon-based technologies, the rise of alternative materials like gallium nitride (GaN) and silicon carbide (SiC).

Keynote speakers, including prominent industry leaders, will share their insights on the future directions of semiconductor research and development. Technical sessions will cover a range of themes, from material synthesis and characterization to device fabrication and application. Attendees will have the opportunity to engage in in-depth discussions on challenges and solutions related to material performance, scalability, and sustainability.

Networking sessions and panel discussions will provide additional opportunities for collaboration and knowledge exchange, fostering connections that can lead to innovative partnerships and advancements in the field.

Join us at the Substrate Vision Summit to stay at the forefront of this dynamic and rapidly evolving industry. Together, we will explore the materials that are set to revolutionize electronics and enable the next generation of technological innovation.

Agenda
[ Registration Required ]
Wednesday, December 4
8:00 AM – 9:00 AM
9:00 AM – 9:20 AM
Pierre Barnabé – CEO
9:20 AM – 9:40 AM
Ajit Manocha – CEO & President
9:40 AM – 10:00 AM
Barbara De Salvo – Director of Research
10:00 AM – 10:15 AM
10:15 AM – 10:35 AM
David Thompson – Vice President, Technology Research Processing Engineering
10:35 AM – 11:05 AM
Christophe Maleville – CTO & SEVP of Innovation
11:05 AM – 12:00 PM
12:00 PM – 1:10 PM
1:10 PM – 1:20 PM
Afternoon Track
1:20 PM – 1:45 PM
Panel Discussion – Afternoon Track
1:45 PM – 2:15 PM
Panel Discussion – Afternoon Track
2:15 PM – 2:25 PM
Afternoon Track
2:25 PM – 2:50 PM
Panel Discussion – Afternoon Track
2:50 PM – 3:05 PM
3:05 PM – 3:35 PM
Panel Discussion – Afternoon Track
3:35 PM – 3:45 PM
Afternoon Track
3:45 PM – 4:30 PM
Panel Discussion – Afternoon Track
4:30 PM – 4:55 PM
Panel Discussion – Afternoon Track
4:55 PM – 5:00 PM
5:00 PM – 6:15 PM
SOITEC IN BRIEF

Soitec plays a key role in the microelectronics industry. It designs and manufactures innovative semiconductor materials. These substrates are then patterned and cut into chips to make circuits for electronic components. Soitec offers unique and competitive solutions for miniaturizing chips, improving their performance and reducing their energy usage. 

Register Here


Get Ready for a Shakeout in Edge NPUs

Get Ready for a Shakeout in Edge NPUs
by Bernard Murphy on 11-20-2024 at 6:00 am

trackstar in a race min (1)

When the potential for AI at the edge first fired our imagination, semiconductor designers recognized that performance (and low power) required an accelerator and many decided to build their own. Requirements weren’t too complicated, commercial alternatives were limited and who wanted to add another royalty to further reduce margins? We saw NPUs popping up everywhere, in-house, in startups, and in extensions to commercial IP portfolios. We’re still in that mode but there are already signs that this free-for-all must come to an end, particularly for AI at the edge.

Accelerating software complexity

The flood of innovation around neural net architectures, AI models and foundation models, has been inescapable. For architectures from CNNs to DNNs, to RNNs and ultimately (so far) to transformers. For models in vision, audio/speech, in radar and lidar, and in large language models. For foundation models such as ChatGPT, Llama, and Gemini. The only certainty is that whatever you think is state-of-the-art today will have to be upgraded next year.

The operator/instruction set complexity required to support these models has also exploded. Where once a simple convolutional model might support <10 operators, now the ONNX standard supports 186 operators, and NPUs make allowance for extensions to this core set. Models today combine a mix of matrix/tensor, vector, and scalar operations, plus math operations (activation, softmax, etc). Supporting this range requires a software compiler to connect the underlying hardware to standard (reduced) network models. Add to that an instruction set simulator to validate and check performance against the target platform.

NPU providers must now commonly provide a ModelZoo of pre-proven/optimized models (CV, audio, etc) on their platforms, to allay cost of adoption/ownership concerns for buyers faced with this complexity.

Accelerating hardware complexity

Training platforms are now architecturally quite bounded, today mostly a question of whose GPU or TPU you want to use. The same cannot be said for inference platforms. Initially these were viewed somewhat as scaled-down versions of training platforms, mostly switching floats to fixed and more tightly quantizing word sizes. That view has now changed dramatically. Most of the hardware innovation today is happening in inference, especially for edge applications where there is significant pressure on competitive performance and power consumption.

In optimizing trained networks for edge deployment, a pruning step zeroes out parameters which have little impact on accuracy. Keeping in mind that some models today host billions of parameters, in theory zeroing such parameters can dramatically boost performance (and reduce power) because calculations around such cases can be skipped.

This “sparsity” enhancement works if the hardware runs one calculation at a time, but modern hardware exploits massive parallelism in systolic array accelerators for speed. However such accelerators can’t skip calculations scattered through the array. There are software and hardware workarounds to recapture benefits from pruning, but these are still evolving and unlikely to settle soon.

Convolutional networks, for many of us the start of modern AI, continue to be a very important component for feature extraction for example in many AI models, even in vision transformers (ViT). These networks can also run on systolic arrays but less efficiently than the regular matrix multiplication common in LLMs.  Finding ways to further accelerate convolution is a very hot topic of research.

Beyond these big acceleration challenges there are vector calculations such as activation and softmax which either require math calculations not supported in a standard systolic array, or which could maybe run on such an array but inefficiently since most of the array would sit idle in single row or column operations.

A common way to address this set of challenges is to combine a tensor engine (a systolic array), a vector engine (a DSP) and a scalar engine (a CPU), possibly in multiple clusters. The systolic array engine handles whatever operations it can serve best, handing off vector operations to the DSP, and everything else (including custom/math operations) is passed to the CPU.

Makes sense, but this solution requires a minimum of 3 compute engines. Product cost goes up both in die area and possibly royalties, power consumption goes up, and the programming and support model becomes more complex in managing, debugging, and updating software across these engines. You can understand why software developers would prefer to see all this complexity handled within a common NPU engine with a single programming model.

Growing supply chain/ecosystem complexity

Intermediate builders in the supply chain, a Bosch or a ThunderSoft for example, must build or at least tune models to be optimized for the end system application, considering say different lens options for cameras. They don’t have the time or the margin to accommodate a a wide range of different platforms. Their business realities will inevitably limit which NPUs they will be prepared to support.

A little further out but not far, software ecosystems are eager to grow around high-volume edge markets. One example is around software/models for earbuds and hearing aids in support of audio personalization. These value-add software companies will also gravitate around a small number of platforms they will be prepared to support.

Survival of the fittest is likely to play out even faster here than it did around a much earlier proliferation of CPU platforms. We still need competition between a few options, but the current Cambrian explosion of edge NPUs must come to an end fairly quickly, one way or another.

Also Read:

Tier1 Eye on Expanding Role in Automotive AI

A New Class of Accelerator Debuts

The Fallacy of Operator Fallback and the Future of Machine Learning Accelerators


The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)

The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)
by Lauro Rizzatti on 11-19-2024 at 10:00 am

Immensity of SW development Part 4 Table 1

The Impact of AI on Software and Hardware Development

Part 4 of this series analyzes how AI algorithmic processing is transforming software structures and significantly modifying processing hardware. It explores the marginalization of the traditional CPU architecture and demonstrates how software is increasingly dominating hardware. Additionally, it examines the impact of these changes on software development methodologies.

From “software eating the world” to “software consuming the hardware”

Energized by the exponential adoption of a multitude of AI applications, the software development landscape is on the brink of a paradigm shift, potentially mirroring the software revolution prophesied by venture capitalist Marc Andreessen in his seminal 2011 Wall Street Journal piece, “Why Software Is Eating The World”[1] (see Introduction in Part 1.) Strengthening this perspective is Microsoft co-founder Bill Gates’ belief in Generative AI’s (GenAI) transformative potential. He positions GenAI as the next paradigm-shifter, alongside the microprocessor, the personal computer, the internet and the mobile phone.[2]

The evolving landscape has given rise to an updated mantra: “Software is eating the world, hardware is feeding it, and data is driving it.”[3] Now, software is consuming the hardware. The outcome stems from the increasingly intertwined relationship between software and hardware. Software advancements not only drive innovation, but also redefine the very fabric of hardware design and functionality. As software becomes more complex, it pushes the boundaries of hardware, demanding ever-more powerful and specialized tools to drive its growth.

Traditional Software Applications versus AI Applications and the Impact on Processing Hardware

It is noteworthy to compare traditional software applications vis-à-vis AI applications to understand the evolving software and hardware scenarios.

Traditional Software Applications and CPU Processing

Traditional software applications are rule-based, captured in a sequence of pre-programmed instructions to be executed sequentially according to the intention of the software coder.

A Central-Processing-Unit (CPU) architecture – the dominating computing architecture since Von Neumann proposed it in 1945 – executes a traditional software program sequentially, in a linear fashion, one line after another, that dictates the speed of execution. To accelerate the execution, modern multi-core, multi-threading CPUs break down the entire sequence in multiple blocks of fewer instructions and process those blocks on the multi-cores and on the multi-threads in parallel.

Over the years, significant investments have been made to improve compiler technology, optimizing the partition of tasks into multiple independent blocks and threads to enhance execution speed. Yet nowadays the acceleration factor is not adequate to meet the processing power demands necessary for AI applications.

Significantly, when changes to traditional software programs are required, programmers must manually modify the code by replacing, adding or deleting instructions.

AI Software Applications and Hardware Acceleration

Unlike traditional software that follows a rigid script, AI applications harness the power of machine learning algorithms. These algorithms mimic the human brain’s structure by utilizing vast, interconnected networks of artificial neurons. While our brains evolved in millions of years and boast a staggering 86 billion neurons intricately linked, in the last decade, Artificial Neural Networks (ANNs) have grown exponentially from few neurons to hundreds of billions of neurons (artificial nodes) and connections (synapses).

For example, some of the largest neural networks used in deep learning models for tasks like natural language processing or image recognition may have hundreds of layers and billions of parameters. The exact number can vary depending on the specific architecture and application.

The complexity of an AI algorithm lies not in lines of code, but rather in the sheer number of neurons and associated parameters within its ANN. Modern AI algorithms can encompass hundreds of billions, even trillions, of these parameters. These parameters are processed using multidimensional matrix mathematics, employing integer or floating-point precision ranging from 4 bits to 64 bits. Though the underlying math involves basic multiplications and additions, these operations are replicated millions of times, and the complete set of parameters must be processed simultaneously during each clock cycle.

These powerful networks possess the ability to learn from vast datasets. By analyzing data, they can identify patterns and relationships, forming the foundation for Predictive AI, adept at solving problems and making data-driven forecasts, and Generative AI, focused on creating entirely new content.

AI software algorithms are inherently probabilistic. In other words, their responses carry a degree of uncertainty. As AI systems encounter new data, they continuously learn and refine their outputs, enabling them to adapt to evolving situations and improve response accuracy over time.

The computational demand for processing the latest generations of AI algorithms, such as transformers and large language models (LLMs), is measured in petaFLOPS (one petaFLOPS = 10^15 = 1,000,000,000,000,000 operations per second). CPUs, regardless of their core and thread count, are insufficient for these needs. Instead, AI accelerators—specialized hardware designed to significantly boost AI application performance—are at the forefront of development.

AI accelerators come in various forms, including GPUs, FPGAs, and custom-designed ASICs. These accelerators offer significant performance improvements over CPUs, resulting in faster execution times and greater scalability for managing increasingly complex AI applications. While a CPU can handle around a dozen threads simultaneously, GPUs can run millions of threads concurrently, significantly enhancing the performance of AI mathematical operations on massive vectors.

To provide higher parallel capabilities, GPUs allocate more transistors for data processing rather than data caching and flow control, whereas CPUs assign a significant portion of transistors for optimizing single-threaded performance and complex instruction execution. To date, the latest Nvidia’s Blackwell GPU includes 208 billion transistors, whereas Intel’s latest “Meteor Lake” CPU architecture contains up to 100 billion transistors.

The Bottom Line

In summary, traditional software applications fit deterministic scenarios dominated by predictability and reliability. These applications benefit from decades of refinement, are well-defined, and are relatively easy to modify when changes are needed. The hardware technology processing these applications are CPUs that perform at adequate speeds and excel in re-programmability and flexibility. Examples of traditional software programs include word processors, image and video editing tools, basic calculators, and video games with pre-defined rules. The profile of a traditional software developer typically requires skills in software engineering, including knowledge and expertise in one or more programming languages and experience in software development practices.

In contrast, AI software applications perfectly fit evolving, data-driven scenarios that require adaptability and learning from past experiences. The hardware technology managing AI applications encompasses vast numbers of highly parallel processing cores that deliver massive throughputs at the expense of considerable energy consumption. Examples of AI applications include facial recognition software (which improves with more faces), recommendation engines (which suggest products based on past purchases), and self-driving cars (which adapt to changing road conditions). The job requirements to become an AI algorithm engineer include a diversity of skills. Beyond specific programming abilities and software development practices, thorough understanding and extensive experience in data science and machine learning are critical.

Table I summarizes the main differences between traditional software applications versus an AI software application.

Software Stack Comparison: Traditional Software versus AI Algorithms

Traditional software applications, once completed and debugged, are ready for deployment. Conversely, AI algorithms require a fundamentally different approach: a two-stage development process known as training and inference.

Training Stage

In the training or learning stage, the algorithm is exposed to vast amounts of data. By processing this data, the algorithm “learns” to identify patterns and relationships within the data. Training can be a computationally intensive process, often taking weeks or even months depending on the complexity of the algorithm and the amount of data. The more data processed during training, the more refined and accurate the algorithm becomes.

Inference Stage

Once trained, the AI model is deployed in the inference stage for real-world use. During this phase, the algorithm applies what it has learned to new, unseen data, making predictions or decisions in real-time. Unlike traditional software, AI algorithms may continue to evolve and improve even after deployment, often requiring ongoing updates and retraining with new data to maintain or enhance performance.

This two-stage development process is reflected in the software stack for AI applications. The training stage often utilizes specialized hardware like GPUs (Graphics Processing Units) to handle the massive computational demands. The inference stage, however, may prioritize efficiency and resource optimization, potentially running on different hardware depending on the application.

AI software applications are built upon the core functionalities of a traditional software stack but necessitate additional blocks specific to AI capabilities. The main differences comprise:

  1. Data Management Tools: For collecting, cleaning, and preprocessing the large datasets required for training.
  2. Training Frameworks: Platforms such as TensorFlow, PyTorch, or Keras, which provide the infrastructure for building and training AI models.
  3. Monitoring and Maintenance Tools: Tools to monitor the performance of the deployed models, gather feedback, and manage updates or retraining as necessary.

Overall, the development and deployment of AI algorithms demand a continuous cycle of training and inference.

Validation of AI Software Applications: A Work-in-Progress

In traditional software, validation focuses on ensuring that the application meets expected functional requirements and operates correctly under defined conditions. This can be achieved through rigorous validation procedures that aim to cover all possible scenarios. Techniques like unit testing, integration testing, system testing, and acceptance testing are standard practices.

In contrast, validating AI software requires addressing not only functional correctness but also assessing the reliability of probabilistic outputs. It involves a combination of traditional testing methods with specialized techniques tailored to machine learning models. This includes cross-validation, validation on separate test sets, sensitivity analysis to input variations, adversarial testing to assess robustness, and fairness testing to detect biases in predictions. Moreover, continuous monitoring and validation are crucial due to the dynamic nature of AI models and data drift over time.

Risk Assessment

Risks in traditional software validation typically relate to functional errors, security vulnerabilities, and performance bottlenecks. These risks are generally more predictable and easier to mitigate through systematic testing and validation processes.

Risks in AI software validation extend beyond functional correctness to include ethical considerations (e.g., bias and fairness), interpretability (understanding how and why the model makes decisions), and compliance with regulations (such as data privacy laws). Managing these risks requires a comprehensive approach that addresses both technical aspects and broader societal impacts.

AI development is rapidly evolving, as these algorithmic models become more sophisticated, verification will become more challenging.

Implications for AI systems development

The suppliers of AI training and inference solutions falls into two main categories. Companies such as NVIDIA develop their own, publicly available programming language (CUDA) and develop faster, more scalable and more energy efficient execution hardware for general purpose use. Hyperscale companies such as Meta develop more specialized AI accelerators (MTIA) that are optimized for their specific workloads. Both require that the software layers and the underlying hardware are optimized for maximum performance and lower energy consumption. These metrics need to be measured pre-silicon, as the AI architecture optimization – as opposed to the traditional Von Neumann architecture – is of central importance for success. Large companies such as NVIDIA and Meta, as well as startup companies such as Rebellions rely on hardware-assisted solutions with the highest performance to accomplish this optimization.

In Conclusion:

The widespread adoption of AI across a variety of industries, from facial/image recognition and natural language processing all the way to self-driving vehicles and generative AI elaboration, is transforming how we live and work. This revolution has ignited a dual wave of innovations. On the hardware side, it is thrusting a massive demand for faster and more efficient AI processing. On the software side, it is driving the creation of ever more complex, and sophisticated AI applications.

While traditional software excels at well-defined tasks with clearly defined rules, AI applications are ideally suited for situations that demand adaptation, learning from data, and handling complex, unstructured information. The evolving nature of AI software presents a new challenge in validation that existing methods are not fully equipped to address. A new wave of innovation in software validation is necessary, opening new opportunities to the software automation industry.

[1] https://www.wsj.com/articles/SB10001424053111903480904576512250915629460

[2] https://www.gatesnotes.com/The-Age-of-AI-Has-Begun.

[3] The quote “Software is eating the world, hardware is feeding it, and data is driving it” is attributed to Peter Levine, a venture capitalist at Andreessen Horowitz, who used it to encapsulate the transformative impact of software, hardware, and data on various industries and aspects of our lives.

Also Read:

The Immensity of Software Development the Challenges of Debugging (Part 1 of 4)

The Immensity of Software Development and the Challenges of Debugging Series (Part 2 of 4)

The Immensity of Software Development and the Challenges of Debugging (Part 3 of 4)


Alchip is Paving the Way to Future 3D Design Innovation

Alchip is Paving the Way to Future 3D Design Innovation
by Mike Gianfagna on 11-19-2024 at 6:00 am

Alchip is Paving the Way to Future 3D Design Innovation

At the recent TSMC OIP Ecosystem Forum in Santa Clara, there was an important presentation that laid the groundwork for a great deal of future innovation. Alchip and its IP and EDA partner Synopsys presented Efficient 3D Chiplet Stacking Using TSMC SoIC. The concept of 3D, chiplet-based design certainly isn’t new. SemiWiki maintains dedicated forums on both Chiplets and 3D IC. There is a lot of buzz on both topics.

And TSMC’s SoIC initiative provides the manufacturing infrastructure and technical support to achieve next-generation innovation. Indeed, all the elements needed for 3D chiplet-based design are taking shape. It has been said that the devil is in the details. And the details and technical challenges to be overcome as we move to a new chapter in semiconductors are daunting. Meaningful progress to reduce these challenges is quite important, and that progress was on full display at the Alchip presentation. Let’s examine how Alchip is paving the way to future 3D design innovation.

Alchip at TSMC OIP

Erez Shaizaf

The presenter from Alchip was Erez Shaizaf, Alchip’s Chief Technical Officer. Erez has been with Alchip for the past two years. He has a long career in semiconductors with companies such as Freescale, EZchip, Mellanox, and Xsight Labs. Erez discussed how Alchip, working with Synopsys and TSMC, has overcome several significant challenges for 3D IC design in the areas of electrical, power, thermal and mechanical design.

Erez described the kind of 3D architecture being addressed as one that contains top dies in advanced nodes (e.g., high-frequency CPU) and bottom dies in older nodes (e.g., memory subsystems). A coherent fabric connects the two layers with an Alchip Micro 3D liteIO PHY interface. Fine pitch hybrid bonding and fine pitch TSVs create high bandwidth interconnect and efficient power delivery between the top and bottom dies. The figure below illustrates this 3DIC folded CPU use case.

Erez also discussed several power delivery challenges, including:

  • Power Integrity Challenges
    • Static and dynamic IR drop
    • Power noise propagation from bottom to top die and vice versa
    • Different power domains among top and bottom dies and a shared ground plane
  • Power Grid Design
    • TSV distribution
    • B distribution
    • PDN design
  • Power Integrity Simulation and Signoff
    • Early analysis (prior to place & route)
    • Early simulation (after place & route)
    • Signoff

The paper also described a sophisticated TSV distribution strategy that uses non-uniform and location-dependent TSV arrays. Using this approach, TSV density is determined by local power density for bottom and top die shared and non-shared power delivery networks (PDNs).  Erez detailed the pros and cons of shared vs. non-shared PDNs. He explained that non-uniform TSV density schemes are friendly to automated place & route. The TSV patterns are compatible with Alchip’s multiple 3D-liteIO micro-PHY P&R and TSMC design rules.

Erez also talked about how to do early PDN analysis and the benefits that result. He also discussed how to achieve 3D data and clock design targets and details of an H-tree strategy for 3DIC clocking. 3DIC thermal characterization challenges and solutions were also presented, along with a set of verification strategies aimed at 3DIC design.

Abhijeet Chakraborty

Abhijeet Chakraborty, Vice President Engineering at Synopsys, followed Erez to the podium. Abhijeet has been with Synopsys more than 18 years. He described how the Synopsys 3DIC Compiler delivers a unified exploration-to-signoff platform. The benefits of this platform include:

  • Extending 2D fusion platform (Fusion Compiler) for 3D heterogenous integration (3DHI) and advanced packaging
  • Delivering a unified environment that supports 3D design exploration, planning, implementation and verification
  • Integrating the golden signoff solutions from Synopsys and Ansys for 3D STA, EM/IR, SI/PI/TI, EMAG
  • Providing full support for TSMC technologies including CoWoS, SOIC, and 3Dblox

Overall, Abhijeet explained that Synopsys and Alchip are collaborating on HPC/AI-optimized physical design for advanced nodes, IP and multi-die packaging. The graphic at the top of this post provides a high-level summary of how Synopsys and Alchip are enabling 3DIC design success.

The Implications of This Work

I had a chance to speak with Erez Shaizaf after the presentation. He gave me some perspective on the implications of the work presented. In a word, it’s transformative.

Erez explained that up to now, most multi-die designs consisted of active devices, like AI accelerators and some HBM memory stacks over passive devices, like caps and interconnect supplied by the interposer. The work presented at OIP opens the possibility for multiple active devices in the stack to come from different technology nodes. He predicted these new options will change the designer’s mindset and system design will take on new meaning.

He explained that the ability to integrate multiple active devices in a true 3D stack with multiple process nodes opens many new options for system architecture and integration. One benefit of this approach is partitioning a subsystem from one large die to multiple smaller dies. This delivers a yield and cost benefit. There are many more examples of how a more unconstrained 3D design flow can change the game.

He pointed out that the yield, thermal, mechanical and power delivery aspects of true multi-dimensional system design are substantial. The way design will be done will change as well. But the opportunities for true system innovation make it all worthwhile.

Erez concluded by saying that Alchip and Synopsys are breaking down the barriers to this new design paradigm. Along with TSMC, they are bringing new opportunities for innovation within reach, and that makes for an exciting future.

To Learn More

You can find out more about the TSMC Global OIP Ecosystem Forum here.  If you are considering the benefits of 3DIC design, you will want to learn more about how Alchip can help. You can access more information about Alchip here. Even better, you can reach out to the company to discuss your future design needs here. And that’s how Alchip is paving the way to future 3D design innovation.


Handling Objections in UVM Code

Handling Objections in UVM Code
by Daniel Payne on 11-18-2024 at 10:00 am

expanded view min

You begin writing some UVM code and there are parts of the code that aren’t done yet, so you begin to use uvm_objection, guarding that code. Rich Edelman, a product engineer at Siemens doing verification debug and analysis, wrote a paper on this topic, which I just read. This blog covers the topic of objections and provides some different approaches.

UVM is founded on processes, and processes can be synchronized automatically or by design during phases. We typically raise an objection, then later on drop the objection during a phase.

Here’s a UVM example using a raised objection to make sure that simulation doesn’t exit until a drop exception happens.

The source code of has over 1,000 lines of code, so it’s recommended to use objections once in a test. Consider a UVM test with four sequences, using raise_objection and drop_objection.

Each of the four environments (e1 – e4) call raise_objection and drop_objection, which is not so efficient.

A simpler objection in UVM is the uvm_barrier.svh, at just 240 lines, but we can define our own barrier function with even fewer lines like this:

This barrier code uses a count to pass the barrier. When the count reaches 0 after a drop, it exits.

Another approach to synchronization is using names like start, middle, and end.

 

This wrapper creates the barrier class if needed, and uses three names: raise, drop, and get.

The next example shows a class and a module, where there are two class instances and three Verilog modules. Three phases are synchronized across the modules and class instances: start, middle, and end. The objects simulate in each phase for some time, then drop the objection. After all objects have dropped, processing continues.

Running this example shows that each object reports after “drop” has returned, then each object moves forward.

Both Class1 and Class2 are SystemVerilog class handles, while A, B, and C are the Verilog module instances. Each of the objects in each phase waits until the next barrier completes, which is our synchronization goal.

Below are visualizations: the “middle” phase and the workload for each object. Each phase—here the middle phase—displays each object: “class1,” “B,” “A,” “class2” and “C,” in order, along with the payload for each object.

This view shows many phase begins and ends, all synchronized.

The expanded view provides details of the objects and payloads in each phase.

Objections and phasing are linked together, so use objections with phasing while limiting their usage to be more efficient. One way to create phasing is through a barrier like uvm_barrier, or using the examples presented. You can solve synchronization with your own code. Adding too many raise_objection and drop_objection pairs in your code will only slow down simulation times.

Summary

Yes, continue to use uvm_objection in your UVM code, being careful to not slow down run times by calling it too often. Alternative approaches were shared in this blog that require less code, are more intuitive, and run quicker.

Read the complete 15 page paper online.

Related Blogs


GaN HEMT modeling with ANN parameters targets extensibility

GaN HEMT modeling with ANN parameters targets extensibility
by Don Dingee on 11-18-2024 at 6:00 am

Modified ASM HEMT equivalent circuit for GaN HEMT modeling with ANN parameters

Designers choosing gallium nitride (GaN) transistors may face a surprising challenge when putting the devices in their context. While the Advanced SPICE Model for GaN HEMTs (ASM-HEMT) model captures many behaviors like thermal and trapping effects, it grapples with accuracy over a wide range of bias conditions. Foundries often define ASM-HEMT parameters from measurements at a specific bias point but don’t solve for different bias values. Keysight device modeling researchers are exploring an improved ASM-HEMT hybrid model, blending measurements with physics and using artificial neural network (ANN) techniques for improving wide-range S-parameter fit in minutes. We spoke with Rafael Perez Martinez, R&D Software Engineer in the R&D Device Modeling group at Keysight EDA, about this new approach to GaN HEMT modeling with ANN parameters.

A choice between lengthy measurements or less-than-accurate simulations

Perez Martinez began his exploration of GaN HEMT modeling at Stanford University, working on his PhD in the Wide-Bandgap Lab (WBGL). “I had an idea in 2022 looking at prior ASM-HEMT publications. It seemed like people weren’t reporting CV characteristics fitting, and they tended to fit the model at one drain voltage bias,” he says. “Measurements are tedious, and measurement-based models such as DynaFET require extensive DC and S-parameter data and large-signal non-linear vector network analyzer (NVNA) measurements that can take one to three months to set up and execute.” Physics-based theoretical models like ASM-HEMT can readily simulate and extend S-parameter predictions across frequency ranges but tend to inaccurately fit parameters at varying bias voltages.

Additionally, many university labs and start-ups don’t have budgets for an NVNA or similar instruments and accessories for GaN HEMT measurements. Perez Martinez parlayed his summer internships at Keysight into a WBGL proposal for grant funding for a Keysight PNA-X, which arrived at the lab in 2023. With coaching from Keysight teams, Perez Martinez dove in, taking PNA-X readings on a 150nm gate length GaN-on-SiC HEMT and capturing its non-linear characteristics. Plugging the measured parameters as-is into a standard ASM-HEMT model highlighted the disparity between the two approaches. The S-parameter fitting performs poorly with VD=5 to 25 V, VG=-3 to -1V, and f = 250MHz to 50GHz (measurements in red, simulations in blue).

Moving to hybrid GaN HEMT modeling with ANN parameters

This persistent mismatch between measurements and simulation gave Perez Martinez the idea of developing a hybrid model example, combining the baseline of a measurement-based model with the extensibility and speed of physics-based modeling. “I had GaN HEMT measurements at 10 GHz with second and third harmonics,” he says. “But starting the hybrid model was difficult initially because you need to know the device model, go through the Verilog code, know what to change – and you can’t just add things randomly. There has to be some physical aspect of any change that makes sense.”

With measurements in the 10 GHz region where the model should be most accurate, Perez Martinez moved into Keysight IC-CAP for modeling with its ANN Modeling Toolkit. “Integrating a neural network into the Verilog model is quite trivial using the ANN toolkit,” continues Perez Martinez. “Looking at some earlier small-signal models, I noticed the ASM-HEMT model was missing something around gate-drain resistance, so that’s where I started, working carefully not to fix one problem and break something else.” A few cycles of replacing parameters with ANN variables and using the IC-CAP optimizer added two resistances and three capacitances to the ASM-HEMT equivalent circuit (inside the dotted pink outlines).

Generalizing results from ANN parameter fitting

A Keysight ADS simulation with hybrid ANN parameters from IC-CAP aligns very closely with measurements, as indicated by the near-perfect overlap between the red lines and the dotted pink lines in this comparison of power-added efficiency, gain versus Pout, and dynamic load lines. In this case, the model modification solves the problem of simulating wide-range bias.

The logical follow-up to this result: are these results device-specific, or will the methodology scale to smaller geometries and higher frequencies? “The first challenge is getting measurements at higher frequencies, which takes access to instrumentation, plus time and care,” observes Perez Martinez. “The next challenge is not every GaN HEMT has the same physical device structure, and people tend to play tricks – maybe the distance between the drain and gate varies, maybe there’s a different field plate, or maybe the gate structure has a different shape.” The implication is that one model may not fit all devices. However, the ANN approach in IC-CAP works with any device model and helps narrow down where modifications can improve and speed up S-parameter fitting – in a matter of hours versus months of measurements.

That’s an important observation since Perez Martinez is not necessarily looking for a formal ASM-HEMT model update. He’s presenting his paper at the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) to raise awareness and generate discussion around the approach. “People always talk about positive results in papers, but rarely do they talk about the failures it took to get there,” says Perez Martinez. “This is really a look at some GaN HEMT model shortcomings we’ve seen, and a hybrid model example in IC-CAP with ANN that we’d like people to look at that might fit their needs.”

To see more details about the methodology for GaN HEMT modeling with ANN parameters and the results, see the BCICTS 2024 paper in the  BCICTS proceedings archive:

A Hybrid Physical ASM-HEMT Model Using a Neural Network-Based Methodology

Also, see more information on the latest in GaN device modeling from Keysight experts:

Electronic Design webinar:   Mastering GaN Device Modeling

Keysight:   Device Modeling IC-CAP   |   W7009E PathWave IC-CAP ANN Modeling Toolkit

Also Read:

Keysight EDA 2025 launches AI-enhanced design workflows

Webinar: When Failure in Silicon Is Not an Option

Keysight EDA and Engineering Lifecycle Management at #61DAC


AMAT has OK Qtr but Mixed Outlook Means Weaker 2025 – China & Delays & CHIPS Act?

AMAT has OK Qtr but Mixed Outlook Means Weaker 2025 – China & Delays & CHIPS Act?
by Robert Maire on 11-17-2024 at 8:00 am

Applied Materials

– AMAT has OK QTR but outlook below expectations as 2025 weakens
– Strength in AI cannot offset weakness in the rest of the market
– Increasing headwinds going into 2025 dampen overall outlook
– Weakness combined with regulatory uncertainty reduce valuations

Quarter and year are just OK but outlook is weak/mixed

Applied Materials reported revenues of $7.05B and non GAAP EPS of $2.32 modestly better than expectations of $6.97B and $2.19.

Guidance is for revenues of $7.15B +-$400M and $2.29+-$0.18 versus street of $7.25B and $2.27.

Body language and discussion on the call was not very assured nor certain about 2025. Actual system sales were not that great but service revenues helped offset systems weakness.

Year over year growth was minimal at 2%.

Hard for AI to drag an overall weakening semiconductor industry along

While we hear a lot of talk about AI, we keep repeating that its less than 10% of memory and only the very bleeding edge of a single foundry , TSMC. The vast majority of memory, two of the 3 big players (Samsung & Intel), trailing edge nodes are all weak with negative momentum.

As we pointed out in our note this past Monday there has been near term additional negative news of Micron’s delay and other order delays.

CHIPS Act risk & China risk add to uncertainty

When asked about the new incoming administration, management demurred rather than reacting positively as prior comments on the CHIPS Act create open questions.

China is down to about 30% but 30% is still the largest slug of Applied business so losing China would be a horrible hit.

Tariffs and other draconian regulatory issues add to potential China risk in addition already declining demand.

Results and outlook supports our ongoing concerns

In our note this past Monday we said “News flow for semi equipment all bad in front of AMAT”.

Link to our recent note

Applied’s report and outlook only support our ongoing concern/predictions about a weaker 2025 and worsening near term data points.

We would reiterate that this in no way implies that AI is weak or has any fundamental issues….quite the contrary, we think AI remains super strong and is tremendously positive for semiconductor equipment. Without AI, semiconductor equipment would be in a freefall right now.

The simple fact is that 10% or less of the chip industry that is on fire , can’t hope to make up for the other 90% that is weak or muddling along at best….

The Stocks

We had warned investors to “lighten up” in front of Applied’s earnings as we saw much more downside beta than potential upside beta.

Applieds stock was off over 5% in after market trading as investors were clearly unhappy with the poor outlook

There will obviously be collateral damage to the semi equipment group as 2025 concerns are not contained to just AMAT.

ASML stock recently saw a nice pop as it reaffirmed its long term revenue and financial model over the next few years (which we heartily agree with). The question is clearly about 2025….is it up, down or sideways….longer term, for semiconductors and semiconductor equipment, is always up and to the right …

There had been an initial, more positive view by many analysts which now appear too optimistic and will have to be trimmed to be more conservative, to the view we have long held, of a slower recovery with more lumps and bumps along the way

We hope you still have your seat belts on as the near term turbulence will continue!

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

KLAC – OK Qtr/Guide – Slow Growth – 2025 Leading Edge Offset by China – Mask Mash

LRCX- Coulda been worse but wasn’t so relief rally- Flattish is better than down

ASML surprise not a surprise (to us)- Bifurcation- Stocks reset- China headfake


Podcast EP261: An Overview of the Upcoming 70th IEDM with Dr. Gaudenzio Meneghesso

Podcast EP261: An Overview of the Upcoming 70th IEDM with Dr. Gaudenzio Meneghesso
by Daniel Nenni on 11-15-2024 at 9:00 am

Dan is joined by Dr. Gaudenzio Meneghesso, IEDM 2024 Publicity Co-Chair, and Head of the Department of Information Engineering at the University of Padua in Italy.

Dan explores the program for the upcoming IEDM event with Gaudenzio. This conference covers a wide range of innovations that have significant impact on the semiconductor industry.

Gaudenzio discusses four “grand challenges” that will be explored at IEDM: Device scaling,memory architectures and in-memory compute, chip packaging and power efficiency. In the area of power efficiency, the impact of new devices based on compound semiconductor technology will be explored.

The demands of AI performance and the associated impact on semiconductors will also be presented. Other high-profile topics include nano-sheet transistors and high-density aligned carbon nanotubes, among others.

The 70th IEDM will be held December 7-11, 2024 in San Francisco. You can learn more about this important conference and register to attend here.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay

More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay
by Robert Maire on 11-15-2024 at 8:00 am

CHIPS Act Semiconductor USA

– CHIPS Act more likely to be maimed & cut than outright killed
– Will Legislators reverse flow of equipment to Reshore from Offshore?
– Recent order cuts, Fab Delay & SMIC comments are all negative
– News flow for semi equipment all bad in front of AMAT

CHIPS Act Chops likely to occur under new administration

In the days leading up to the election, Trump made it crystal clear he thought the CHIPS Act was a “bad deal”. Then Mike Johnson, following his lead said he would probably want to repeal the CHIPS Act.

Even though some analysts and investors will say the incoming administration can’t do anything because deals are signed, there is certainly plenty that can be done to delay, prevent, modify, question and generally screw with even a done deal….especially if you are the new administrator, who writes the checks, of said deal.

We don’t think that the deal with Intel will get torpedoed but the TSMC deal has some risk. Samsung Texas will likely get done. Micron in Idaho is probably safe but the Micron Clay, New York fab is likely toast.

We think the administration will also look to undo the chip design center in California just to spite a Blue state and Newsome. Likewise Clay New York was Schumer’s baby in an also very blue New York state.

No matter what, its going to be different than anticipated as the incoming administration will influence it much as the outgoing administration influenced it.

Take a look at the electoral map then look at the CHIPS Act map if you want an idea:

At the end of the day, reduced CHIPS Act spend is most directly less spend on semiconductor equipment as 90% of the cost of a new fab is in the equipment…

Cancellations & delays last week

We heard of some large cancellations coming out of a large US chip maker last week. Although likely anticipated its always a negative when it actually happens.

We also heard that Micron’s new Idaho Fab has been delayed. While this is not a near term issue it adds to the increasing headwinds. It also increases the chances of Micron’s Clay NY fab to be further delayed if not outright canned.

SMIC comments on China semi equipment indigestion

Adding to the cancelation/delay headwinds we heard from SMIC, China’s largest fab that orders for equipment coming out of China will be down as trailing edge capacity is over supplied.

Although this is something we already know and already heard about slowing China orders it is just confirmation that China is up to their eyeballs in equipment and already has way to much.

Over supply situations like this can take years to fix as not only is there too much current trailing edge supply but we also have a pipeline of equipment that hasn’t even been turned on yet.

The “Captain Obvious” award of the week goes to US legislators that finally figured out chip equipment is still be offshored, while trying to reshore chips.

US legislators sent letters to AMAT, LRCX, KLAC, Tokyo Electron & ASML asking what was up with their sales of chip equipment to China. But perhaps more importantly the letter asked about where the equipment is being made and the supply chain of that equipment.

Select committee on CCP Chips

SCMP article

NY Times article

This topic is something we have been talking about longer and more vocally than anyone else.

It seems insanely stupid and short sighted to “re-shore” semiconductors while you continue to “off-shore” the equipment made to produce them.

Wouldn’t it be just plain dumb to move chip manufacturing back to the US only to have equipment made by US companies in Asia imported back into the US where all the equipment used to be made?

Applied Materials has been the leader in moving production out of Texas to Singapore. Lam is not far behind in moving all its California and Oregon based manufacturing to Malaysia. Lam recently crowed about shipping its 5,000th chamber out of Malaysia.

Could the US finally get its act together and force chip equipment makers to reshore that which they have off shored so quickly just over the past few years? Its not like Taiwan or China stole the US equipment industry. The industry has been moving to Asia as fast as humanly possible for primarily financial reasons.

It would be yet another problem/headwind for equipment makers. The huge cost of moving only to have a large cost to move back. Lower margins and higher costs due to increased costs in the US that led them to leave in the first place.

The incoming administration could even put a tariff on imported chip equipment much as they will likely put a tariff on imported chips to force manufacturers to move back to the US as this is a core of the platform Trump was running on.

It could get ugly.
The Stocks

The recent election results raised all the boats in the stock market to new highs.

We would point out that the actual impact on the semiconductor and especially the semiconductor equipment stocks are not quite so positive especially over the longer run given both recent and future headwinds.

The CHIPS act will be likely negatively impacted, its only a question of how much. China and Tariffs will only get worse and likely impact chip production and equipment.

Near term headwinds continue to slow the overall market and most recent news is certainly negative.

It may not be a bad time to think about reducing exposure to some of the more impacted names in the space before everyone figures out the potential negative impacts.

Buckle up, things will change, a lot.
About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

KLAC – OK Qtr/Guide – Slow Growth – 2025 Leading Edge Offset by China – Mask Mash

LRCX- Coulda been worse but wasn’t so relief rally- Flattish is better than down

ASML surprise not a surprise (to us)- Bifurcation- Stocks reset- China headfake