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Webinar: RF design success hinges on enhanced models and accurate simulation

Webinar: RF design success hinges on enhanced models and accurate simulation
by Don Dingee on 02-19-2025 at 10:00 am
Categories: EDA, Events, Keysight EDA

Modelithics 3D Library for RFPro increases the chances for RF design success

Traditional RF board design strategies based on circuit simulation worked at lower frequencies and relatively large spacing between components. Higher frequencies and densification dominate RF designs now, where corresponding wider bandwidths and tighter layouts with closely spaced components produce more complex 3D electromagnetic (EM) interactions. Relying on circuit simulation alone with simplistic models lacks sufficient accuracy and can result in costly re-spins. Keysight and Modelithics have teamed up for an advanced RF board simulation workflow in Keysight ADS and RFPro with 3D passive vendor component models supporting highly accurate, automated 3D EM-circuit co-simulation seeking better chances of RF design success.

WATCH REPLAY NOW: Maximizing RF Board Accuracy with 3D EM and Scalable SMD Circuit Models

Why 3D passive component models are needed

Keysight RF design teams often quote the phrase, “At high frequencies, with every resistor you buy, you get a free inductor.” It’s a bit of an oversimplification, but the point is valid. Packaged and soldered to a board, every passive resistor, capacitor, and inductor can introduce non-schematic parasitic resistance, capacitance, and inductance values. Higher frequencies and layout densities also increase the chances of electromagnetic coupling between components.

Unaccounted for, these parasitics and proximity EM coupling effects can shift circuit performance and frequencies. Circuit simulation alone might get spoofed into thinking all is well. Ultimate high-frequency RF board simulation accuracy depends on circuit and EM modeling and simulation working together. Without both simulation modes, the risks of board re-spins skyrocket. Designers may still be hesitant about increased simulation times in their workflow. Circuit simulation typically runs quickly, while EM simulation with more complex models, solvers, and a 3D volume to analyze usually takes longer.

Modelithics specializes in accurate equivalent circuit models for passive components. Each measurement-based model captures a part’s parasitics. Models then scale across all values of a part series. They also scale with respect to the substrate the part mounts on and the solder pad dimensions.

However, Modelithics goes a step further. “Our models fit directly into the ADS and RFPro workflow, allowing fast initial circuit simulation and optimization, followed by detailed EM simulation for highly accurate results,” says Chris DeMartino, Application Engineer at Modelithics. ADS and RFPro integration eliminates the need to manually connect EM simulation data to passive component models, building all required connections automatically to enable seamless EM-circuit co-simulation at will.

Moving from simulation to real-world board producibility

Both Keysight and Modelithics keep the goal in mind – simulation is a means to an end in producing an RF board assembly that works, and accuracy often is the difference between first-pass RF design success and a re-spin. Keysight uses Modelithics models and ADS with RFPro internally, with a recent example of an RF board design for the Keysight UXA Signal Analyzer. The 16-layer, 50 GHz design thoroughly illustrates RF board assembly complexity.

“Two things have to happen to make real RF board hardware – you need to find purchasable parts and then run accurate circuit-EM co-simulations with those parts in dense, multi-layer, high-frequency layouts,” says How-Siang Yap, Keysight EDA Marketing Manager for RF/MW solutions including ADS and RFPro. “Sweeping parameters like etching width, dielectric constant, and thickness and analyzing performance with the Modelithics component models get us first-pass layout success and confidence these RF board assemblies perform as advertised when produced in volume.”

Modelithics component modules start with actual manufacturer parts, such as TDK, Murata, or Coilcraft. Keysight ADS can use gradient followed by discrete optimization to find purchasable part values for resistance, capacitance, or inductance. These discrete values drive the selection of 3D components from the Modelithics library for highly accurate circuit-EM co-simulation with RFPro. The result is an accurately analyzed, sign-off-ready bill of materials for producing an RF board with first-pass success.

Stepping through component models and RF board simulation

Yap and DeMartino discuss the details of modeling and the need for 3D EM simulation in a SemiWiki webinar illustrating this enhanced RF board design workflow. One crucial finding they show is that circuit simulation diverges from EM simulation in dense layouts as EM coupling effects increase between passive components, missing the performance degradation.

The integrated circuit and EM simulation workflow of Keysight ADS, RFPro, the Modelithics Microwave Global +3D model library, and the discrete optimization capability give designers a significant advantage for RF design success no other EDA environment offers today. Registration for this webinar is open now:

WATCH REPLAY NOW: Maximizing RF Board Accuracy with 3D EM and Scalable SMD Circuit Models

Also Read:

Chiplets-Based Systems: Keysight’s Role in Design, Testing, and Data Management

Crosstalk, 2kAmp power delivery, PAM4, and LPDDR5 analysis at DesignCon

Chiplet integration solutions from Keysight at Chiplet Summit

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2025 Outlook with Paul Wells of sureCore

2025 Outlook with Paul Wells of sureCore
by Daniel Nenni on 02-19-2025 at 8:00 am
Categories: IP, sureCore

Paul Wells sureCore photo

Paul Wells, CEO at sureCore, an ultra-low power memory specialist, has been involved in the semiconductor industry for over 35 years. Previously, he has worked as Director of Engineering for Pace Networks where he led a multidisciplinary product development team creating a broadcast quality video and data mini-headend. Before this, he worked for Jennic Ltd as VP Operations, successfully building the team from scratch as the company transitioned to a fabless model. Prior to this, he was responsible for a team at Fujitsu Microelectronics supporting ASIC customers in Europe and Israel.

Tell us a little bit about yourself and your company. 

I’ve been in the semiconductor industry now for over 35 years. I began my career at Ferranti Electronics in Manchester, UK, as an ASIC engineer delivering custom chips for a wide range of innovative consumer applications. Ferranti had invented the gate array and the possibilities for its use seemed endless. I also worked for Fujitsu, Jennic and Pace Networks, holding senior engineering and operations positions, before co-founding sureCore and taking on the role of CEO back in 2011.

SureCore started out by taking a radically different view of memory. All SoC devices need embedded memory, usually SRAM, but also register files, and occasionally ROM. With the growing trend to even more integration, and the need to be able to accommodate larger software footprints, the demand for on-chip memory just kept increasing until for some devices it reached 70% die area! SRAM whilst fast is also power hungry and by analysing the traditional architectures we were able to identify some key power saving strategies that resulted in up to 50% dynamic power savings.

For many consumer and medical products, the performance delivered by modern process nodes is often overkill. Very significant power savings can be achieved by operating at much lower voltages and sureCore have been able to develop and demonstrate in silicon the industry’s lowest operating voltage SRAM. These power optimising technologies are embedded in our market-leading PowerMiserTM and EverOnTM product families. By exploiting our ultra-low power design expertise, we have created our sureFITTM custom memory development service that provides our customers with the optimal solution for their application.

What was the most exciting high point of 2024 for your company? 

Throughout 2024 sureCore delivered a number of custom advanced memory implementations, including a low power memory compiler for 16nm FinFET.

SureCore also continued to lead on the cutting-edge government funded InnovateUK project to develop cryogenic IP for quantum computers. We successfully taped-out a cryogenic IP demonstrator – our test chip which included cryogenic SRAM, register files and ROM based on the GlobalFoundries 22FDX process. As part of the seven member consortium transistor parameters were measured at both 77K and 4K, and SPICE models updated using advanced TCAD. We received samples in November and the great news is that the devices are working extremely well. We already have a lead customer who has proven that the IP works at 3.3K and we just need to complete the full chip characterisation to fully validate the compiler space.

What was the biggest challenge your company faced in 2024? 

After a buoyant 2022, 2023 and early 2024 presented very challenging market conditions for the semiconductor industry. Geopolitical issues and the ever increasing importance of semiconductors to the global economy turned out to be a double-edged sword, with restrictions being imposed on advanced manufacturing equipment sales whilst the Chips Acts in both Europe and the US pumped money into the industry. However, this funding seems so far to have done little to stimulate the sector. Despite these challenges, sureCore have managed to successfully navigate the downturn. In fact, we saw an upsurge in business, especially our specialist design services, in the third and fourth quarters.

How is your company’s work addressing this biggest challenge? 

SureCore’s ultra-low power memory solutions can provide our customers with a competitive advantage in the market. Battery powered products in particular continue to evolve, with Edge AI applications, smart watches and health monitors pushing the boundaries of what is possible in small form factor devices. With the upturn in the 2nd half of 2024 and extending into 2025 we are now seeing increased interest in how our novel power saving technology can help developers meet their ever tightening power budgets. We have global representation and continue to attract new customers from across Asia, the US and Europe.

What do you think the industry’s biggest growth areas will be in 2025?

Unfortunately, the outlook for the global economy is still not very encouraging. However, the current enthusiasm for AI continues unabated and this will almost certainly be the big growth driver in the semiconductor industry in 2025. Edge AI is likely to progress if only as a way to offload some of the pressure on data centres. We also believe that smart medical and healthcare solutions will gain further traction as the baby boomer generation starts to really focus not just on ‘life-span’ but on ‘health-span’ extension.

What about industry conferences and events?

Last year we prioritised the foundry events, attending TSMC Technology Symposiums and OIP events, in addition to the GF Technology Summits. As usual these events were well attended and provided excellent networking opportunities. In 2025, we plan to attend several industry events – certainly the foundry events. We are also looking at Embedded World and DAC.

What will be the main product focus areas for your company in 2025? 

The sureCore team will continue to innovate in the ultra-low power memory market, addressing the key issues of both dynamic and leakage power. The cost-effectiveness of both 16nm and 12nm technologies is becoming a key focus for us as product companies are increasingly recognising their benefits. We are also working with lead customers down to 4nm and it is encouraging that our power saving technology seems to migrate well to these more advanced nodes. In addition, although the quantum computing market is still in its infancy, we will continue to push our cryogenic design expertise and engage with as many companies in this sector as possible. 2025 looks set to be another exciting year for sureCore, with many interesting customer projects and deliveries in the pipeline – so watch this space!

Also Read:

sureCore Brings 16nm FinFET to Mainstream Use With a New Memory Compiler

sureCore Enables AI with Ultra-Low Power Memory IP

Agile Analog Partners with sureCore for Quantum Computing

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Arteris Raises Bar Again with AI-Based NoC Design

Arteris Raises Bar Again with AI-Based NoC Design
by Bernard Murphy on 02-19-2025 at 6:00 am
Categories: AI, Arteris, IP

Arteris FlexGen example min

Modern semiconductor devices, a far cry from the chips we once knew, are now highly complex intelligent systems used in datacenters, communications infrastructure, in consumer electronics, automotive, home and office automation, almost everywhere. All such applications build around large subsystems, invariably compute, often AI, sometimes vision/audio engines, always memory and communications subsystems, and more. Each subsystem hosts its own network-on-chip (NoC) connecting sub-functions together, as does the top-level design to connect between subsystems. These structures commonly incorporate a hierarchy of 5-20 NoCs per die/chiplet.

Even when the full system builds entirely on subsystems proven elsewhere, new spec and floorplan constraints may require several of these NoCs to be redesigned or refined, a potentially huge task impacting product schedules. Arteris’ AI-based NoC IP generator, FlexGen, aims to address this challenge. Rick Bye (Director of Product Management, Arteris) and Andy Nightingale (VP Product Management, Arteris) shared their insights with me.

(Source: Arteris, Inc.)

AI for Full-Chip NoC Optimization

We’re already seeing a trend to use AI in global optimization for electronic design: in physical design, in board design, in multiphysics analysis and optimization. These are all problems with huge search spaces, not amenable to traditional optimization techniques, better suited to heuristics learned over trials on historical data.

NoC optimization over a hierarchy of NoCs looks like a very similar problem. Optimizing based on learning over a range of topologies, floorplans, performance and QoS goals, drawing on prior experience which I bet Arteris has in abundance given the years they have been in this business. Then given a new design and network objectives with constraints defined at least to initial estimates, they are able to generate implementations of all those NoCs at the push of a button. I am told this is exactly what their field AEs do to launch evaluations. Pretty neat.

The Caveat

Automating the whole NoC design task through to signoff sounds ideal but reality is never quite that simple. Others have offered this hope but always fall short in lack of repeatability. Optimization may generate significantly different solutions between different design drops, improved certainly in some respects but adding new chaos in floorplanning, timing, QoS, on each new drop. Moreover, constraints provided to guide optimization are never complete, and lack understanding of some system objectives, design expert experience, even future product line objectives.

Automating generation is a very important step forward but it must allow for experts to provide incremental manual overrides where they see a need, and those manually supplied constraints should persist as the design evolves. The Arteris team stressed that this repeatability is why the current FlexGen is based on ML rather than a fancier AI foundation model. Given what I know of AI today, I can understand their caution.

That said, the objective of AI-centric generation is still to find a better PPA solution, faster. On the “faster” metric, Arteris claim generation times dropping from 20 hours to 4 hours, early optimization time (initial trials against a rough floorplan) dropping from 3 hours to 10 minutes and final optimization dropping from 2 weeks to 100 minutes. Even better, such turnaround times enable design teams to explore a wider range of options, getting to better global optima from topology generation to final signoff.

Results

Those are the claims, how does FlexGen deliver in practice? Arteris ran trials on an in-house design (shown above), comparing on manually optimized FlexNoC implementations, tuning against different objectives to explore a range of possibilities. Optimizing just for wire length, they were able to drop total length from over 300 meters to just over 100 meters. Not a very realistic objective of course since this does not factor in performance but is still useful to see where the boundary is. An optimization acknowledging all performance goals still dropped total wirelength to 280 meters, a 10% reduction, with consequences for latency, power and area – improved PPA. Incidentally, a 10% optimization is very much in line with other AI optimizers in EDA.

Dream Chip Technologies used FlexGen on one of their designs, again comparing with a prior FlexNoC implementation. They found a 26% reduction in total wire length, 28% reduction in the longest wire, a 5% reduction in latency, 51% reduction in max latency and a 3% reduction in area. Again, improved PPA. All with a 10x boost in productivity versus effort invested on the manual implementation.

I’m impressed. Automated optimization delivering real improvements but within tightly controlled bounds to preserve repeatability. You can read the press release HERE and explore the product in more detail HERE.

Also Read:

Arteris Raises Bar Again with AI-Based NoC Design

MCUs Are Now Embracing Mainstream NoCs

Arteris Empowering Advances in Inference Accelerators

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2025 Outlook with Veerbhan Kheterpal of Quadric

2025 Outlook with Veerbhan Kheterpal of Quadric
by Daniel Nenni on 02-18-2025 at 10:00 am
Categories: AI, IP, Quadric

Veerbhan Kheterpal

Quadric Inc. is the leading licensor of general-purpose neural processor IP (GPNPU) that runs both machine learning inference workloads and classic DSP and control algorithms.  Quadric’s unified hardware and software architecture is optimized for on-device ML inference. Veerbhan Kheterpal is the CEO and one of the co-founders of Quadric.

Tell us a little bit about yourself and your company.

Quadric is a startup processor IP licensing company delivering a unique general-purpose, programmable neural processor (GPNPU) IP solution. In a marketplace with more than a dozen machine learning “accelerators,” ours is the only NPU solution that is fully C++ programmable. This means that it can run any and every AI/ML graph without the need for any fallback to a host CPU or DSP.  I am one of the three co-founders of the company, which we started back in late 2017.

What was the most exciting high point of 2024 for your company?

2024 was a year of tremendous momentum building for Quadric.  We introduced and began customer deliveries of the 2nd generation of our Chimera GPNPU processor, which now scales to over 800 TOPs.  We also dramatically expanded the size of our model zoo (available in our online DevStudio at our quadric.io website) from only 20 models at the start of the year to over 200 by the close of 2024 thanks to the rapid maturation of our compiler stack.  And that maturation of the technology was accompanied by a growing customer base, that included a public announcement by Denso Corp of Japan that they are basing their future ADAS systems on our GPNPU processors.

What was the biggest challenge your company faced in 2024?

2024 witnessed the beginning of the thinning of the herd of rival NPU architectures in the marketplace.  Far too many IP startups and large IP players all launched AI/ML accelerator efforts from 2020 through 2023 – too many for the market to support them all.   Quadric’s goal in 2024 was to gain the necessary traction in the market to become one of the survivors of the shakeout, and to thrive amid that big shakeout.

Indeed, we did thrive!  We grew the team. We grew the customer base.  We greatly expanded the scope of the product.  We grew revenues by over 600%. And we just kicked off 2025 by forming a Japanese K.K. subsidiary and opening a physical office in Japan – so I think we met the challenge of 2024 head-on and succeeded!

How is your company’s work addressing this biggest challenge?

The challenge of surviving the inevitable thinning of the herd was really a question of highlighting and enhancing the thing that makes Quadric unique among AI/ML solutions: the Quadric Chimera GPNPU is 100% programmable, capable of running any and all ML workloads.  In detailed evaluation after detailed evaluation, we shined by rapidly porting dozens of new, leading-edge models to the platform – many of which compiled straight out of the box with no manual intervention.  The resulting massive increase in the size of the known-working model zoo throughout 2024 cemented in customers’ minds that the promise of full programmability with high performance was a reality, not just a promise.

What do you think the biggest growth area for 2025 will be, and why?

Every year we marvel at how fast AI models changed the previous year.  And every year the industry buckles up for a wild ride to see how much change hits in the coming year.  2025 is no different – in fact, 2025 has already seen huge changes.  DeepSeek so disrupted the conventional wisdom that stock markets quaked, politicians pontificated, and technologists paused to wonder.  And that was only within the first 4 weeks of the year!

These changes won’t slow down.  Look at the automotive market, for instance.  One year ago none of the leading OEMs and Tier 1s had vision-language models (VLMs) on their Must Have list.  VLMs at the time were barely registering in academia.  Now, VLMs are fast becoming requirements.

How is your company’s work addressing this growth?

Quadric welcomes rapid change in AI models.  Quadric processors can run every ML operator, every ML graph.  The more change the better for our business!   Quadric is continuously adding ports of new algorithms to our processors. Today we support all the major modalities of ML inference, including a variety of leading-edge transformers.  Adding a demonstration of a new ML model is a pure software effort for us, and we are focused in 2025 on widening the array of models further with each periodic software release.

What conferences did you attend in 2024 and how was the traffic?

In 2024 we attended quite a few smaller, focused technical conferences: Embedded Vision Summit, IPSoC, ACC, Innovex (part of Computex), Design Solution Forum, EdgeTech, and we held two of our own private seminars.   Those tailored conferences were robustly attended and the big mega shows – such as CES – also did well.

Will you attend conferences in 2024? Same or more?

Quadric will be expanding our outreach marketing programs in 2025 commensurate with our business growth.  Look for us to be at more events and more prominent sponsors of those venues that bring together the chip and systems architects that make programmable processor IP decisions.

How do customers engage with your company?

The first step is easy: visit our online DevStudio at www.quadric.io.  We have hundreds of benchmark performance figures – and full source code of all those benchmarks – right on the website in Studio.  And our worldwide sales and applications team stands ready to follow-up with training and support to help you decide if Quadric’ Chimera GPNPU processor is right for your next SoC design.

Also Read:

Tier1 Eye on Expanding Role in Automotive AI

A New Class of Accelerator Debuts

The Fallacy of Operator Fallback and the Future of Machine Learning Accelerators

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Samtec Advances Multi-Channel SerDes Technology with Broadcom at DesignCon

Samtec Advances Multi-Channel SerDes Technology with Broadcom at DesignCon
by Mike Gianfagna on 02-18-2025 at 6:00 am
Categories: Events, Samtec, Semiconductor Services

Samtec Advances Multi Channel SerDes Technology with Broadcom at DesignCon

There were many announcements and significant demonstrations of new technology at the recent DesignCon. The show celebrated its 30th anniversary this year and it has grown quite a bit. As in past years Samtec had a commanding presence at the show. There will be more about that in a moment, but first I want to focus on a substantial demo that teamed Samtec’s interconnect technology with Broadcom’s SerDes technology for the first time. I have many memories of my time at eSilicon. Some of those memories center on how difficult it was to compete with Broadcom’s SerDes. The demo at DesignCon brought together this substantial capability with Samtec’s industry-leading interconnect to open new horizons. Let’s examine how Samtec advances multi-channel SerDes technology with Broadcom at DesignCon.

Interconnect Technology

The key enabling technology from Samtec for the DesignCon demo with Broadcom was its Si-Fly® HD 224 Gbps PAM4, co-packaged and near chip capabilities. As the name implies, these products offer the system designer flexibility with either co-packaged interconnect with the chip on the same substrate or near-chip interconnect. The die and connector on substrate configuration creates the need for broader ecosystem collaboration since the silicon provider, interconnect provider and OSAT all need to work together to achieve a reliable product. Broader collaboration is a trend in advanced design styles like this.

The image at the top of this post shows what these connectors look like.

To get to high-density 224 Gbps PAM4 channel capability, the co-packaged option offers the lowest loss signal transmission from the package to the front panel or backplane while providing the highest density. Samtec’s Eye Speed® Hyper Low Skew Twinax cable technology supports 224G signaling with an industry leading 1.75 ps/m max intra-pair skew. Digging a bit deeper, placement of Flyover® cable solutions on, or near, the chip package improves transmission line density and extends signal reach in high-performance applications. More information on this technology and the demo is coming.

The Demo

The demo at DesignCon showcased an evaluation platform with Broadcom’s 200 Gbps SerDes technology. The Samtec Si-Fly HD CPC on-package high-speed cable systems and OSFP front panel connectors were used for the interconnect. The Broadcom 200 Gbps chips and these connectors were attached to the package to maximizes system performance.

For those who want the details, here they are for the two demo platforms that were used.

Platform #1

  • Evaluates the performance of the new Si-Fly HD cable assembly
  • The 200 Gbps signal routes through 30 mm of substrate and loops back through 150 mm of Samtec Eye Speed Hyper Low Skew twinax cable
  • BER is e-13, error-free. Total channel loss is 20 dB at 212.5 Gbps

Platform #2

  • Mid-board to front panel and back
  • 200 Gbps signal travels through Si-Fly HD cable assembly (25 cm Eye Speed Hyper Low Skew Twinax) with OSFP front panel connector
  • One meter DAC cable, rated at 224G
  • BER e-9, total channel loss 48 dB at 212.5 Gbps
  • Performance will improve with release of 224G Flyover OSFP

A photo of the demo running live at the show is shown below. Note there is a link coming to a detailed video of this demo done live from the Samtec booth at DesignCon.

Samtec/Broadcom Demo at DesignCon

Samtec at DesignCon

As I discussed previously, Samtec has a tendency to dominate DesignCon. This year was no different. Beyond the compelling demos at the Samtec booth, Samtec products were also featured in demos with its partners throughout the show floor. In particular, there were noteworthy demos at the Rohde & Schwarz and Keysight booths.

Samtec was also quite visible in the technical program with the following contributions.

Panels

  • PCI Express & PAM4: Balancing Silicon & Interconnect Interdependencies for 128 GT/s
  • Expert Discussion: How Will AI Applications Affect High Speed Link Design?

Presentations

  • Reduced Order Geometric Macro Model of PCB Fiberglass Spatial Variation for Skew & Impedance Prediction
  • Transmitter Power Spectral Density Noise Impact for 200 Gb/s PAM 4 per Lane
  • Direct to Substrate 200G-PAM4 Co-Packaged Connectors: Is it a Reality?
  • Beyond 200G: Brick Walls of 400G links per Lane
  • Accurate Adapter Removal in High Precision Low Loss RF Interconnect Characterization
  • Determining the Requirements, Die vs Package vs Board: Multi-Level Power Distribution Network Design

To Learn More

You can learn more about Samtec’s Si-Fly HD co-packaged and near-chip systems here. You can also learn about another 224 Gbps PAM4 effort with Synopsys here. And finally, you can check out the live video of the important demo with Broadcom here.  And that’s how Samtec advances multi-channel SerDes technology with Broadcom at DesignCon.

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Outlook 2025 with David Hwang of Alchip

Outlook 2025 with David Hwang of Alchip
by Daniel Nenni on 02-17-2025 at 10:00 am
Categories: 3D IC, AI, Alchip, Chiplet, Semiconductor Services

Dave Huang

Dave Hwang joined Alchip in 2021 as General Manager of Alchip’s North America Business Unit.  He also serves as Senior Vice President, Business Development.  Prior to join Alchip, Dave served as Vice President, Worldwide Sales and Marketing for Global Unichip and in a variety of management and technical roles at TSMC.  He holds a Ph.D. in Material Science and Engineering from North Carolina State University.

What was the most exciting high point of 2024 for your company?

That’s a great question.  It’s been a very hectic year, for sure.  Alchip will, more than likely, achieve over $1 billion in revenue in 2024. That’s a huge milestone for any company.  But the biggest, most important milestones are our 2nm shuttle tape-out in September and our 3DIC design flow readiness, which we will announce in January.

What was the biggest challenge your company faced in 2024?

By far, the biggest challenge has been finalizing the design flow for advanced packaging, which has its own set of unique challenges.  We’ve brought a new level of flexibility to our design platform to accommodate increasingly specific targets for both power consumption and high performance.

How is your company’s work addressing this biggest challenge?

Ultimately, in the end, we introduced, and are now accepting designs, for our 3DIC design flow that has both flexibility and robustness.  Alchip’s silicon-proven 3DIC design flow optimizes 3DIC designs along three critical dimensions: power delivery, die-to-die electrical interconnect, and system-wide thermal characterization.

What do you think the biggest growth area for 2025 will be, and why?

System companies, no doubt have become huge consumers of ASICs.  They see them as critical differentiators, particularly in AI and HPC applications.  We’re fairly aligned with the thinking that, in the not-too-distant future, system company investments in the development of ASICS are estimated to reach over several million AI chips in 2027-2028, creating a $60-$90 billion market.

How is your company’s work addressing this growth?

We are taking a holistic systems approach, developing a design platform to accommodate advanced packaging, advanced chiplet, and advanced process technologies.  We’re doubling down on adding engineering and resources throughout our global design centers to address market-specific HPC, AI, and automotive demand.

What conferences did you attend in 2024 and how was the traffic?

We take a significant presence in all TSMC events … The TSMC Technology Symposiums and OIP.  And we do it globally.  We also exhibit at industry events like Chiplet Summit and the AI Hardware Summit.

Will you attend conferences in 2025? Same or more?

We’ll add the Open Compute Platform to our plan, and we’ll look next to expand our presence in industry events and conferences.

How do customers engage with your company?

There is no one way.  Nearly every company is different, so we take a true ASIC approach and have a strategic flexible engagement model.  This allows companies to engage in multi-ways, through many entry points along the value chain.  Essentially, we customize the ASIC value chain to meet the specific needs.

Additional questions or final comments? 

Without a doubt, the AI/HPC market is the place to be.  The key differentiator will be advanced packaging, which will be absolutely required in all high-performance computing applications.  We see ourselves as leaders in this area.

Also Read:

Alchip is Paving the Way to Future 3D Design Innovation

Alchip Technologies Sets Another Record

Collaboration Required to Maximize ASIC Chiplet Value

Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems

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Synopsys Expands Optical Interfaces at DesignCon

Synopsys Expands Optical Interfaces at DesignCon
by Mike Gianfagna on 02-17-2025 at 6:00 am
Categories: Events, IP, Synopsys

Synopsys Expands Optical Interfaces at DesignCon

The exponential growth of cloud data centers is well-known. Driven by the demands of massive applications like generative AI, state-of-the-art data centers present substantial challenges in terms of power consumption. And AI is poised to drive a 160% increase in data center power demand while also increasing demands on storage and communication efficiency, throughput and latency. Cisco has estimated that ASIC SerDes power consumption has increased 25X over the past decade or so. Something needs to change.

The core communication method for these new data centers is based on optical networking. At the recent DesignCon, Synopsys focused on how to reduce power in data center comms, offering insights, strategies and real solutions. The company is working on an innovative new approach to optical communications that essentially reduces complexity to improve power and latency. There was a presentation on this topic and a live demonstration. I’ll provide some details on what Synopsys presented and demonstrated at DesignCon. I also had a chance to speak live with the presenter to get some of the backstory. Let’s examine how Synopsys expands optical interfaces at DesignCon.

The Presentation

Priyank Shukla

Priyank Shukla, product line director for HPC IP at Synopsys presented Linear Eletro-Optical Interfaces: What, Why, When, and How? in the Chiphead Theater at DesignCon. Priyank is responsible for the deployment of Synopsys’ High Speed SerDes IP in complex SoCs. He has broad experience in analog, mixed-signal design with strong focus on high performance compute SoCs. He actively contributes as an IEEE802.3 voter, playing a pivotal role in shaping industry standards. A graduate of IIT Madras, Priyank has a US patent on low power RTC design.

Priyank described some compelling trends. He cited the 160% increase in data center power demand statistic. A key contributor to this is data communications. He explained that interconnects contribute about 27% of total data center power and interconnect power has increased 46x from 2010 to 2024. To complete the picture, he discussed the trends in how data is communicated. In a word, it’s done with light.

Optical interconnects are becoming crucial in data centers as they address the limitations of electrical copper interconnects in high data rate environments approaching 224 Gbps, where copper’s effectiveness diminishes. This creates a need for denser interconnect networks, which in turn increases power consumption. Optical solutions, however, can extend reach and offer scalability in data center topologies. The industry is moving towards optical interconnects to reduce latency and signal integrity issues, which helps with data center expansion.

So, the question is how to reduce the power demands of optical networking interfaces. Priyank described a direct drive/linear interface to meet this challenge. The term “less is more” comes to mind. A conventional optical interface typically has re-timer logic and a DSP to facilitate reliable communication. These items add parts count, size, cost, and power. It turns out the PHY on the transmission end can do more in advanced nodes.

Priyank explained that the switch ASIC’s PHY can directly drive an optical engine on a pluggable module. This optical engine does not include re-timers or DSPs. It does the job with linear amplifiers. This streamlined approach leads to a more compact and efficient design, making the system less complex and highly functional. The figure below illustrates what this new and simplified architecture looks like.

Direct Drive/Linear Interface (Source: Synopsys, Inc.)

Implementing an approach like this can certainly be done if you’re designing the complete system and all of its components. This is not the case for the companies building massive data centers. These organizations rely on a worldwide supply chain to deliver the required components. So predictable interoperability between vendors to deliver this new capability is required. The next two sections of this post will look at this challenge.

The Demonstration

Developing the specifications required to ensure interoperability between vendors for any complex design is daunting. That is certainly true for linear optical interfaces. I’ll get to some details on that in a moment. But first, let’s look at the proof points that are already available. Synopsys has been demonstrating examples of how its IP works with other vendor’s technology for a while.

At ECOC 2023, Synopsys, in collaboration with OpenLight, a photonics venture formed with Juniper Networks, demonstrated the optical eye performance of a linear electrical-optical-electrical link transceiver. At DesignCon, Synopsys demonstrated its 112G Ethernet PHY IP enabling a linear pluggable optics (LPO) module diagnostic with TeraSignal’s ultra-low power linear driver – the industry’s first optical diagnostic interoperability at 112Gbps. 

Using a digital eye monitor, the transmitted signal was captured and analyzed and then settings were updated to minimize errors. It was shown that the Synopsys 112G Ethernet PHY IP receiver equalizes the incoming signal and achieves a near-zero bit error rate, highlighting its reliability and high performance in data transmission. Below is a photo of the demonstration hardware.

Synopsys and Terasignal Demo DesignCon 2025

The Backstory

I had the opportunity to speak with Priyank Shukla recently. We discussed his presentation at DesignCon and Priyank provided a lot of color regarding what will be needed to make the new direct drive/linear interface broadly available. To achieve this goal, standards will need to be developed regarding how the pieces work together and test equipment and software will need to be built to verify compliance. 

This is a complex process, but the payoff is substantial when you consider the power crisis currently facing large data center build out. Priyank described the OIF 112G-Linear Optical Drive Standard effort that aims to define the electrical standards to ensure linear interoperability. Priyank went on to explain that there will be a need to measure photonic parameters to verify compliance, and a different type of test equipment will be needed to achieve this goal. This represents new investment and opens new markets for test and measurement vendors.

Priyank described some of the new parameters being defined by OIF to validate compliance. These include voltage modulation amplitude (VMA) and electrical eye closure quaternary (EECQ). These are new measurements that are under development. It is expected the standard will be ready later in 2025, so the required test equipment and software needed to measure these parameters is also under development.  Achieving mainstream deployment of direct drive/linear interfaces has brought many parts of the supply chain together.

Beyond 112G, Priyank also described work on a 224G standard. Achieving a direct drive/linear interface at this speed is more difficult and will require yet more innovation and new standards. And beyond these standards, Priyank explained that the PCI SIG is also working on optimized interfaces for PCIe.

My discussion with Priyank provided more detail regarding the complexity of this new interface and why it is indeed worth the effort. I got a better appreciation for the importance of the Synopsys IP and the company’s efforts to collaborate across the ecosystem to make the vision a reality.

To Learn More

TeraSignal issued a press release describing more details about the DesignCon demo. It is entitled, TeraSignal Demonstrates Interoperability with Synopsys 112G Ethernet PHY IP for High-Speed Linear Optics Connectivity and you can read the release here.

You can also learn more about direct-drive electro-optical interfaces from this informative technical bulletin.

And if you missed DesignCon, Synopsys will be showing the TeraSignal demo at the upcoming Optical Fiber Communications Conference and Exhibition (OFC), to be held in early April at Moscone Center in San Francisco. You can find Synopsys in booth 2818.

And that’s how Synopsys expands optical interfaces at DesignCon.

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Trump whacking CHIPS Act? When you hold the checkbook, you make up the new rules

Trump whacking CHIPS Act? When you hold the checkbook, you make up the new rules
by Robert Maire on 02-16-2025 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services
1 Comment

Robert Maire Semiconductor Advisors
  • News reports that Trump will change CHIPS Act to suit his views
  • We specifically predicted this months ago as deals closed 11th hour
  • Blue states, enemies list & foreign entities likely to get cut
  • Big changes/cuts likely to a program Trump roundly criticized

Reuters: Exclusive: Trump prepares to change US CHIPS Act conditions, sources say

We had said that Trump would likely stop the checks on CHIPS Act for funding even on done deals. For all we know he might even try to claw back checks that are already cashed.

As with everything else we are seeing from the new administration he will likely gut what he doesn’t like or turn it into something that benefits his views.

Blue states, political enemies, foreign firms, China deals – all at risk

The Reuters report suggests that companies with a China angle may get scrutinized or cut. Globalwafers of Taiwan was specifically mentioned. Trump has also accused Taiwan of stealing the Chip industry from the US and may want to seek revenge on Taiwanese companies….maybe even including TSMC.

Projects in Texas and Arizona are likely OK for the most part. Ohio being a swing state likely would make it safer from getting whacked.

Micron in Idaho is likely OK but Schumer sponsored Micron New York will likely get more scrutiny.

Additional projects like the national semiconductor technology center which was planned to go hand in hand with a HIGH NA EUV installation in New York may also be at risk.

Companies doing business in China, such as Intel, mentioned in the Reuters article may also get extra scrutiny.

Basically, as we have seen with other things, the CHIPS Act will get twisted for political advantage

DEI in CHIPS Act likely to DIE

The CHIPS Act had some controversial clauses that we, and many others, thought went too far. Such as guaranteed child care for workers.

Union workers, another clause, is not too bad in our view, as the government has long supported unions, but with Musk around now, unions may not be so safe.

Trump loves to “renegotiate” done deals…..

Trump is famous for renegotiating deals, stiffing contractors, reneging on deals. We are sure Trump will want to improve on every CHIPS Act deal and will likely withhold funding to extract better terms.

Trump doesn’t need a reason or an excuse to change , gut or just plain renege on CHIPS Act deals. Saving money is a core principle that Musk is wielding as a hatchet.

The stocks

Aside from the bad Applied Materials news this evening. This news about the CHIPS Act just adds to the many headwinds facing the industry; China, crappy memory pricing, Intel & Samsung falling behind, weak trailing edge, emerging China competition both in chips and chip equipment, weak PC and mobile phone etc, etc.

Whacking the CHIPS Act does not just impact the $39B associated with it but likely hundreds of billions of projects that CHIPS Act was a catalyst for.

Lets also not forget the goal of bringing back semiconductor dominance to the US. But then again, Trumps view is that we can bring back chips to the US by tariffing the heck out of imported chips. Somehow I don’t see that working.

The CHIPS Act was a nice idea while it lasted……

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor), nspecializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

KLAC Good QTR with AI and HBM drive leading edge and China is Okay

Consumer memory slowing more than AI gaining

Posted on

AMAT- In line QTR – poor guide as China Chops hit home- China mkt share loss?

AMAT- In line QTR – poor guide as China Chops hit home- China mkt share loss?
by Robert Maire on 02-16-2025 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services

Robert Maire Semiconductor Advisors
  • QTR was just “in-line” but guide was below expectations
  • We think its not just China export rules but share loss as well
  • Leading edge is strong but obviously not enough to offset China
  • Memory remains weak-Foundry (TSMC) is the primary driver
Headwinds slow growth to flat

Applied reported $7.166B in revenues and Non GAAP EPS of $2.38 versus street of $7.16B and EPS of $2.30.

Applied is projecting $7.1B +-$400M and EPS DOWN at $2.30 +-$0.18 versus street expectation of $7.2B and $2.29 in EPS.

Applied is suggesting that the flatness lasts only a quarter or two but we think it likely lasts throughout the year

AMAT blames China export restrictions for 100% of weakness

We think share loss in China adds to the weakness

We continue to hear that domestic Chinese semiconductor equipment makers are taking a larger and larger percentage of WFE sales in China. Data from industry sources appears to clearly support that trend.

Chinese chip makers are doing all they can to avoid buying American tools and are buying more and more domestic tools. This trend is not going to change or reverse any time soon.

We would also add that China has been buying any and all US equipment that wasn’t nailed down in anticipation of restrictions that have finally showed up. Warehouses are likely bursting at the seams with equipment that still needs to be put to use.

So the reality is that China is a “triple play” of restrictions, inventory gluts and domestic tool maker share competition.

Only the inventory glut will improve over time, share loss and restrictions are not likely to get better.

The industry is quickly becoming a monopoly of one… TSMC

Samsung and Intel get further behind….

Although AI is great, it is virtually 100% TSMC as Intel and Samsung have fallen further behind. We don’t see with Samsung or Intel as big capex spenders in the near term.

So its really up to TSMC to carry the flag of AI chips.

This means that AMAT has fewer customers who are spending big……

HBM is great but the rest of memory still sucks…..

As we have stated a number of times, don’t expect memory to ramp overall capex. Applied commented on memory weakness with the obvious exception of HBM.

You have to remember that eventually HBM supply will catch up to demand and that means pricing and investment will both decline.

Eventually, all unique memory types become commodities…..that’s the problem with the memory market, its a constant race to the bottom

2025 looking at a middling 0% to 5% WFE growth Y/Y

We are increasingly thinking that 2025 could be a flat year over 2024. With added headwinds from China and only TSMC at the bleeding edge and memory weak its hard to see where growth is coming from.

We have been warning forever, that the recovery is slower than prior cyclical recoveries, we are clearly seeing that right now.

The stocks

AMAT was down about 5% in the after market which we think is an appropriate reaction.

The headwinds are getting too large for even bullish analysts to ignore so we will likely see a series of cuts in numbers for not just AMAT but across the industry as we get closer to a flat WFE outlook.

There is likely some collateral damage in other equipment names as the weaker outlook from the industry leader settles in

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies.
We have been covering the space longer and been involved with more transactions than any other financial professional in the space.
We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.
We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

KLAC Good QTR with AI and HBM drive leading edge and China is Okay

Consumer memory slowing more than AI gaining

If you believe in Hobbits you can believe in Rapidus

 

 

Podcast EP274: How Axiomise Makes Formal Predictable and Normal with Dr. Ashish Darbari

Podcast EP274: How Axiomise Makes Formal Predictable and Normal with Dr. Ashish Darbari
by Daniel Nenni on 02-14-2025 at 10:00 am

Dan is joined by Dr. Ashish Darbari, CEO of Axiomise. Axiomise was founded in 2017 by Dr. Darbari, who has spent over two decades in the industry and top research labs increasing formal verification adoption. At Axiomise, they believe the only way to make formal methods mainstream for all semiconductor design verification is to enable and empower the end-user of formal – the hundreds of designers and verification engineers in the semiconductor industry. Dr. Darbari was joined by Neil Dunlop in 2022. Between Neil and Ashish, the Axiomise leadership team has over 60 years of formal verification experience on various projects.

Dan explores the capabilities, impact and plans of this unique company with Ashish. The various types of training Axiomise offers, from instructor-led, to on-demand to custom are reviewed. Ashish also describes the broad services work Axiomise engages in as well as some powerful, high impact apps the company has developed. Examples include formalISA, which can establish ISA compliance via mathematical proofs for RISC-V processors.

The footprint app is also discussed, which provides an efficient and fast method for identifying redundant design components, allowing architects and designers to exhaustively find wasted area in a design while focusing on power and performance.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.