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Semiconductor Expert Forum

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Upcoming Webinar: Accelerating Semiconductor Design with Generative AI and High-Level Abstraction

Upcoming Webinar: Accelerating Semiconductor Design with Generative AI and High-Level Abstraction
by Daniel Nenni on 03-27-2025 at 10:00 am
Categories: AI, EDA, Events, Rise Design Automation

RDA SemiWikiblog graphic

We have been hearing so much lately about the power of AI and the potential of technologies like agentic AI to address the productivity gap and complexities of semiconductor designs of today and tomorrow.  Currently, however, the semiconductor industry has been slow to adopt generative and agentic AI for RTL design code.   There have been many reasons for this hesitation such as concerns about the quantity and source of RTL-based training data, plus the verification, quality and reliability of any AI generated code that is so critical for the success of the project. However, to stay competitive, the industry must embrace AI-driven hardware design to lower costs, expand accessibility, improve productivity and drive innovation.

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A new EDA startup, Rise Design Automation (RDA), has developed a solution that enables the use of generative AI for design, verification and exploration that overcomes many of these objections and coupled with the creativity of the human-in-the-loop, dramatically improves productivity to deliver high-quality RTL that is both verifiable and implementable.

RDA in partnership with SemiWiki will host a live webinar,  𝗔𝗰𝗰𝗲𝗹𝗲𝗿𝗮𝘁𝗶𝗻𝗴 𝗦𝗲𝗺𝗶𝗰𝗼𝗻𝗱𝘂𝗰𝘁𝗼𝗿 𝗗𝗲𝘀𝗶𝗴𝗻 𝘄𝗶𝘁𝗵 𝗚𝗲𝗻𝗲𝗿𝗮𝘁𝗶𝘃𝗲 𝗔𝗜 𝗮𝗻𝗱 𝗛𝗶𝗴𝗵-𝗟𝗲𝘃𝗲𝗹 𝗔𝗯𝘀𝘁𝗿𝗮𝗰𝘁𝗶𝗼𝗻 where you can learn more about this solution and have an opportunity to ask questions directly to the technical experts.  In this webinar you will learn how Rise uses a unique combination of raising design abstraction, a comprehensive high-level toolchain and a seamlessly integrated generative AI solution to deliver high quality RTL and architectural innovation in a fraction of the time.

These three technologies together are the perfect combination and complement to each other.   Once the design abstraction is raised beyond RTL, all of a sudden the massive amount of high-level code(C, C++, Python, etc.) that existing LLM’s have been trained on, become a very effective training set for generating quality high-level code.   This overcomes the questions and concerns of RTL-based training data.  Built with industry-first high-level agents and easily deployable with pretrained language models, the Rise AI solution translates natural-language intent into human-readable, modifiable, and verifiable high-level design code—reducing manual effort and accelerating adoption.

Rather than relying solely on AI for Quality of Results (QoR), Rise augments human expertise with a comprehensive high-level toolchain for design, verification, debug, and architectural exploration to generate highly optimized RTL code.  Raising design abstraction and high-level design has been proven over many years to dramatically improve productivity and quality of both design and verification but has not seen widespread adoption due to multiple factors.  These often include adoption/learning curve, lack of expertise in a project, knowing how to consistently get needed QofR compared to hand-coded RTL, verification questions, etc.   Generative AI with specialized high-level tool and language knowledge complementing human creativity and expertise with both assistants and coding and optimization agents can help overcome these challenges – like having a high-level design expert with you at all times.  Additionally, Rise has added support for untimed and loosely-timed SystemVerilog to the existing HLS languages of C++ and SystemC, so that RTL designers and project teams can choose which language best fits both their expertise and adoption comfort level.

This webinar is designed for both engineers and project managers alike.   Attendees will gain insights on into practical applications of AI-driven design methodologies and how AI can be incorporated into the design process without compromising verification rigor. This webinar is designed for both engineers and project managers alike. As SystemVerilog is new as a high-level language, it will then dive into a technical explanation of exactly what it looks like and how it works along with the features of the high-level tool chain and how RTL and verification engineers could use it.   With that foundation, it will then explain the details of the generative AI solution and how it is built and works both to assist, generative, optimize and explore.   The webinar will then conclude with a live demonstration of both the high-level tool chain running on a real design, with code walk-through, simulation results, etc followed by the AI solution interacting with both the design and the tool chain to assist, code-complete, optimize and explore various PPA solutions.   There will be plenty of time for an interactive Q&A directly to the technical team.

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Also Read:

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An Imaginative Approach to AI-based Design

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Vision-Language Models (VLM) – the next big thing in AI?

Vision-Language Models (VLM) – the next big thing in AI?
by Daniel Nenni on 03-27-2025 at 6:00 am
Categories: AI, IP, RISC-V, Semidynamics

Semidynamics AI SemiWiki

AI has changed a lot in the last ten years. In 2012, convolutional neural networks (CNNs) were the state of the art for computer vision. Then around 2020 vison transformers (ViTs) redefined machine learning. Now, Vision-Language Models (VLMs) are changing the game again—blending image and text understanding to power everything from autonomous vehicles to robotics to AI-driven assistants. You’ve probably heard of the biggest ones, like CLIP and DALL-E, even if you don’t know the term VLM.

Here’s the problem: most AI hardware isn’t built for this shift. The bulk of what is shipping in applications like ADAS is still focused on CNN never mind transformers. VLM? Nope.

Fixed-function Neural Processing Units (NPUs), designed for yesterday’s vison models, can’t efficiently handle VLMs’ mix of scalar, vector, and tensor operations. These models need more than just brute-force matrix math. They require:

  • Efficient memory access – AI performance often bottlenecks at data movement, not computation.
  • Programmable compute – Transformers rely on attention mechanisms, softmax etc. that traditional NPUs struggle with.
  • Scalability – AI models evolve too fast for rigid architectures to keep up.

AI needs to be freely programable. Semidynamics provides a transparent, programable solution based on the RISC-V ISA with all the flexibility that provides.

Instead of forcing AI into one-size-fits-all accelerators, you need architectures that let you build processors better suited to your AI workload. Semidynamics’ All-In-One approach delivers all the tensor, vector and CPU functionality required in a flexible and configurable solution. Instead of locking into fixed designs, a fully configurable RISC-V processor from Semidynamics can evolve with AI models—making it ideal for workloads that demand compute designed for AI, not the other way around.

VLMs aren’t just about crunching numbers. They require a mix of vector, scalar, and matrix processing. Semidynamics’ RISC-V-based All in one compute element can:

  • Process transformers efficiently—handling matrix operations and nonlinear attention mechanisms.
  • Execute complex AI logic efficiently—without unnecessary compute overhead.
  • Scale with new AI models—adapting as workloads evolve.

Instead of being limited by what a classic NPU can do, our processors are built for the job. Crucially they are fixing AI’s biggest bottleneck: memory bandwidth. Ask anyone working in AI acceleration—memory is the real problem, not raw compute power. If your processor spends more time waiting for data than processing it, you’re losing efficiency.

That’s why Semidynamics’ Gazzillion™ memory subsystem is a game-changer:

  • Reduces memory bottlenecks – Feeds data-hungry AI models with high efficiency.
  • Smarter memory access – copes with slow, external DRAM by hiding its latency.
  • Dynamic prefetching – Minimizes stalls in large-scale AI inference.

For AI workloads, data movement efficiency can be as important as FLOPS. If your hardware isn’t optimized for both, you’re leaving performance on the table.

AI shouldn’t be held back by hardware limitations. That’s why RISC-V processors like our All-In-One designs are the future. And yet most RISC-V IP vendors are struggling to deliver the comprehensive range of IP needed to build VLM capable NPUs. Semidynamics is the only provider of fully configurable RISC-V IP with advanced vector processing and memory bandwidth optimization—giving AI companies the power to build hardware that keeps up with AI’s evolution.

If your AI models are evolving, why is your processor staying the same? The AI race won’t be won by companies using generic processors. Custom compute is the edge AI companies need.

Want to build an AI processor that’s made for the future? Get in touch with Semidynamics today.

Also Read:

2025 Outlook with Volker Politz of Semidynamics

Semidynamics: A Single-Software-Stack, Configurable and Customizable RISC-V Solution

Gazzillion Misses – Making the Memory Wall Irrelevant

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CEO Interview with Jonathan Klamkin of Aeluma

CEO Interview with Jonathan Klamkin of Aeluma
by Daniel Nenni on 03-26-2025 at 10:00 am
Categories: CEO Interviews

Jonathan Klamkin Aeluma

 

Jonathan Klamkin, Ph.D. is founder and CEO of Aeluma, Inc. (ALMU). He is a Professor at the University of California Santa Barbara and has previously worked at Boston University, Scuola Superiore Sant’Anna, MIT Lincoln Laboratory, and BinOptics Corp. (a laser diode manufacturer that was acquired by Macom in 2015). He is the recipient of numerous awards including the NASA Young Faculty Award, the DARPA Young Faculty Award, and the DARPA Director’s Fellowship. He has published more than 230 papers, holds more than 30 issued and pending patents, and has delivered more than 120 invited presentations to industry, government and the academic community. Dr. Klamkin has nearly 25 years of experience in integrated photonics, compound semiconductors, and silicon photonics. He and team members have grown Aeluma from its conception into a transformative semiconductor company with a U.S.-based operation capable of producing high-performance chips at scale.

Tell us about your company.

At Aeluma, we are redefining semiconductor technology by integrating high-performance materials with scalable silicon manufacturing. Our goal is to bridge the gap between compound semiconductors and high-volume production, enabling AI, quantum computing, defense and aerospace, 3D sensing and next-generation communication applications. Traditionally, these high-performance semiconductors have been limited to low-volume, niche markets, but Aeluma’s proprietary approach allows us to scale this cutting-edge technology for mass-market adoption.

We have built a U.S.-based semiconductor platform, leveraging both internal R&D and foundry partnerships, to develop and commercialize next-generation chips. With strategic collaborations with NASA, DARPA, DOE, and the Navy, we are accelerating the development of AI-driven photonics, quantum dot lasers, optical interconnect solutions and high sensitivity detectors.

What problems are you solving?

As AI, quantum computing, high-performance computing (HPC), and sensing systems evolve, the demand for higher-speed, lower-power, and more scalable semiconductor solutions is growing rapidly. Traditional semiconductor architectures struggle to meet these demands, particularly in areas like AI acceleration, high-speed optical interconnects, quantum networking, and 3D sensing. Aeluma solves this by integrating compound semiconductors with large-diameter substrates (ex. 200 and 300mm), enabling mass production of photonic and electronic devices that significantly outperform existing solutions. By bringing monolithically integrated light sources to silicon photonics, we are eliminating a key bottleneck in AI and high-performance computing, improving speed, efficiency, and scalability beyond the limitations of conventional semiconductor technology.

What application areas are your strongest?

Aeluma’s technology is making a transformative impact in AI infrastructure, defense, quantum computing, and next-generation sensing. In AI and HPC, our quantum dot laser technology and high-speed optical interconnects enable ultra-fast, low-power data transfer, solving the bandwidth and power challenges facing next-generation AI accelerators and cloud infrastructure. In defense and aerospace, we work with NASA, DARPA, and the Navy to advance high-sensitivity sensing, quantum networking, and next-generation communications. These solutions are critical for autonomous systems, secure satellite communications, and precision navigation systems. In quantum computing, our silicon-integrated photonic materials are paving the way for scalable quantum networking and next-gen optical processors, essential for unlocking the next era of computational power. Additionally, our technology is driving advancements in mobile, AR/VR, and automotive lidar, where precision, performance, and scalability are paramount.

What keeps your customers up at night?

The biggest challenge for our customers is scaling AI and high-performance computing without hitting power, speed, and latency bottlenecks. As AI models grow, data centers are pushing the limits of existing semiconductor technology. Customers are looking for breakthroughs in chip architecture to maintain performance and efficiency as AI, quantum computing, and 6G networks continue to scale. For 3D sensing, customers desire low-cost and scalable approaches that are also eye safe. Another major concern is supply chain resilience. The semiconductor industry has seen significant disruptions, and companies are looking for reliable, scalable solutions with a strong U.S.-based supply chain. Aeluma is positioned to address both performance challenges and supply chain reliability, making next-gen AI and quantum computing infrastructure more scalable and accessible.

What does the competitive landscape look like and how do you differentiate?

The semiconductor industry is evolving rapidly, with NVIDIA, Intel, and Broadcom investing heavily in AI acceleration and optical networking. However, traditional chip architectures were not designed for the demands of modern AI and quantum computing. While some competitors are focused on incremental improvements, Aeluma is delivering fundamental advancements in semiconductor technology. Our differentiation comes from monolithic integration of quantum dot lasers with silicon photonics, which enables faster, more efficient AI acceleration, optical interconnects, and quantum networking. Our scalable U.S.-based manufacturing approach also sets us apart, allowing us to deliver breakthrough performance while maintaining cost efficiency at scale.

What new features/technology are you working on?

We are at the forefront of AI acceleration, quantum networking, and high-speed optical data transfer. Some of our key innovations include advancing the integration of quantum dot lasers with silicon photonics, enabling high-speed, low-power optical interconnects that are essential for next-generation AI accelerators, cloud data centers, and HPC systems. Additionally, we are developing advanced SWIR (shortwave infrared) photodetectors for defense and aerospace, energy, mobile, AR/VR, and automotive applications, providing high-sensitivity imaging and sensing for facial identification, 3D imaging, and autonomous systems, and communications. Our work in next-gen optical computing solutions is also driving breakthroughs in photonics-based AI acceleration and quantum processing, addressing the speed and power limitations of traditional semiconductors. These innovations position Aeluma at the forefront of semiconductor evolution, shaping the future of AI, quantum computing, and HPC.

How do customers normally engage with your company?

Aeluma partners with leading AI, defense and aerospace, and semiconductor companies, collaborating to integrate high-performance photonics and semiconductor solutions into their next-generation platforms. We engage with AI and HPC leaders to optimize optical interconnect solutions for next-gen AI accelerators, helping them achieve faster processing speeds with lower power consumption. Our strategic partnerships with various government agencies and the DOD support the development of high-sensitivity imaging, quantum networking, and autonomous systems, ensuring. Additionally, we work closely with semiconductor manufacturers and foundries to scale high-performance semiconductors for mass-market adoption. Whether through joint development programs, direct technology licensing, or research collaborations, our customers engage with us to accelerate their technology roadmaps, improve system performance, and bring cutting-edge semiconductor innovations to market faster.

How do you see semiconductor technology evolving in the future, and what role will Aeluma play in that transformation?

Semiconductor technology is undergoing a fundamental shift, driven by rapid growth in AI, quantum computing, and HPC. Traditional silicon-based architectures are reaching their physical limits for higher processing speeds, lower power consumption, and greater data throughput. The future of semiconductors will be defined by advanced materials, integrated photonics, and large-scale heterogeneous integration, enabling faster, more efficient computing at scale.

Aeluma is positioned at the forefront of this transformation with a breakthrough semiconductor platform that integrates compound semiconductor materials with large-diameter silicon wafers. This approach eliminates performance bottlenecks in AI and quantum computing by providing performance at scale and at low cost. Aeluma’s large-diameter wafer capability and ISO 9001-certified operation allow us to produce high-speed, energy-efficient optical interconnect technologies that will be critical for next-generation AI accelerators, data centers, and quantum networks.

The market opportunity is massive. Global semiconductor sales are projected to reach $1 trillion as early as 2030, according to analysts at the Semicon West trade show in July 2024, including Needham & Co.’s Charles Shi and Gartner’s Gaurav Gupta, who suggests the milestone could occur closer to 2031 or 2032. Meanwhile, the silicon photonics market is expected to grow to approximately $8 billion by 2030, as reported by Grand View Research.

By bringing advanced photonics and compound semiconductors into mainstream semiconductor production, Aeluma is enabling the next era of computing, where speed, efficiency, and scalability define success. Our partnerships with government agencies and commercial customers further reinforce our leadership in shaping the future of AI-driven semiconductor technology.

Also Read:

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Metamorphic Test in AMS. Innovation in Verification

Metamorphic Test in AMS. Innovation in Verification
by Bernard Murphy on 03-26-2025 at 6:00 am
Categories: Cadence, EDA

Innovation New

We have talked about metamorphic testing before. Here is a clever application to testing an AMS subsystem. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is System Level Verification of Phase-Locked Loop using Metamorphic Relations and was published in the 2021 DATE conference. The authors are from the University of Bremen and the Johannes Kepler University in Austria. The paper has 5 citations.

A quick recap on metamorphic testing. In some cases it is difficult or impossible to construct a meaningful oracle against which test runs can be compared to find problems. Instead metamorphic testing compares simulation behavior between two or more different tests for which certain properties in simulation results are expected to remain the same (or close to the same). Let’s call these properties “invariants”. This method is especially interesting for AMS testing where oracles inside a circuit are hard to define.

The authors use this approach to test a production PLL – part analog and part digital – by defining invariants that should hold given the structure of that function. Through this testing they were able to find an uncommon but real case in which a production PLL can lock to the wrong frequency.

Paul’s view

Fun paper this month – metamorphic testing of analog circuits. Metamorphic Testing (MT) is testing that doesn’t need a golden reference model for the design being tested. It relies instead on validating that certain relationships hold true between two different executions of a design. A common example given is for testing design that implements the sin(x) function. One “metamorphic relation” (MR) for this function is that sin(x) = sin(180-x) for any value of x. So we can write a test that just runs the design with different values of x and 180-x and check the result is always the same. Simple concept with a lot of published works showing how powerful it can be to catch corner case bugs. Threadmill, which we blogged on last month, can be considered an MT system, since it runs multi-threaded programs many times and checked the behaviors are identical to try and catch concurrency related bugs.

This paper applies MT to a commercial PLL and finds a corner case bug where a small change in the PLL input clock frequency from 1MHz to 1.01MHz causes the phase locking feedback loop in the PLL to breakdown. The paper’s main contribution is a number of clever MRs for PLLs, one of which catches this real silicon bug. This MR states that if the input clock frequency is multiplied by some factor C, then the feedback loop clock frequency inside the PLL must also be multiplied by the same factor C. Another MR states that the locking time should be the same irrespective of the input clock frequency.

Short paper, easy read. A good motivator for us all to look at our DV suites and see if we missed writing assertions/properties that check if certain relationships hold across multiple tests, not only within a single test.

Raúl’s view

“Metamorphic” testing focuses on how a system transforms inputs rather than static input-output pairs. For example, to test a program implementing sin(x), one can use sin(x)=sin(180-x) as a “metamorphic relation”. Instead of checking the expected output for a concrete input, run the program for an input x1 and afterwards for the input x2=180-x1 and check that the program gives the same output in both cases, otherwise there is a bug. Metamorphic testing has been used for software; a major advantage of this technique is that no reference model/value is needed.

This month’s paper discusses the application of metamorphic testing to Analog/Mixed-Signal (AMS) systems, specifically focusing on the verification of Phase-Locked Loops (PLLs). The authors from the University of Bremen and Johannes Kepler University identify 8 metamorphic relations for PLLs, for example: The PLL stays in the locked state if the input frequency is varied inside the lock range, and the Lock Detector signal stays on. They applied these to an industrial PLL (from an industrial partner not named explicitly) coded in SystemC and simulated with COSIDE, and discovered a previously undetected rare but real case where the PLL could lock to the wrong frequency. The bug was related to a dead-zone effect in the Phase Frequency Detector (PFD), which was resolved by adding a delay element.

The paper is succinct and self-contained and is a pleasure to read. It gives a nice introduction to PLLs and metamorphic testing of AMS systems and shows the potential of metamorphic testing for AMS verification and its ability to uncover hard to find bugs.

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Webinar: RF board design flow examples for co-simulating active circuits

Webinar: RF board design flow examples for co-simulating active circuits
by Don Dingee on 03-25-2025 at 10:00 am
Categories: EDA, Events, Keysight EDA

Mesh domain optimization

In part one of this webinar series, Keysight and Modelithics looked at the use of 3D passive vendor component models supporting highly accurate, automated 3D EM-circuit co-simulation of high-frequency RF board designs. Part two continues the exploration of RF board design flows for simulating active circuits on boards, again with accurate, parameterized Modelithics models with the appropriate versions driving simulations in Keysight EDA Advanced Design System (ADS), RFPro, and Genesys.

Watch the replay now: Accelerate Your Design Flows with Highly Accurate Simulation Models

Design efficiency depends on using purchasable part values in accurate simulations

In this webinar, Keysight features the use of Modelithics model libraries of vendor parts with RFPro in ADS to perform accurate EM-circuit co-simulation of RF boards, and Genesys RF circuit synthesis to automatically pick the optimal discrete purchasable vendor part values to meet performance requirements of circuits built on RF boards.

If you have ever simulated and optimized even a relatively simple circuit on an RF board design, you may have noticed that optimized component values are not available from any vendor. Designers must look up vendor parts catalogs to identify real-life purchasable components, substitute those in a circuit, re-simulate, and either live with the slightly changed results or redesign using different part values. It is a very inefficient workflow.

Genesys’ unique Vendor Parts Synthesis (VPS) utilizes the Modelithics COMPLETE Library for RF circuit synthesis. VPS starts with gradient optimization to obtain the optimal theoretical part values to meet specs, then switches to discrete grid search for the nearest purchasable real-life vendor part values and further optimizes for the best combination of upper or lower nearest discrete values to produce the best realizable results. Designers have accurate simulation results and a purchasable bill of materials ready when simulations complete, saving a tremendous amount of manual schematic adjustments.

Keysight ADS users can also employ gradient, followed by discrete optimization to obtain real-life-ready results with the Modelithics COMPLETE Library for Advanced Design System (ADS). Chris DeMartino, Applications Engineer at Modelithics, conveys a simple nonlinear component example – a model for and simulation of an Infineon BAS70 nonlinear Schottky diode in a 2.45 GHz detector circuit. Their measurement-based model of the diode delivers highly accurate simulations, as shown by the match in DC output voltage between simulated (red trace) and measured (blue Xs) results.

DeMartino provides detailed examples with Skyworks diodes and Mini-Circuits LNAs in his discussion on making EM-circuit co-simulation as easy as circuit analysis with ADS and RFPro.

Exploring what is possible with models for nonlinear components

Martin Trossing, Customer Success Manager for EDA at Keysight, builds on an example in ADS used in part one to illustrate 3D component spacing, but in this session emphasizes nonlinear behavior. His demonstration creates accurate simulations of amplifiers (LNA and PA) with EM-circuit co-simulation of the physical layout and Modelithics nonlinear component models.

Comprehensive evaluation of linear and nonlinear stability of amplifiers is easy with the Winslow stability analysis in ADS. One Winslow stability analysis with one schematic (no manual probe setups) replaces 14 separate traditional stability analyses, producing all results simultaneously.

After amplifier instabilities are detected, EM-circuit co-simulation and visualization can troubleshoot the physical locations and frequencies where undesired feedback occurs. This workflow enables amplifier designers to fix issues and eliminate multiple hardware re-spins.

Stepping through component models and RF board simulation

ADS RFPro mesh domain optimization (MDO) makes EM-circuit co-simulation of any chosen RF paths comprising layout traces and circuit models easy. It eliminates tedious traditional “cookie-cutting” of the layout for localized EM simulation, followed by manual connection of EM S-parameter ports to circuit nodes for EM-circuit analysis.

The Modelithics COMPLETE Library family contains over 28,000 passive and active components, accelerating EM-circuit co-simulations in Keysight EDA platforms and smoothly connecting designs to real-world component availability. More details and discussion follow in the RF board design flow webinar, and registration is open now:

Watch the replay now: Accelerate Your Design Flows with Highly Accurate Simulation Models

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Ceva-XC21 and Ceva-XC23 DSPs: Advancing Wireless and Edge AI Processing

Ceva-XC21 and Ceva-XC23 DSPs: Advancing Wireless and Edge AI Processing
by Kalar Rajendiran on 03-25-2025 at 6:00 am
Categories: 5G, AI, Ceva, IP

Cellular Evolution

Ceva recently unveiled its XC21 and XC23 DSP cores, designed to revolutionize wireless communications and edge AI processing. These new offerings build upon the Ceva-XC20 architecture, delivering unmatched efficiency, scalability, and performance for 5G-Advanced, pre-6G, and smart edge applications. As demand grows for low-power, high-performance DSPs, Ceva’s latest innovations provide future-proof solutions tailored for a broad spectrum of industries.

Architectural Highlights

Both the Ceva-XC21 and Ceva-XC23 leverage the Ceva-XC20 architecture, providing a scalable, multi-threaded processing framework optimized for cost, power, and performance. The Ceva-XC21 offers best-in-class performance per area, ensuring multi-protocol support and LTE/5G compatibility, while the Ceva-XC23 delivers higher processing power to meet the demands of next-generation cellular and satellite communications. Additionally, the software compatibility across all Ceva-XC20 DSPs and legacy XC4500 ensures seamless migration and future scalability.

Highlights of Ceva-XC21 and Ceva-XC23 DSPs

The Ceva-XC21 DSP family introduces three advanced vector DSPs: the XC210, XC211, and XC212, each offering significant improvements in area efficiency, power consumption, and performance. These DSPs are optimized for cost-sensitive and size-constrained applications, such as IoT UE (eRedCap, RedCap, CAT M, CAT1, CAT4) and 5G Non-Terrestrial Networks (NTN) terminals. The Ceva-XC212, in particular, delivers up to a 180% performance of XC4500 with a 12% area reduction, making it a high-efficiency solution for 5G-Advanced processing.

On the other hand, the Ceva-XC23 DSP is tailored for high-end applications, including infrastructure (RAN), High Power User Equipment (HPUE), Fixed Wireless Access (FWA) and satellite communications (SATCOM). It boasts a 2.4X performance improvement, AI support, high-precision acceleration, and achieves speeds of up to 1.8GHz on TSMC’s 5nm process. With its ability to handle complex communication workloads, the XC23 has already been licensed by two Tier-1 OEMs for 5G-Advanced and pre-6G deployments.

Future-Proofing

Ceva’s XC21 and XC23 leverage the Software-Defined Radio (SDR) capabilities of the XC20 architecture, allowing seamless adaptation to evolving wireless standards via software updates. Their modular and configurable nature enables customers to tailor DSP performance, ensuring longevity and scalability in an era of rapidly advancing technology. The enhanced AI capabilities also support next-generation AI-driven signal processing and edge computing, making them highly adaptable for future innovations.

Built-In AI and ML Acceleration

The integration of AI and machine learning (ML) capabilities is another standout feature of the XC23 and XC21 processors. They come with AI capabilities for modem and communications. Tasks such as channel estimation and noise filtering are traditional handled by DSP algorithms but can be supported more efficiently with the AI capabilities that come with the XC23 and XC21 processors.

Infrastructure Market Trends

The global RAN market remains strong, generating about USD 35-40 billion annually. The deployment of 5G-Advanced is accelerating, enabling enhanced connectivity and expanded network capabilities. The growth of private and industrial networks is further driving demand for customized private 5G solutions. Meanwhile, research and development for 6G technology is progressing, with commercial deployment expected by 2030. The rising network data traffic, projected to triple by 2030, necessitates advanced spectrum efficiency and infrastructure enhancements. Additionally, spectrum expansion efforts are exploring 7 GHz to 24 GHz frequency bands to accommodate future connectivity needs. The 6G market is forecasted to reach USD 68 billion by 2035, growing at an impressive CAGR of 76.9% from 2030 to 2035.

SATCOM Market – The New Space Race

The SATCOM industry is undergoing a paradigm shift, transitioning from proprietary technologies to 3GPP-compliant 5G NTN. Ceva is at the forefront of this transformation, powering Satellite 5G Base Stations that enable global coverage for consumer and industrial applications. Additionally, Ceva supports OEMs and satellite operators in user terminals, ground gateways, and satellite communication payloads. These solutions are critical as satellite communications become increasingly integrated with terrestrial 5G networks, expanding the reach of wireless connectivity.

Ceva’s Position in the Market

Ceva’s technology spans the entire cellular ecosystem, supporting applications in infrastructure, smartphones, and IoT. The company’s 5G RAN architectures extend across base stations, disaggregated DU/RU, Active Antenna Units (AAU), small cells, vRAN, Open-RAN, backhaul, and fronthaul solutions. Ceva also plays a critical role in the 5G smartphone industry, providing optimized DSP platforms and baseband modem solutions. Furthermore, in cellular IoT, Ceva delivers cutting-edge DSPs for RedCap, eRedCap, Cellular V2X, Industrial IoT, Fixed Wireless Access (FWA), and 5G Satellite connectivity.

Summary

With the Ceva-XC21 and Ceva-XC23 DSP families, Ceva continues to push the boundaries of performance, efficiency, and AI-driven processing in next-generation wireless communication and smart edge applications. By building on the scalable and future-proof Ceva-XC20 architecture, these offerings provide best-in-class solutions for 5G-Advanced, pre-6G, cellular IoT, and SATCOM. As the industry moves toward 6G, Ceva seems well-positioned to drive innovation in connectivity, AI acceleration, and advanced network infrastructure.

To learn more, visit the respective product pages below.

Ceva-XC21 page

Ceva-XC23 page

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CEO Interview with Brad Booth of NLM Photonics

CEO Interview with Brad Booth of NLM Photonics
by Daniel Nenni on 03-24-2025 at 10:00 am
Categories: CEO Interviews

Brad Booth

Brad Booth, CEO of NLM Photonics, is a distinguished technology strategy and development leader, and influential in industry consortia and standardization. Prior to NLM, Booth served at Meta Platforms and Microsoft Azure, where he focused on developing next-generation optical connectivity solutions for Cloud and AI data centers. Previously, he worked at Dell, Intel, and Bell-Northern Research. Booth led the formation of the Ultra Ethernet Consortium, the Ethernet Technology Consortium, the Consortium for On-Board Optics, and the Ethernet Alliance. He is well-known in the networking industry and has received awards for his contributions to the industry and networking standards.

Tell us about your company?

NLM Photonics is working to change the trajectory of the photonics industry using groundbreaking hybrid organic electro-optic (OEO) materials. The photonics industry does not have an analogue to Moore’s Law in the electronics industry: For us, as bandwidth increases, so does power consumption. NLM focuses on shifting the power curve down by up to 50%.

What problems are you solving?

One of the most critical problems today is the power demand associated with AI data centers. Network power demands for AI data centers can be more than double that of traditional data centers. Photonics account for 70 percent of network power consumption; almost a third of an AI data center’s total power. NLM’s target is to cut photonics power consumption by up to 50 percent, which will have a significant impact on data center power efficiency.

What application areas are your strongest?

Energy efficient modulation. Power consumption and frequency of modulation are directly impacted by the losses inherent in the modulator. Use an inefficient or high-loss modulator, and you have to correct that by burning more power. NLM’s energy-efficient modulation has gained traction in the photonics industry for datacom, telecom, and quantum applications, plus in the mmWave industry.

What keeps your customers up at night?

Customers across this industry are concerned about how to stay competitive on bandwidth capabilities while fitting within their power limitations. Whether they’re considering pluggable optics, co-packaged optics, or optical I/O, the challenges are complex. OEO materials, like NLM’s Selerion-HTX, can provide a path to address those limitations by offering increased bandwidth for significantly less power than competing technologies.

What does the competitive landscape look like and how do you differentiate?

Many incumbent technologies in the photonics industry are now being challenged by both inorganic and organic technologies. What I like about NLM’s technology is that we’re agnostic to the photonics platform, and there’s no disruption to the wafer development. And more importantly, NLM’s technology is designed for high thermal stability to make it suitable for high-volume manufacturing.

What new features/technology are you working on?

NLM Photonics continues to develop new materials, processes, and devices to tune performance, improve modulation efficiency, and accelerate the manufacturing process. Our forthcoming additions to the Selerion family of OEO materials will further redefine the boundaries of photonics performance. We look forward to sharing more on those developments in the near future.

How do customers normally engage with your company?

NLM’s customers engage with us directly today. We foresee that model will continue as we work to develop an ecosystem. Over time, our goal is to have our technology be ubiquitous throughout the semiconductor industry, enabling those in the industry to easily access NLM’s technologies for their developments and devices. If you’re a fabricator interested in partnering with us, connect with me on LinkedIn; I’d love to talk with you about the future of photonics.

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Going Beyond DRC Clean with Calibre DE

Going Beyond DRC Clean with Calibre DE
by Mike Gianfagna on 03-24-2025 at 6:00 am
Categories: EDA, Siemens EDA

Going Beyond DRC Clean with Calibre DE

For advanced semiconductor designs, achieving both design rule check clean layouts and optimal electrical performance is crucial for minimizing design iterations, reducing time-to-market and ensuring product reliability. Balancing electrical performance and layout integrity is a difficult task. Achieving an optimal and balanced solution demands deep technical understanding of all the nuances and impact of each set of requirements. There are often unexpected interactions at play. Achieving a result that satisfies all requirements can result in an overly pessimistic design. Pushing the envelope in the other direction can result in a non-functional design.

Siemens Digital Industries Software recently published a comprehensive technical paper on these challenges. It turns out Calibre DesignEnhancer (DE) possesses the required deep understanding of the technology requirements and interactions at play. The product delivers an analysis-based, signoff-quality layout modifying EMIR solution that enhances power integrity and reduces IR drop. This results in improved design reliability and manufacturability across multiple foundry technologies, reduced support costs and increased usability for foundries, CAD teams, and designers. The technical paper gets into substantial detail on how Calibre DE accomplishes this. There are also detailed use cases from Google and Intel. A download link is coming but first let’s explore going beyond DRC clean with Calibre DE.

About the Technical Paper

I find it interesting that Google and Intel are cited side-by-side in this piece. It wasn’t that long ago that Intel would never disclose anything about its design capability and Google would really have nothing to say about chip design. It seems that semiconductor companies are becoming system companies and system companies are becoming semiconductor companies. And so, we move forward.

Jeff Wilson

The technical paper is entitled How Google and Intel use Calibre DesignEnhancer to reduce IR drop and improve reliability. The author is Jeff Wilson. Jeff is a product management director for DFM applications in the Calibre organization at Siemens Digital Industries Software. He is responsible for the development of products that analyze and modify the layout to improve the robustness and quality of the design. Before joining Siemens, Jeff worked at Motorola and SCS. He holds a B.Sc. in design engineering from Brigham Young University and an MBA from the University of Oregon.

About Calibre DE

Foundries face many challenges with each new technology, like the need for new analysis and qualified DRC/LVS decks. Calibre DE addresses this challenge by reading the relevant data from DRC rules file, then using its built-in expertise with SVRF commands to create a deck that modifies the layout to solve identified EMIR problems. These files create a design kit that includes specific DRC values from the foundry/IDM.

At the core of all this is Calibre’s deep understanding of design rules. One example use case is adding DCAP and filler cells after P&R has completed power, performance and area iterations. This can be tricky since P&R tools are not good at filling open spaces with very specific design rules. If you run PV on a medium to large design with DCAP and filler cells inserted by a P&R tool, runtime can exceed 10 hours. Calibre DE Pvr (physical verification ready) flow uses the world’s best correct-by-construction fill tool, SmartFill, to place DCAP and filler cells. The runtime for this approach will take ~1 hour, delivering much better results.

Another example is the challenge of ensuring that designs are free from electrical violations like IR drop. This is getting more important at advanced nodes. Calibre DE Pge (power grid enhancement) and Calibre DE Via (via insertion) are tools that optimize the power delivery network and reduce the impact of IR drop, improving electromigration/IR drop and overall yield. By using these tools, design teams can minimize the risks of power failure and other integrity issues that affect product performance.

The technical paper gets into lots of details about these capabilities and more. You can also access a lot of detailed information on Calibre DesignEnhancer here. Let’s now take a brief look at what Google and Intel found. This information was taken from recent conference presentations from both companies.

Google’s Experience

Google’s goal was to reduce IR drop at 3 nm. The Google team found that finding IR drop issues at the chip finishing stage was particularly challenging and that conventional solutions came with unfortunate consequences:

  • Derating means decreased speed.
  • Changing floorplan or re-designing the power distribution network (PDN) means additional design cycles.
  • Fixing the PDN becomes very complicated and ineffective due to the huge increase in DRC rules, especially if attempted manually or using conventional tools.
Google flow incorporating Calibre DesignEnhancer during the chip finishing stage

Google used Calibre DE via insertion to improve IR drop with little or no timing impact, and Calibre DE power grid enhancement to improve the power grid by creating parallel run lengths. They used the EMIR results to focus layout modifications on design areas where the power grid needed to be enhanced. They also used built-in functionality to limit edits around critical nets and establish priorities for the power signals.

There is a lot more detail on what Google found in the technical paper. You will definitely want to review this data. The figure on the right shows what Google’s flow looks like.

Intel’s Experience

Intel’s goal was to improve power grid robustness at 5nm and beyond. The Intel team had created a PDN during automated floorplanning but found corner cases that prevented some via hookups. The result was a weak power grid and inadequate power hookups that caused inaccurate electrical modeling.

The team provided several nets that needed additional via hookups for Calibre DE Via to work on to maximize the number of vias to reduce IR drop issues. The P&R team did their job based on their understanding of the design rules. They were forced to take a conservative approach to the rules. Using Calibre DE, the P&R team was able to insert an additional 9 million vias on the nets that they specified on the 5 nm process node. These additions were very targeted as shown in the figure below.

Via counts per net

By leveraging Calibre DE’s detailed understanding of via-related DRC rules—such as spacing, width and width-dependent rules—Intel was able to insert the additional vias without introducing DRC violations. This significant increase in vias had a measurable impact on IR drop, improving both electrical performance and yield. More details of Intel’s experiences are provided in the publication.

To Learn More

I have just scratched the surface of what is discussed in the new Siemens Digital Industries technical paper, How Google and Intel use Calibre DesignEnhancer to reduce IR drop and improve reliability. If balancing electrical performance and layout integrity at advanced nodes is giving you a headache, you will definitely want to read this paper. You can download your copy here.  And you can learn more about the family of Calibre DE products here.  All this will help you understand going beyond DRC clean with Calibre DE.

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Podcast EP278: Details of This Year’s Semiconductor Startups Contest with Silicon Catalyst’s Nick Kepler

Podcast EP278: Details of This Year’s Semiconductor Startups Contest with Silicon Catalyst’s Nick Kepler
by Daniel Nenni on 03-21-2025 at 10:00 am

Dan is joined by Nick Kepler, COO and Director at Silicon Catalyst. Nick has over 30 years of experience in the semiconductor industry, with varied leadership and technology management roles including semiconductor process technology development and manufacturing, design enablement, technical program management, and customer-facing marketing and technical sales.

Nick describes the details of Silicon Catalyst’s third Semiconductor Startups Contest with Dan. The contest is opening today and like prior events is co-sponsored by Arm. Nick explains the history and goals of the event, along with a description of prior winners. He describes the prizes of the current contest, which are substantial and include $150K – $250K of prize money along with admission to the Arm Flexible Access program which includes try before you buy access to Arm IP, tools training, support and simpler legal agreements.

Dan also explores the details of how and when to apply to the contest and when results will be announced with Nick. Details about the contest can be found here, and you can submit an application here.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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CEO Interview with Jonas Sundqvist of AlixLabs

CEO Interview with Jonas Sundqvist of AlixLabs
by Daniel Nenni on 03-21-2025 at 6:00 am
Categories: CEO Interviews

04 AlixLabs portrait 211116

Jonas Sundqvist received his PhD in inorganic chemistry from Uppsala University, Department for Materials Chemistry at The Ångström Laboratory in 2003 where he developed ALD and CVD processes for metal oxide ALD and CVD processes using metal iodides. Jonas is in charge of the daily business at AlixLabs – as a co-founder, he’s been with the company since day one in 2019.

Tell us about your company?
AlixLabs is the world’s only pure-play Atomic Layer Etch (ALE) equipment company, pioneering a breakthrough technique called APS (ALE Pitch Splitting). Our technology enables precise, atomic-scale feature definition in semiconductor manufacturing, helping chipmakers achieve critical dimensions below 10 nm at dense line pitch. By reducing the number of process steps in advanced patterning, we offer a more cost-effective and sustainable alternative to multi-patterning and extreme ultraviolet (EUV) lithography.

What problems are you solving?
We address the growing challenges in semiconductor manufacturing as the industry continues to scale down feature sizes. Traditional multi-patterning approaches introduce complexity, cost, and yield loss. APS streamlines the patterning process, reducing lithography steps, improving throughput, and lowering costs by up to 40% per multi patterning mask layer. Additionally, our solution minimizes energy and material consumption, supporting a more sustainable semiconductor industry.

What application areas are your strongest?
Our APS technology is particularly valuable for advanced logic (leading-edge node processors and GPUs) and DRAM memory. Our focus is on high-volume leading edge 300 mm semiconductor manufacturing, where reducing cost and improving yield are critical.

What keeps your customers up at night?
Chipmakers are constantly seeking ways to improve yield, reduce costs, and extend Moore’s Law. The increasing complexity of patterning techniques, rising lithography costs, and sustainability concerns around energy and material use are major challenges. Our APS technology directly addresses these pain points by simplifying manufacturing, lowering cost per wafer, and improving process efficiency and limiting the use of fluorinated gases with high GWP and PFAS issues.

What does the competitive landscape look like and how do you differentiate?
The advanced patterning landscape is dominated by EUV lithography and multi-patterning techniques. Competitors include optical lithography equipment provider ASML and alternatives like Canon’s and EVG’s Nano Imprint Lithography and companies offering complex self-aligned multi-patterning solutions. AlixLabs differentiates itself by providing a complementary or alternative solution that significantly reduces the reliance on costly lithography steps. APS enables manufacturers to scale down features without the added process complexity and cost burden of traditional patterning methods.

What new features/technology are you working on?
We are continuously refining our APS process for even finer feature scaling and expanding our compatibility with additional wafer sizes and materials. Our R&D team is focused on optimizing APS for future semiconductor nodes and integrating it with emerging process flows to enhance manufacturability, yield, and sustainability.

How do customers normally engage with your company?
Our customers typically engage with us through early-stage evaluations and process development collaborations. We work closely with leading semiconductor manufacturers, foundries, and research institutes to qualify and integrate APS into their production workflows. Engagements range from feasibility studies and we are developing a Beta tool (RFP 3Q2025) for early pilot design verification and pilot production to be followed by full-scale implementation for high-volume manufacturing in 2027-2029.

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