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How Memory Technology Is Powering the Next Era of Compute

How Memory Technology Is Powering the Next Era of Compute
by Kalar Rajendiran on 02-11-2026 at 10:00 am
Categories: AI, IP, Rambus

How AI is Shaping the Memory Market Title Slide

For more than a decade, progress in artificial intelligence has been framed almost entirely through the lens of compute. Faster GPUs, denser accelerators, and higher TOPS defined each new generation. But as generative and agentic AI enter their next phase, that framing is no longer sufficient. The most advanced AI systems today are not constrained by arithmetic throughput. They are constrained by memory.

That reality was the central theme of “How Memory Technology Is Powering the Next Era of Compute,” a panel session featuring Rambus participants Steven Woo, John Eble, and Nidish Kamath, moderated by Timothy Messegee. Timothy is Senior Director, Solutions Marketing; Steven is a Fellow and Distinguished Inventor; John is Vice President, Product Marketing for Memory Interface Chips; and Nidish Kamath, is Director, Product Management, Memory Controller IP.

The discussion revealed how modern AI workloads are placing unprecedented demands across the entire memory hierarchy, forcing fundamental changes in system architecture, power delivery, and reliability strategies.

When AI Models Outgrow the Memory Hierarchy

The defining characteristics of today’s AI models include exploding parameter counts, longer context windows, persistent reasoning, and simultaneous multi-user inference. All these characteristics translate directly into dramatically higher memory demands. AI systems now need to move, store, and retain far more data than previous generations of workloads, often for extended periods of time.

At the same time, scaling limits at the lowest levels of the memory hierarchy are becoming increasingly visible. SRAM no longer scales economically or densely enough to keep pace with AI’s appetite for on-chip data. As a result, pressure shifts upward into DRAM, which must now deliver both higher bandwidth and greater capacity. The traditional memory hierarchy, designed for more balanced and predictable workloads, is struggling to adapt to this imbalance.

Architecture Steps In Where Physics Pushes Back

In server environments, the constraints are especially acute. CPUs can only support a limited number of memory channels due to pin count, packaging, and system form-factor limitations. Simply adding more memory channels is not practical, yet AI workloads demand more bandwidth than ever.

This is where architectural innovations such as MRDIMM, or Multiplexed Rank DIMM, become critical. MRDIMM technology uses on-module logic to multiplex parallel memory ranks into a single CPU channel, effectively doubling usable bandwidth without requiring additional pins or channels. Rather than relying solely on faster DRAM devices, MRDIMM demonstrates how intelligent system design can extend performance beyond traditional physical limits.

Telemetry: From Debug Tool to Performance Enabler

Another important shift highlighted during the panel is the growing role of telemetry and observability. In earlier generations, memory subsystems were largely static, configured once and rarely revisited. That approach no longer works in AI systems, where workloads evolve rapidly and performance requirements shift continuously.

Modern memory controllers now provide detailed visibility into internal behavior, enabling real-time tuning and long-term optimization. This level of observability allows systems to adapt as AI models change, sustaining performance and efficiency rather than allowing them to degrade over time. In this context, telemetry is no longer just a debugging aid, it has actually become a core enabler of AI performance.

Reliability Moves to the Center of AI Infrastructure

As AI deployments scale, reliability has emerged as a defining constraint. Memory-related errors already contribute to significant system downtime in large data centers, driving costly overprovisioning to maintain service levels. For AI workloads, where training and inference cycles are both expensive and time-sensitive, an overprovisioning approach is unsustainable.

The panel emphasized that reliability, availability, and serviceability features must now be designed into memory systems from the outset. Advanced error correction, cyclic redundancy checks, retry mechanisms, and fault isolation are becoming essential for sustaining AI uptime. Performance without reliability is no longer acceptable in large-scale AI infrastructure.

Memory Technologies Begin to Converge

One of the most striking themes to emerge from the discussion is the blurring of traditional memory boundaries. Technologies once confined to specific markets are now being reevaluated through the lens of AI workloads.

GDDR7, historically associated with graphics, is increasingly attractive for edge inference. Its use of PAM3 signaling delivers exceptional bandwidth while controlling pin count, and built-in retry mechanisms improve robustness in environments where reliability matters. Meanwhile, LPDDR5X and LPDDR6, long optimized for mobile devices, now offer bandwidth comparable to DDR5 while maintaining superior power efficiency. New modular formats such as LPCAMM2 further extend LPDDR’s reach by combining proximity to the processor with serviceability.

As a result, memory selection is becoming less about market segmentation and more about workload fit.

Power Becomes the Dominant Design Constraint

As AI systems grow denser and more powerful, power delivery has become one of the most difficult challenges facing system architects. Future AI data centers are being designed around megawatt-class racks, driven by high-bandwidth memory, dense accelerators, and massive data movement.

A growing share of total system energy is now consumed not by computation, but by moving data between components. To manage this, architectures are shifting toward higher-voltage, lower-current delivery, with power management integrated directly onto memory modules through PMICs. Even fractional improvements in efficiency can translate into enormous savings at scale.

These power densities also drive changes in cooling strategies. Liquid cooling is rapidly becoming standard in AI systems, reshaping server design and data center infrastructure. Memory, once a relatively passive consideration, is now deeply intertwined with power and thermal architecture.

Chasing the “Best of Both Worlds”

Looking ahead, the panel pointed toward a future in which memory technologies blend strengths that were once considered mutually exclusive. The goal is to combine the bandwidth and power efficiency of mobile-class memory with the reliability, security, and resilience traditionally associated with server-class systems.

This direction opens the door to innovations such as processing-in-memory, inline memory encryption, and new reliability frameworks tailored specifically for AI workloads. As systems evolve toward agentic and autonomous behavior, memory will play a central role in enabling not just performance and scale, but trust, privacy, and long-term stability.

A New Mandate for Memory

The AI revolution has fundamentally changed what is expected from memory systems. Faster alone is no longer sufficient. Memory must now be closer to compute, more efficient, deeply observable, highly reliable, and inherently secure.

AI did not simply expose the limits of the old memory playbook. It is driving its rewrite.

You can watch the entire Rambus panel session here.

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Semidynamics Unveils 3nm AI Inference Silicon and Full-Stack Systems

Semidynamics Unveils 3nm AI Inference Silicon and Full-Stack Systems
by Daniel Nenni on 02-11-2026 at 8:00 am
Categories: IP, Semidynamics
2 Comments

Semidynamics Unveils TSMC N3 AI Inference Silicon

Semidynamics has taken a significant step forward in the race to build next-generation AI infrastructure with the unveiling of its 3nm AI inference silicon and a vertically integrated, full-stack systems strategy. Announced in February 2026, the development marks the company’s evolution from an advanced architecture specialist into a full-stack AI platform provider, delivering not only chips but also boards and rack-scale systems designed for demanding data center inference workloads. At a time when AI performance is increasingly constrained by memory efficiency and system integration rather than raw compute alone, Semidynamics’ approach reflects a clear shift toward system-level optimization.

Central to this announcement is the company’s successful 3nm tape-out with TSMC, achieved in December 2025. Fabricated using one of TSMC’s most advanced process technologies, this milestone validates Semidynamics’ ability to execute at the leading edge of semiconductor manufacturing. Tape-out at 3nm is not only a technical achievement but also a signal of silicon readiness, placing Semidynamics among a small group of companies capable of translating complex AI architectures into manufacturable, production-grade designs on the world’s most advanced nodes.

While the use of TSMC’s 3nm technology provides density, performance, and power-efficiency advantages, Semidynamics emphasizes that process scaling alone is not sufficient to meet the needs of modern AI inference. As AI models continue to grow in size and concurrency requirements increase, memory bandwidth and data movement have emerged as the dominant performance bottlenecks. This so-called “memory wall” limits the real-world gains achievable by compute-centric designs and drives up system cost and power consumption.

To address this challenge, Semidynamics has developed a new memory subsystem that rethinks data flow and memory access from first principles. Rather than relying heavily on scarce and expensive high-end memory components, the architecture optimizes how data is moved, reused, and accessed across the system. This enables large inference models to operate more efficiently, supports high-concurrency workloads, and reduces total cost of ownership for data center operators. The result is an architecture designed not just for peak performance, but for sustained, scalable inference in real deployment environments.

Building on this silicon foundation, Semidynamics is expanding into a full-stack AI infrastructure model. The company plans to deliver tightly integrated boards and rack-level systems based on its 3nm inference silicon, ensuring that architectural benefits at the chip level translate directly into system-level gains. This vertical integration is increasingly important in modern AI data centers, where performance, power efficiency, and scalability depend on how well accelerators, interconnects, and system software are co-designed.

By offering a complete stack (chips, boards, and racks), Semidynamics aims to reduce integration complexity for customers and provide predictable performance across multi-accelerator configurations. This approach contrasts with more fragmented models, where silicon vendors leave system optimization largely to OEMs and hyperscalers. For inference-heavy workloads that demand high throughput, low latency, and energy efficiency, such end-to-end optimization can be a decisive advantage.

Company leadership has positioned the 3nm tape-out with TSMC as a critical validation point in a broader, multi-stage roadmap. The goal is not simply to demonstrate advanced silicon, but to deliver production-ready AI inference platforms capable of operating at scale in next-generation data centers. This long-term perspective reflects Semidynamics’ architectural heritage and its focus on building durable platforms rather than one-off accelerators.

The announcement also carries strategic significance beyond technology. As a European-headquartered company designing advanced AI silicon manufactured at TSMC, Semidynamics represents a bridge between global manufacturing leadership and regional architectural innovation. This positioning aligns with broader efforts to strengthen Europe’s role in advanced computing while leveraging best-in-class foundry capabilities.

Bottom line: Unveiling its 3nm AI inference silicon and full-stack systems strategy, Semidynamics is addressing the realities of the current AI landscape. Performance gains are increasingly determined by memory efficiency and system integration, not just transistor counts. By combining an advanced 3nm implementation at TSMC with a memory-centric architecture and vertically integrated systems, Semidynamics is positioning itself as a differentiated player in AI inference infrastructure—one focused on scalable, efficient, and deployable solutions for the data centers of the future.

CONTACT SEMIDYNAMICS

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Watch Live Agentic Software Debug

Watch Live Agentic Software Debug
by Bernard Murphy on 02-11-2026 at 6:00 am
Categories: AI

agentic debug cppcon

Many moons ago in the Innovation series we explored techniques like spectrum analysis to root-cause bugs. While these methods provide some value they don’t get as close as we would like to isolating a root-cause. In hindsight given what we know about the complexity of conventional debug it is unsurprising that we can’t root-cause in one shot. Hence the rise of agentic debug solutions from companies like ChipAgents and ChipStack. Agentic systems can reason through a root cause analysis in multiple steps just as we do in human-based analysis. Following is a very intriguing parallel from our sister field (software debug) posted as a YouTube session from the C++ conference.

(Image courtesy of Cppcon)

Background and bugs

This event was a joint presentation between UnDo.io (who provide time-travel debugging for C++ and Java, think something like gdb with full context replay) and Anthropic. Their goal was to explore live (not a canned demo) what agentic debugging would look like. Gutsy move because the reality was messy though still very informative. They test on a couple of cases in parallel: A segfault in the Python interpreter and unexpected behaviors (which prove not to be bugs) in Doom.

The Python bug should attract the interest of hardware designers: effectively a cache coherency issue in software. The code caches pointers to objects allocated in memory and entries in the cache can be tested without incrementing reference counts for those objects. The coherency risk is that a referenced object may be freed without clearing the cache reference, a worthy test for the value of agentic debugging. The Doom exploration is primarily interesting for how it influences the debugging process in localizing a behavior within a playback to get close to whatever triggered that behavior. This case may be even more interesting for hardware debug, where unexpected behavior is much more likely than anything comparable to a crash.

My takeaways from the demo

The Python debug demo is, as far as I can tell, hands-free apart from the initial setup. Analysis starts with the crash and iterates backwards and between multiple types of agents, trying different hypotheses, testing with different techniques to eliminate possibilities. UnDo added an adversarial “bug diagnosis validator” agent (Claude Code) provides support for this). As agentic analysis progresses, discoveries start to converge towards the right area ultimately getting get pretty darn close to the root cause.

As expected, Claude builds a ToDo list of tasks it believes it needs to perform to work towards a goal (e.g. find when the second zombie was killed in the Doom debug, see below), and checks these off as it progresses. An interesting revelation is that it apparently can lose the plot periodically, at which point it needs to be reminded to revisit the list. This didn’t seem to happen in this Python case.

The Doom analysis is more collaborative, I imagine because they don’t have a bug to target. Instead, they are trying to understand unexpected”behaviors. For example, why did the player get stuck in the map room after killing the second Zombie? Here the demo guy asked, “when was the second zombie killed during this playthrough (recorded playback)?” Claude got him to this point, from which he could ask it to drill down further. Note the value of being able to use a high level reference (second zombie) in prompting next steps.

The demo often ran into system problems (“repeated server overload with “Opus model” – Opus is Claude’s model optimized for coding) which seem to reflect server busy problems on the Claude side. These issues are now apparently fixed (or at least improved) – this demo was running with a pre-release of the Claude Code API.

There was question from the audience about token costs. The UnDo speaker suggested single-digit dollars for the Doom example (56k LOC), much higher costs  ($$ numbers not cited) to track down the Python interpreter bug mentioned earlier (350k C LOC, 800k Python LOC).

Long video (about an hour) but well worth watching all the way through for the insights it provides. You can find the video HERE.

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Accellera Strengthens Industry Collaboration and Standards Leadership at DVCon U.S. 2026

Accellera Strengthens Industry Collaboration and Standards Leadership at DVCon U.S. 2026
by Daniel Nenni on 02-10-2026 at 10:00 am
Categories: Accellera, Events, Semiconductor Services

DVCON 2026

At DVCon U.S. 2026, Accellera Systems Initiative reinforces its central role in shaping the future of electronic design and verification through a focused program of workshops, tutorials, and community engagement. As system complexity continues to rise across AI, automotive, HPC, and communications markets, the need for robust, interoperable standards has become more urgent. Accellera’s presence at DVCon highlights how standards development is evolving to address verification scalability, system-level modeling, and IP reuse in increasingly heterogeneous designs.

We have been working with Accellera since the early days of SemiWiki when our membership was in the thousands. Now our members are in the hundreds of thousands and it really has been a pleasure working with them.

A central theme of Accellera’s program is raising the level of abstraction in design and verification. The workshop on Portable Stimulus Standard (PSS) exemplifies this shift. As SoC verification expands beyond simulation into emulation, FPGA prototyping, and post-silicon validation, traditional testbench-centric approaches struggle to scale. PSS addresses this by allowing engineers to model verification intent at the scenario level, enabling automated generation of tests that can be reused across platforms. By focusing on practical adoption patterns, Accellera positions PSS not as a theoretical construct, but as a pragmatic solution for revitalizing legacy flows and improving coverage in real-world environments

Accellera-Sponsored Events:

Monday, March 2:
Portable Stimulus Modeling Patterns (Practical Tips for Adopting PSS)
9:00-10:30am, Grand Ballroom D

SystemC – What’s New? What’s Next?
11:00am-12:30pm, Grand Ballroom D

Thursday, March 5:
Breakthrough in CDC-RDC Verification Defining a Standard for Interoperable Abstract Model
9:00am-12:30pm, Grand Ballroom D:

IP-XACT Demystified: An In-Depth Training on the IEEE 1685-2022 IP-XACT Standard
1:30-3:00pm, Grand Ballroom D

Another major pillar of Accellera’s DVCon engagement is the continued evolution of SystemC, long regarded as foundational for system-level modeling and virtual platforms. While SystemC has matured significantly, new architectural demands such as chiplet-based designs, software-defined hardware, and large-scale virtual prototyping require renewed attention to interoperability and tooling. The session outlining updates from IEEE 1666-2023, along with progress on the SystemC CCI reflects Accellera’s recognition that standards must evolve in lockstep with industry practice. Lessons drawn from widely adopted open-source frameworks such as QEMU further underscore the importance of learning from production-proven ecosystems rather than relying solely on academic or vendor-specific approaches

Verification correctness and predictability across complex clocking environments is another area where Accellera is driving standardization. The CDC-RDC tutorial introduces efforts by the Clock Domain Crossing Working Group to define a standardized abstract model using IP-XACT and TCL. CDC and RDC issues remain among the most subtle and costly classes of silicon bugs, particularly in large SoCs integrating third-party IP. By working toward a portable, interoperable CDC-RDC model, Accellera aims to reduce tool fragmentation and enable consistent verification flows across vendors, a long-standing industry challenge

The focus on IP-XACT (IEEE 1685-2022) further emphasizes Accellera’s commitment to automation and reuse. As SoC integration teams grapple with exploding register maps, memory hierarchies, and software dependencies, spreadsheet-based approaches have become untenable. The updated IP-XACT standard provides a vendor-neutral framework for capturing IP metadata in a structured, machine-readable form. Accellera’s in-depth training session reflects growing recognition that design, verification, and software teams must operate from a single source of truth to avoid costly integration errors and delays

Beyond the technical content, Accellera’s DVCon activities highlight the importance of community-driven standards development. The Birds-of-a-Feather discussion following the SystemC session and the evening reception are not peripheral events; they are integral to how consensus is built and future directions are shaped. In an era where proprietary solutions can fragment ecosystems, Accellera’s neutral, not-for-profit model remains a critical mechanism for aligning semiconductor companies, IP providers, and EDA vendors around shared technical foundations.

Overall, Accellera’s presence at DVCon U.S. 2026 reflects a broader industry transition. As scaling challenges shift from pure transistor density to system integration, verification productivity, and software alignment, standards are no longer optional—they are strategic infrastructure. Through its workshops, tutorials, and collaborative forums, Accellera continues to position itself as a catalyst for that infrastructure, ensuring the electronics industry can move forward with greater confidence, interoperability, and efficiency.

For a complete program schedule, including exhibition hours, visit the DVCon U.S. 2026 website.

Registration is open. Registration for the keynotes, panel, and exhibits is free.

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Ceva Wi-Fi 6 and Bluetooth IPs Power Renesas’ First Combo MCUs for IoT and Connected Home

Ceva Wi-Fi 6 and Bluetooth IPs Power Renesas’ First Combo MCUs for IoT and Connected Home
by Daniel Nenni on 02-10-2026 at 8:00 am
Categories: Ceva, IP

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The rapid expansion of IoT, smart home, and industrial automation markets is reshaping how connectivity is designed into embedded systems. Developers increasingly require highly integrated wireless solutions that deliver strong performance, ultra-low power consumption, and design flexibility, while also shortening development cycles and reducing system cost. Addressing these needs, Ceva, Inc. (NASDAQ: CEVA), the leading licensor of silicon and software IP for the Smart Edge, announced that Renesas Electronics Corporation has integrated Ceva-Waves™ Wi-Fi 6 and Bluetooth® Low Energy (LE) IPs into its newly launched RA6W1 and RA6W2 microcontrollers (MCUs), marking Renesas’ first combo wireless MCU offerings.

Renesas’ RA6W1 and RA6W2 MCUs are designed to support a broad range of connected applications, including smart home devices, industrial IoT, consumer electronics, and building automation. The RA6W1 integrates dual-band Wi-Fi 6, while the RA6W2 combines Wi-Fi 6 and Bluetooth LE into a single MCU platform. By leveraging Ceva-Waves connectivity IPs, Renesas enables developers to choose between standalone Wi-Fi designs, Wi-Fi/Bluetooth LE combo solutions, or fully integrated wireless modules, depending on performance, cost, and power requirements.

This flexibility is increasingly critical as IoT devices diversify across use cases, from battery-powered sensors and smart appliances to industrial controllers and gateways. The Ceva-powered RA6W1 and RA6W2 solutions simplify system architecture by reducing the need for external connectivity components, lowering bill-of-materials costs, and streamlining RF and software integration. At the same time, they offer both hosted and hostless implementation options, allowing customers to tailor system partitioning and optimize overall efficiency.

Power efficiency remains a key differentiator in IoT and connected home markets, where battery life and thermal constraints directly impact product usability and lifetime. Ceva-Waves Wi-Fi 6 and Bluetooth LE IPs are optimized for low-power operation without compromising throughput, reliability, or interoperability. Wi-Fi 6 brings benefits such as improved spectral efficiency, reduced latency, and better performance in dense environments, while Bluetooth LE provides energy-efficient short-range connectivity for device provisioning, control, and data exchange. Together, these technologies enable always-connected devices that operate reliably within strict power budgets

“Connected devices are advancing at an unprecedented pace, opening new opportunities in IoT and industrial applications,” said Chandana Pairla, Vice President of Connectivity at Renesas. “By incorporating Ceva’s Wi-Fi and Bluetooth LE IPs into our MCUs, we are delivering system-level connectivity that combines high performance with exceptional energy efficiency. This integration helps customers reduce design complexity, extend battery life, and accelerate time to market in smart home and industrial automation applications.”

From Ceva’s perspective, the collaboration highlights the growing role of licensable connectivity IP in enabling scalable, standards-compliant wireless solutions across a wide range of MCU and SoC designs. “Our unique connectivity IP portfolio delivers the performance and efficiency needed to bring next-generation wireless features into MCUs,” said Tal Shalev, Vice President and General Manager of the Wireless IoT Business Unit at Ceva.

“This collaboration with Renesas reinforces our role as a trusted partner, enabling faster IoT innovation and empowering developers to expand what’s possible at the smart edge.”

Ceva-Waves is a comprehensive portfolio of wireless connectivity IPs supporting Wi-Fi 6 and Wi-Fi 7, Bluetooth LE and Dual Mode, IEEE 802.15.4, Ultra-Wideband (UWB), and turnkey multiprotocol platforms that also support Thread, Zigbee, and Matter. With proven hardware implementations and complete software stacks, Ceva-Waves enables faster integration, reduced risk, and shorter time to market for MCU and SoC developers targeting next-generation IoT and connected home devices.

Bottom line: By combining Renesas’ robust MCU platforms with Ceva’s industry-proven connectivity IPs, the RA6W1 and RA6W2 MCUs set a new benchmark for flexible, power-efficient wireless integration helping developers meet the evolving demands of the connected world while accelerating innovation at the smart edge.

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Why PDF Solutions Is Positioning Itself at the Center of the Semiconductor Ecosystem

Why PDF Solutions Is Positioning Itself at the Center of the Semiconductor Ecosystem
by Kalar Rajendiran on 02-10-2026 at 6:00 am
Categories: AI, EDA, PDF Solutions

PDF Solutions Thank You

The semiconductor industry is on track to exceed one trillion dollars in annual revenue by the end of the decade, propelled by AI, advanced computing, and edge applications. Yet beneath this growth lies a structural shift. Manufacturing complexity is rising faster than the industry’s ability to manage it. As architectures move deeper into 3D, production disperses globally, and product cycles compress, scale alone is no longer a differentiator. Operational coherence is.

In this environment, competitive advantage increasingly depends on how effectively organizations can learn, decide, and act across organizational boundaries. PDF Solutions’ 2026 priorities reflect a clear recognition of this shift: the company is evolving from a best-in-class analytics provider into a coordination and orchestration platform positioned at the center of the semiconductor ecosystem.

The following analysis reflects PDF Solutions’ stated priorities, positioning, and marketing opportunities based on its most recent Analyst Day presentation.

Manufacturing Analytics as Infrastructure, Not Just Tools

For decades, manufacturing analytics functioned as an overlay. Though powerful, it was disconnected from direct execution. PDF is reframing analytics as infrastructure: a shared data backbone that spans characterization, process development, high-volume manufacturing, test, and assembly. This distinction is critical as data volumes explode and process interactions become increasingly nonlinear.

By standardizing how data is ingested, contextualized, and analyzed across domains, PDF’s Exensio platform reduces reliance on custom integrations and tribal knowledge. The result is not simply better visibility, but a common analytical language that enables faster root-cause analysis, more consistent decision-making, and shared accountability across teams and partners. Additionally, it is clear that valuable, trusted, production-ready applications of AI in an industrial context need to be anchored on that type of robust, scalable, and secure data platform. PDF Solutions aims to be the platform enabling the scaling of AI across the semiconductor ecosystem.

Why Analytics Alone Is No Longer Enough

Insight without execution has diminishing value in a distributed manufacturing environment. Analytics can explain what happened and why, but as fabs scale and supply chains fragment, decision latency becomes as costly as yield loss. The next bottleneck is no longer diagnosis but orchestrated execution.

PDF’s strategy reflects this reality. Rather than stopping at insight, the platform embeds analytics directly into manufacturing workflows, ensuring that conclusions translate into aligned action across fabs, test operations, and external partners. This shift moves analytics from advisory to operationally critical.

From Insight to Orchestration

Orchestration is where PDF’s positioning becomes distinctly strategic. Orchestration answers not just “what should happen next,” but also ensures that it actually does. By connecting data, decisions, and actions, PDF enables coordinated responses to yield excursions, prioritizes engineering resources, and synchronizes operations across organizational boundaries.

This evolution is visible in Exensio’s role as an operating layer rather than a standalone analysis environment. It is further reinforced by secureWISE, which extends orchestration beyond the enterprise, enabling standardized, governed data exchange across the broader semiconductor ecosystem. Together, these capabilities position PDF not as another analytics vendor, but as the system that aligns learning and execution at scale.

Orchestration as a Strategic Risk Reducer

As semiconductor manufacturing becomes more globally distributed, coordination failures carry outsized consequences, from delayed ramps to systemic yield losses. Orchestration directly addresses this growing strategic risk. Standardized data exchange and shared workflows enable faster diagnosis, tighter alignment, and more resilient operations across regions and partners.

This elevates platforms like PDF’s from operational tools to strategic assets. The ability to coordinate learning and execution across a fragmented ecosystem becomes as important to resilience as it is to performance.

Secure Data Exchange in a Distributed Ecosystem

Modern semiconductor manufacturing is inherently cross-enterprise. Foundries, OSATs, equipment suppliers, and customers must collaborate without compromising security or IP. PDF’s secureWISE initiative reframes this challenge as a network and standardization problem rather than a series of custom integrations.

By enabling secure, governed data exchange across organizations, secureWISE supports functional consolidation without ownership consolidation. Participants remain independent, but coordinate through shared data models and workflows. As supply chains become more dynamic and geopolitical risk increases, this capability shifts from a differentiator to a requirement.

AI in Manufacturing: Discipline Over Hype

AI is a core pillar of PDF’s platform strategy, but its positioning is deliberately pragmatic. Manufacturing AI operates under constraints that differ sharply from consumer or enterprise applications: low tolerance for error, high accountability, and the need for explainability.

PDF embeds AI within governed analytics environments where models augment engineering judgment rather than replace it. The focus is on productivity, yield improvement, and cycle-time reduction rather than experimentation for its own sake. AI becomes an operational lever, not a speculative bet.

Platform Economics and Financial Leverage

PDF’s technical strategy is reinforced by a clear economic model. The company continues to expand recurring and usage-based revenue streams through subscriptions, cloud deployment, and volume-linked offerings such as secureWISE, Cimetrix, and gainshare. Analytics revenue is growing faster than total revenue, margins are expanding, and backlog growth outpaces the top line, all clear signals of increasing platform maturity.

Importantly, these offerings are becoming embedded deeper into customer operations, positioning PDF’s platform as production infrastructure rather than discretionary IT. This alignment between customer success and revenue growth strengthens financial leverage and durability.

Platform Economics and the Valuation Question: Why This Moment Matters

Despite this evolution, market perception has lagged execution. PDF is still often viewed as a niche analytics specialist rather than a system-level orchestrator. Closing this perception gap represents one of the company’s largest marketing opportunities. The company is working hard trying to change that perception with for example the recent SEMICON WEST keynote given by John Kibarian, PDF Solutions’ CEO emphasizing the need and opportunity for more AI driven collaboration across the semiconductor industry.

The semiconductor industry is approaching an inflection point. Fragmentation, rising complexity, and accelerating demand cycles are colliding with higher capital intensity and tighter talent constraints. Large-scale consolidation is neither practical nor desirable. The more likely outcome is convergence around a small number of coordination platforms that allow diverse ecosystems to function as coherent systems.

PDF Solutions is positioning itself squarely in that role. As a neutral, vendor-agnostic coordination layer, it can benefit from ecosystem fragmentation rather than fight it. When more tools and partners rely on the same platform to share data and coordinate work, the platform naturally becomes more valuable and harder to walk away from. Its future value will be defined less by individual products and more by how deeply it becomes embedded in industry operations.

In an environment where coordination is the new constraint, platforms that enable shared learning and aligned execution may prove to be among the most strategically valuable assets in semiconductor manufacturing.

Learn more at www.pdf.com and here.

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Chiplets Reach an Architectural Turning Point at Chiplet Summit 2026

Chiplets Reach an Architectural Turning Point at Chiplet Summit 2026
by Daniel Nenni on 02-09-2026 at 10:00 am
Categories: eFPGA, Events, IP, Menta

Chiplet Summit 2026

The semiconductor industry’s transition toward chiplet-based architectures is entering a decisive new phase. What began as a promising alternative to SoC design is now confronting real-world demands around system integration, validation, and long-term scalability. At Chiplet Summit 2026, taking place February 17–19 in Santa Clara, California, Menta will play a prominent role in addressing these challenges, marking its third consecutive year of participation at the event.

Menta, a semiconductor IP and platform company with more than 15 years of experience in programmable and adaptable silicon architectures, has positioned itself as a key architectural voice in the evolving chiplet ecosystem. Originally known for its pioneering work in embedded FPGA (eFPGA) technology, the company has expanded its focus to system-level challenges in advanced and chiplet-based designs. Its continued presence at the Chiplet Summit reflects the industry’s broader shift from conceptual enthusiasm toward industrial validation and deployment.

At Chiplet Summit 2026, Menta returns at what it describes as a pivotal moment. As chiplets move from architectural concepts into production-oriented systems, the dominant challenges are no longer limited to packaging or interfaces. Instead, issues such as architectural coherence, validation under real operating conditions, and the ability to manage heterogeneous systems over long lifecycles are coming to the forefront. Menta will address these topics through a technical presentation, participation in a panel discussion, and on-site engagement at Booth #316.

The company’s technical presentation will focus on architectural decision-making and system-level trade-offs required to design scalable chiplet hubs. These hubs must support long-lived systems while balancing performance, power efficiency, and adaptability. Complementing this, Menta will take part in the panel discussion titled “Selecting the Right Chiplets for Your Edge Application,” which explores how constraints such as power budgets, cost sensitivity, security requirements, communication needs, and limited update cycles shape chiplet choices as intelligence increasingly shifts to the edge.

A central theme of Menta’s participation is the growing need for platforms that go beyond theoretical interoperability. As the chiplet ecosystem matures, the industry faces a critical gap: the lack of environments capable of measuring, comparing, and de-risking modular designs under real-world conditions. Without such platforms, architectural decisions remain difficult to validate before industrial deployment. Menta argues that this gap must be addressed for chiplets to fulfill their promise at scale.

This is where MOSAICS, Menta’s modular chiplet development and validation platform, takes center stage. Initiated at Chiplet Summit 2024, MOSAICS was created to overcome the limitations of monolithic SoC design by providing a universal chassis with standardized interfaces for heterogeneous chiplet systems. By 2026, the platform has reached a significant new phase. A development kit and evaluation platform are scheduled to become available by summer 2026, enabling early adopters to explore and validate modular configurations. The first platform tape-out is planned for the first quarter of 2027, marking a concrete step toward industrial deployment.

MOSAICS is designed to allow real-world measurement and validation of chiplet-based systems, accelerating development cycles and reducing non-recurring engineering costs, particularly for edge and automotive, class applications. By translating architectural vision into an executable platform, Menta aims to provide the structure needed to turn chiplet strategies into reliable, scalable products.

“As chiplets mature, the industry needs fewer promises and more structure,” said Vincent Markus, CEO of Menta, emphasizing the shift from idea-driven discussions to architecture shaping and validation. This perspective underscores Menta’s broader message at Chiplet Summit 2026: the future of chiplets will be defined not only by openness and modularity, but by the ability to prove designs in realistic conditions before they reach production.

Through its technical contributions, platform roadmap, and ongoing engagement with the ecosystem, Menta’s presence at Chiplet Summit 2026 highlights an industry at an architectural turning point, where validation, coherence, and execution are becoming just as critical as innovation itself.

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Gate-All-Around (GAA) Technology for Sustainable AI

Gate-All-Around (GAA) Technology for Sustainable AI
by Daniel Nenni on 02-09-2026 at 8:00 am
Categories: AI, Events, FinFET, Foundries

Gate All Around Technology for Sustainable AI SemiWiki
IEDM 2025 GAA FinFET Paper

The transition from FinFET to Gate-All-Around (GAA) transistor technology represents a pivotal moment in the evolution of logic devices, driven by both physical scaling limits and the rapidly growing computational demands of artificial intelligence. As semiconductor technology approaches the sub-3 nm regime, traditional FinFET architectures face fundamental challenges in electrostatic control, performance scalability, and power efficiency. GAA transistors have emerged not as an optional enhancement, but as an essential foundation for sustaining future logic architectures and enabling sustainable AI computing, absolutely.

FinFETs were introduced to overcome the shortcomings of planar MOSFETs by improving effective channel width and electrostatic integrity through a three-dimensional fin structure. However, aggressive scaling has exposed inherent limitations in this approach. As fin widths shrink, parasitic resistance increases and carrier mobility degrades due to quantum confinement and surface roughness scattering. Additionally, the three-sided gate configuration of FinFETs struggles to adequately suppress short-channel effects at advanced nodes. These issues collectively constrain further scaling, particularly when standard cell heights approach the ~140–160 nm range.

GAA transistors fundamentally address these challenges by fully surrounding the channel with gate material, delivering superior electrostatic control. This all-around gating enables steeper subthreshold slopes, reduced leakage current, and improved short-channel behavior, even at extremely small dimensions. As a result, GAA architectures re-enable cell height scaling to approximately 100 nm and below, restoring performance and power scaling that had plateaued during the later FinFET generations. This capability has driven industry-wide adoption of GAA as the successor to FinFET technology beyond the 3 nm node.

Beyond electrostatics, GAA devices introduce unprecedented design flexibility. Unlike FinFETs, which rely on discrete fin counts to adjust effective width, GAA transistors allow continuous tuning of nanosheet width. This feature enables designers to finely balance speed and power consumption within the same process node. Wider nanosheets support high-performance computing and server applications, while narrower nanosheets reduce power consumption for mobile and AI-centric workloads. This broad coverage across the speed–power spectrum makes GAA particularly well suited for heterogeneous systems and application-specific optimization.

The rise of generative AI and large language models has further amplified the importance of GAA technology. AI workloads demand exponential growth in compute capability, pushing systems toward petascale and exascale performance levels. At the same time, global data center power consumption is projected to increase dramatically, raising concerns about energy sustainability. GAA transistors directly address this tension by enabling higher performance per watt and supporting increased SRAM density. Higher on-chip memory density reduces off-chip data movement, improving data locality and lowering energy costs associated with high-speed interconnects.

Crucially, GAA also serves as a structural platform for future transistor innovations. Architectures such as Forksheet FETs and three-dimensional stacked FETs (3DSFETs) build directly upon the GAA concept, preserving its electrostatic advantages while enabling further area scaling. When combined with backside power delivery networks, these advanced structures offer improved routing efficiency, reduced voltage drop, and enhanced overall performance. Together, these innovations position GAA as the cornerstone of “beyond-GAA” logic technologies.

Bottom line: The transition to Gate-All-Around technology marks a foundational shift in semiconductor design. GAA is not merely a replacement for FinFETs, but a scalable, flexible, and energy-efficient platform capable of supporting future logic architectures and sustainable AI growth. As device scaling continues to confront physical and power-related constraints, the successful implementation of GAA will determine the industry’s ability to meet the performance, efficiency, and societal demands of next-generation computing.

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VSORA Board Chair Sandra Rivera on Solutions for AI Inference and LLM Processing

VSORA Board Chair Sandra Rivera on Solutions for AI Inference and LLM Processing
by Lauro Rizzatti on 02-09-2026 at 6:00 am
Categories: CEO Interviews

Sandra Rivera VISORA

Sandra Rivera, a Silicon Valley veteran who is the former CEO of Altera, an Intel FPGA spinout, and long-time Intel executive, recently became Chair of the Board of Directors of Paris-based VSORA. VSORA, a technology leader redefining AI inference for next-generation data centers, cloud infrastructure and edge, is focused on addressing high-performance, low-latency inference use cases, a market that is expected to grow to $250B by 2029.

I recently had a chance to talk with Rivera to find out more about what she sees as VSORA’s strengths and opportunities.

Rizzatti: What specific technical bottlenecks in the current AI hardware landscape convinced you that VSORA’s unique architecture provides a solution?

Rivera: One of the things we know now, in terms of the AI industry and the juncture that we’re at, is that the bottleneck for more scalable deployments is not in raw compute—it is absolutely about data movement. And if you look at the current architectures being deployed, they’ve been focused more on heavy training workloads, which GPUs are more suited.

If you look at the problem we’re trying to solve around AI inference—particularly for large models and real-time workloads—we know that performance is not constrained by compute, but by memory bandwidth, latency, and determinism,.

When we look at the problems customers are expressing to us, they want a solution that addresses high throughput, low latency, and a more deterministic set of requirements that they need to deploy in their environments. And VSORA’s architecture directly attacks this problem in terms of how data flows through the system. It minimizes off-chip memory access, maximizes effective bandwidth, and delivers much more predictable latency.

What we’re hearing from customers is that current solutions are increasingly underutilized for inference—perhaps even over-engineered for inference. They’re expensive to scale and power-hungry, whereas the VSORA architecture and product are compelling because they are built specifically to address this bottleneck: high-bandwidth, low-latency, scalable inference.

And these solutions are also quite cost-effective compared to the power-hungry GPUs that were designed to address a different part of the workflow, mainly training.

Rizzatti: Nvidia acquired Groq. Its architecture differs from that of VSORA, but at a 30,000-foot view, the problem it is addressing is similar. Do you view this acquisition as an implicit acknowledgement by Nvidia that the GPGPU is not doing the proper job for LLM processing?

Rivera: The investment by Nvidia in Groq certainly reinforces the position we’ve taken regarding the problem we’re focused on solving. It validates the thesis for the VSORA business, which is that customers are increasingly looking for solutions to address the AI inference problem.

This is about power efficiency, cost per token, and certainly much lower latency and more determinism than you’re able to get from more general purpose computing architectures.

So yes, it’s quite helpful, because the market leader is acknowledging that it is not a one-size-fits-all architecture for addressing all the different elements of an overall AI workflow. Indeed, you need heterogeneous architectures that address different areas of that AI continuum.

For us, it’s a strong validation that the thesis we had—focusing on what is probably the biggest pain point and the largest market opportunity in the coming years—is correct: low-latency, high-performance inference that is cost-effective and power-efficient. And with our innovative architecture, we address those problems head-on.

Rizzatti: In a previous chapter, the VSORA team founded, built, and successfully exited a company called DibCom, an innovator in radio decoding that developed an advanced digital signal processor. In many ways, it laid the groundwork for VSORA. Are you confident this same team can achieve a similar level of success in AI.

Rivera: One of the biggest appeals for me in joining the team—and for prospective customers considering VSORA solutions—is the fact that this is a team that has been working together and delivering products for many years.

They have had 14 successful tape-outs in their history. They have now taped out a very complex logic device on leading process technology, including advanced packaging technology and high-bandwidth memory embedded into the overall platform.

It is not an easy thing for organizations, and certainly for silicon development teams, to come together and deliver complex products. The fact that this team, with this particular leader—the CEO—has done that 14 times before, and now has done it once again in an fast-moving field like AI, really demonstrates the cohesiveness of the team and the deep experience and expertise they have in developing complex silicon products.

I think it is one of the biggest differentiators of VSORA compared with many of the new startups that don’t necessarily have a history of working together or a demonstrated track record of success.

I consider this one of the major positives that prospective customers can feel confident about when choosing VSORA solutions for their AI infrastructure.

Rizzatti: Do you agree or disagree with the “one size doesn’t fit all” narrative that a few major players in AI processing promote? How does VSORA fit into this narrative?

Rivera: As I said earlier, the industry is very much moving toward heterogeneous architectures that address the entire AI workflow.

Even if you look at the role of the CPU as the head node and orchestrator, it handles preprocessing and data cleaning before training. GPUs and highly parallel architectures used effectively for training-heavy workloads with massive frontier models.

Then you move into architectures designed for specific parts of the workflow and different applications. Some focus on media processing, some on networking throughput and others on storage acceleration.

In our case, we are focused on efficient data movement between the processing engine and external memory. We have a unique architecture that addresses the memory wall problem where compute units stall waiting for data, resulting in wasted performance and excessive power draw.  Our award-winning, patented architecture enables a very power-efficient, low-latency, and low-cost solution for the AI inference problem.

The need for heterogeneous architectures to address the varying AI workload requirements is not just my belief – you’re seeing a number of strategic partnerships, collaborations, and acquisitions in the industry to support this approach..

Lauro: 2025 was defined by the race to scale. As we look forward to 2026 and beyond, what would you predict to be the main trends?

Rivera: I think the next phase will be defined much more around efficiency, specialization, and economics—going back to having the right architecture for the right part of the workload.

All the data and analyst research show that inference is going to dominate in terms of what enterprises are looking to address for large-scale deployments.

Problems around latency, power efficiency, and deployment costs will matter much more than headline peak benchmark numbers, which is how much of the industry has evaluated solutions to date.

I think we will also see tighter coupling between software and hardware, and architectures specifically designed for inference characteristics will shine compared to solutions repurposed from training accelerators.

In that market landscape, and in meeting customer requirements, VSORA is very well positioned—not because we seek to be different, but because we are aligned with customer pain points and where the market is heading.

We believe we will be a major player in enabling AI to scale sustainably, not just because of the technical solution, but also because of the commercial attractiveness of the offer.

Contact VSORA

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TSMC & GCU Semiconductor Training Program: Preparing Tomorrow’s Workforce

TSMC & GCU Semiconductor Training Program: Preparing Tomorrow’s Workforce
by Daniel Nenni on 02-08-2026 at 2:00 pm
Categories: Foundries, TSMC

TSMC GCU Semiconductor Training Program

The expansion of semiconductor manufacturing in the United States, particularly with TSMC’s multi-fab campus in Phoenix, Arizona, has created a significant need for skilled technical workers. To meet this demand, TSMC has partnered with educational institutions, including Grand Canyon University (GCU), to launch innovative training pathways aimed at preparing individuals for careers in semiconductor fabrication and operations. This partnership is part of a broader ecosystem effort involving government, workforce boards, community colleges, and universities working together to develop a sustainable talent pipeline for the semiconductor industry.

Why the Program Exists

Semiconductor manufacturing is one of the most technically demanding and high-technology sectors in the global economy. Operating advanced fabrication facilities, or “fabs”, requires talent with specialized skills in automated systems, precision processes, cleanroom operations, and semiconductor science. When TSMC announced its Arizona investment, one of the key challenges highlighted was the shortage of locally available semiconductor workforce talent with requisite technical skills. In response, the company and regional partners have collaborated on training and apprenticeship programs to build that talent ecosystem locally.

Program Structure and Partnerships

The TSMC-GCU semiconductor training program, formally known as the Manufacturing Specialist Intensive Pathway, is an industry-aligned educational pathway created to prepare participants for technical roles within semiconductor manufacturing. This initiative is part of a broader suite of workforce development efforts that also include registered apprenticeship programs, technician training with community colleges and Northern Arizona University, and other industry partnerships.

At its core, the program with Grand Canyon University focuses on equipping individuals with practical skills that map directly to Manufacturing Specialist roles at TSMC’s Phoenix fabs. The curriculum encompasses semiconductor fundamentals, wafer fabrication processes, standard operational procedures, and factory-floor workflows, all of which are foundational knowledge areas for anyone seeking to enter semiconductor manufacturing.

Program Details

Duration & Format: The program typically runs over a 15-week period, blending classroom instruction with industry-relevant learning experiences designed to mirror real semiconductor manufacturing environments.

Credentialing: Participants earn a certificate of completion from GCU, along with 16 college credit hours, and industry-recognized professional credentials from the Institute of Electrical and Electronics Engineers (IEEE), which helps validate competencies to employers.

Target Audience: The training is geared toward a wide range of learners — from high school graduates and career changers to individuals already in the workforce seeking new tech-focused opportunities.

Pathway to Employment: Successful participants gain not only educational credentials but also a competitive advantage when applying for semiconductor technician, manufacturing specialist, or related technical roles at TSMC or other semiconductor firms in Arizona.

Broader Workforce Strategy

While the GCU partnership is a key piece of the talent development puzzle, it sits within a larger regional workforce strategy. TSMC’s Registered Technician Apprenticeship program, supported by the State of Arizona, the City of Phoenix, and institutions like Estrella Mountain Community College, Northern Arizona University, and other partners, offers multi-year apprenticeship pathways in equipment, process, and facilities technician roles that combine classroom instruction with paid on-the-job training.

These programs are designed to address both entry-level and advanced technical needs. Apprentices typically work hands-on in real semiconductor environments while earning credit and experience, which can lead to stackable credentials and even associate or bachelor’s degrees when combined with college coursework.

Impact and Future Prospects

The TSMC-GCU semiconductor training program underscores the importance of public-private educational collaboration in scaling a skilled workforce fast enough to match the pace of industrial growth. By equipping participants with relevant technical knowledge and credentials recognized by both academia and industry, the program not only fills immediate labor gaps but also fosters long-term career opportunities in a high-tech sector that is becoming increasingly critical for U.S. competitiveness.

Bottom line: This initiative helps bridge the transition from education to employment in a field where the demand for skilled workers is projected to grow as semiconductor manufacturing continues to expand across the United States.

GCU and TSMC’s MSI Pathway Webinar

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