Photonic Computing – Now or Science Fiction?

Photonic Computing – Now or Science Fiction?
by Mike Gianfagna on 02-26-2024 at 6:00 am
Categories: AI, Cadence, EDA, Events

Cadence recently held an event to dig into the emerging world of photonic computing. Called The Rise of Photonic Computing, it was a two-day event held in San Jose on February 7^th and 8^th. The first day of the event was also accessible virtually. I attended a panel discussion on the topic – more to come on that. The day delivered a rich set of presentations from industry and academic experts intended to help you tackle many of your design challenges. Some of this material will be available for replay in late February. Please check back here for the link. Now let’s look at a spirited panel discussion that asked the question, Photonic computing – now or science fiction?

The Panelists

There is a photo at the top of this post of the panel Moving left to right:

Gilles Lamant, distinguished engineer at Cadence moderated the panel. Gilles has worked at Cadence for almost 31 years. He is a Virtuoso platform architect and a design methodology consultant in San Jose, Moscow, Tokyo and Burlington Vermont. Gilles has a deep understanding of system design and kept the panel moving in some very interesting directions.

Dr. Daniel Perez-Lopez, CTO and co-founder of iPronics, a company that aims to expand photonics processing to all the layers of the industry with its SmartLight processors. The company is headquartered in Valencia, Spain.

Dr. Michael Förtsch, Founder and CEO of Q.ANT, a company that develops quantum sensors and photonic chips and processors for quantum computing based on its Quantum Photonic Framework. The company is headquartered in Stuttgart, Germany.

Dr. Bahvin Shastri, Assistant Professor, Engineering & Applied Physics, Centre for Nanophotonics, Queen’s University, located in Kingston, Ontario, Canada. Bhavin presented the keynote address right before the panel on Neuromorphic Photonic Computing, Classical to Quantum.

Dr. Patrick Bowen, CEO of and co-founder of Neurophos, a company that is pioneering a revolutionary approach to AI computation, leveraging the vast potential of light. Neurophos leverages metamaterials in its work, they are based in Austin, Texas.

That’s quite a lineup of intriguing worldwide startups and advanced researchers. The conversation covered a lot of topics, insights and predictions. Watch for the replay to hear the whole story. In the meantime, here are some takeaways…

The Commentary

Gilles observed that some of the companies on the panel look like traditional players in the sense that they use existing materials and fabs to build their products but others are innovating in the materials domain and therefore need to build the factory and the product. This observation highlights the fact that photonic computing is indeed a new field. The players that are building fabrication capabilities may become vertically integrated suppliers or they may become pure-play fab partners to others. It’s a dynamic worth watching.

Bahvin commented on this topic from an academic research perspective. His point of view was that, if you can get it done with mainstream silicon photonics, that’s what you do. However, new and exotic materials research is opening up possibilities that are not attainable with silicon and so advanced work like that will be important to realize the broader potential of the technology.

Other discussions on this topic pointed out that the massive compute demands of advanced AI algorithms simply cannot fit the size or power envelope required using silicon. New materials will be the only way forward. In fact, some examples were given as to how challenging applications such as transformers can be re-modeled in a way that makes them more appropriate for the analog domain offered by photonic processing.

An interesting observation was made regarding newly minted PhD students. What if part of the dissertation was to develop a pitch about the invention and try it with a VC. This would bring a reality check to the invention process – how does the invention contribute to the real world? I thought that was an interesting idea.

Here is a good quote from the discussion: “Fifty years of Moore’s Law and we are still at the stage where we haven’t found an efficient computer to simulate nature.” This is a problem that photonic computing has a chance to solve.

Gilles ended the panel with a question regarding when photonic computing would be fully mainstream. 10 years, 20 years? No one was willing to answer. We are at the beginning of a very exciting time.

To Learn More

Much of the first day of the event will be available for replay, including this panel. Check back here around the end of February. In the meantime, you can check out what Cadence has to offer for photonic design here. The panel Photonic computing – now or science fiction? didn’t necessarily answer the question, but it did deliver a lot of detail and insights to ponder for the future.

February 23, 2024February 13, 2025

Intel Direct Connect Event

Intel Direct Connect Event
by Scotten Jones on 02-23-2024 at 12:00 pm
Categories: Events, Foundries, Intel Foundry
20 Comments

On Wednesday, February 21^st Intel held their first Foundry Direct Connect event. The event had both public and NDA sessions, and I was in both. In this article I will summarize what I learned (that is not covered by NDA) about Intel’s business, process, and wafer fab plans (my focus is process technology and wafer fabs).

Business

Key points in the keynote address from my perspective.

Intel is going to organize the company as Product Co (not sure Product Co is the official name) and Intel Foundry Services (IFS) with Product Co interacting with IFS like a regular foundry customer. All the key systems will be separated and firewalled to ensure that foundry customer data is secure and not accessible by Product Co.
Intel’s goal is for IFS to be the number two foundry in the world by 2030. There was a lot of discussion about IFS being the first system foundry, in addition to offering access to Intel’s wafer fab processes, IFS will offer Intel’s advanced packaging, IP, and system architecture expertise.
It was interesting to see Arm’s CEO Rene Haas on stage with Intel’s CEO Pat Gelsinger. Arm was described as Intel’s most important business partner, and it was noted that 80% of parts run at TSMC have Arm cores. In my view this shows how seriously Intel is taking foundry, in the past it was unthinkable for Intel to run Arm IP.
Approximately 3 months ago IFS disclosed they had orders with a lifetime value of $10 billion dollars, today that has grown to $15 billion dollars!
Intel plans to release restated financials going back three years breaking out Product Co and IFS.
Microsoft’s CEO Satya Nadella appeared remotely to announce that Microsoft is doing a design for Intel 18A.

Process Technology

In an NDA session Ann Kelleher presented Intel’s process technology.
Intel has been targeting five nodes in four years (as opposed to the roughly 5 years it took to complete 10nm). The planned nodes were i7, i4 Intel’s first EUV process, i3, 20A with RibbonFET (Gate All Around) and PowerVia (backside power), and 18A.
i7 and i4 are in production with i4 being produced in Oregon and Ireland, and i3 is manufacturing ready. 20A and 18A are on track to be production ready this year, see figure 1.

Figure 1. Five Nodes in Four Years.

I can quibble with whether this is really five nodes, in my view i7, i3 and 18A are half nodes following i10, i4, and 20A, but it is still very impressive performance and shows that Intel is back on track for process development. Ann Kelleher deserves a lot of credit for getting Intel process development back on track.

Intel is also filling out their offering for foundry, i3 will now have i3-T (TSV), i3-E (enhanced), and i3-P (performance versions).
I can’t discuss specifics, but Intel showed strong yield data for i7 down through 18A.
20A and 18A are due for manufacturing readiness this year and will be Intel’s first RibbonFET processes (Gate All Around stacked Horizontal Nanosheets) and PowerVia (backside power delivery. PowerVia will be the world’s first use of backside power delivery and based on public announcement I have seen from Samsung and TSMC, will be roughly two years ahead of both companies. PowerVia leaves signal routing on the front side of the wafer and moves power delivery to the backside allowing independent optimization of the two and reduces power droop and improves routing and performance.
18A appears to be generating a lot of interest and is progressing well with 0.9PDK released and several companies have taped out test devices. There will be an 18A-P performance version as well. It is my opinion that 18A will be the highest performance process available when it is released although TSMC will have higher transistor density processes.
After 18A Intel is going to a two-year node cadence with 14A, 10A and NEXT planned. Figure 2 illustrates Intel’s process roadmap.

Figure 2. Process Roadmap.

Further filling out Intel’s foundry offering they are developing a 12nm process with UMC and a 65nm process with Tower.
The first High NA EUV tool is in Oregon with proof points expected in 2025 and production on 14A expected in 2026.

Design Enablement

Gary Patton presented Intel’s design enablement in an NDA session. Gary is a longtime IBM development executive and was also CTO at Global Foundries before joining Intel. In the past Intel’s nonstandard design flows have been a significant barrier to accessing Intel processes. Key parts of Gary’s talk:

Intel is adopting industry standard design practices, PDK releases and nomenclature.
All the major design platforms will be supported, Synopsys, Siemens, Cadence, Ansys and representatives from all four presented in the sessions.
All the major foundational IP is available across Intel’s foundry offering.
In my view this is a huge step forward for Intel, in fact they discussed how quickly it has been possible to port various design elements into their processes now.
The availability of IP and the ease of design for a foundry are critical to success and Intel appears to have checked off this critical box for the first time.

Packaging

Choon Lee presented packaging and he is another outsider brought into Intel, I believe he said he had only been there 3 months. Another analyst commented that it was refreshing to see Intel putting people brought in from outside in key positions as opposed to all the key people being long time Intel employees. Packaging isn’t really my focus but a couple of notes I thought were key:

Intel is offering their advanced packaging to customers and referred to it as ASAT (Advanced System Assembly and Test) as opposed to OSAT (Outsourced Assembly and Test).
Intel will assemble multiple die products with die sourced from IFS and from other foundries.
Intel has a unique capability for testing singulated die that enables much faster and better temperature control.
Figure 3 summarizes Intel’s foundry and packaging capabilities.

Figure 3. Intel’s Foundry and Packaging.

Intel Manufacturing

Also under NDA Keyvan Esfarjani presented Intel’s manufacturing. Key disclosable points are:

Intel is the only geographically diverse foundry with Fabs in Oregon, Arizona, New Mexico, Ireland and Israel and planned fabs in Ohio and Germany. Intel builds infratsutures around the fabs at each location.
The IFS foundry model will enable Intel to ramp up processes and keep them in production as opposed to ramping up processes and then ramping them down several years later the way they previously did as an IDM.
Intel fab locations:
- Fab 28 in Israel is producing i10/i7 and fab 38 is planned for that location.
- Fab 22/32/42 in Arizona are running i10/i7 with fabs 52/62 planned for that site in mid 2025 to run 18A.
- Fab 24 in Ireland is running 14nm with i16 foundry planned, Fab 34/44 also at that location are running i4 now and ramping i3. They will eventually run i3 foundry.
- Fab 9/11x in new Mexico is running advanced packing and will add 65nm with Tower in 2025.
Planned expansions in Ohio and Germany.
Oregon wasn’t discussed in any detail presumably because it is a development site although it does do early manufacturing. Oregon has Fabs D1C, D1D and 3 phase of D1X running with rebuilds of D1A and an additional 4^th phase of D1X being planned.

Conclusion

Overall, the event was very well executed, and the announcements were impressive. Intel has their process technology development back on track and they are taking foundry seriously and doing the right things to be successful. TSMC is secure as the number one foundry in the world for the foreseeable future, but given Samsung’s recurring yield issues I believe Intel is well positioned to challenge Samsung for the number two position.

Also Read:

ISS 2024 – Logic 2034 – Technology, Economics, and Sustainability

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How Disruptive will Chiplets be for Intel and TSMC?

Podcast EP209: Putting Soitec’s Innovative Substrates to Work in Mainstream Products with Dr. Christophe Maleville

Podcast EP209: Putting Soitec’s Innovative Substrates to Work in Mainstream Products with Dr. Christophe Maleville
by Daniel Nenni on 02-23-2024 at 10:00 am

Dan is joined by Dr. Christophe Maleville, chief technology officer of Soitec’s Innovation. He joined Soitec in 1993 and was a driving force behind the company’s joint research activities with CEA-Leti. For several years, he led new SOI process development, oversaw SOI technology transfer from R&D to production and managed customer certifications.

He also served as vice president, SOI Products Platform at Soitec, working closely with key customers worldwide. Christophe has authored or co-authored more than 30 papers and also holds some 30 patents.

In this fascinating and informative discussion, Christophe details the innovations Soitec has achieved in engineered substrates, with a particular emphasis on silicon carbide material. He explains how these unique substrates are manufactured. The qualification that has been achieved with partners as well as how the manufacturing process is cost optimized and environmentally friendly are also discussed.

Chistophe cites some impressive data that shows the improvements the technology can deliver for EVs along with a timeline for production deployment.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

February 23, 2024July 17, 2024

A Candid Chat with Sean Redmond About ChipStart in the UK

A Candid Chat with Sean Redmond About ChipStart in the UK
by Daniel Nenni on 02-23-2024 at 6:00 am
Categories: Semiconductor Services, Silicon Catalyst

When I first saw the Silicon Catalyst business plan 10 years ago I had very high hopes. Silicon Valley design starts were falling and Venture Capital Firms were distracted by software companies even though without silicon there would be no software.

Silicon Catalyst is an organization focused on accelerating silicon-based startups. It provides a unique incubation ecosystem designed to help semiconductor-centric startups overcome the challenges they face in bringing their innovations to market. Silicon Catalyst offers access to a broad range of resources including mentors, industry partners, investors, and other support services critical for the success of startups in the semiconductor space. The organization aims to foster innovation and entrepreneurship within the semiconductor industry by providing startups with the guidance, resources, and networking opportunities they need to thrive.

We have been collaborating with Silicon Catalyst for 4 years with great success. SemiWiki is part of the Silicon Catalyst ecosystem. We not only offer the incubating companies coverage (CEO interviews and podcasts), we attend the Silicon Catalsyt events and participate on many different levels. It has been an incredibly enriching partnership, absolutely.

One of the advantages of being a semiconductor professional is we get to work with the smartest and most driven people in the world. We also get to see new technologies developing that may change the world. I was on the ground floor of the smartphone revolution which changed the world and it does not even compare to what AI will do, my opinion. Bottom line: If you look at the Silicon Catalyst incubate companies you will see the future.

Two years ago Silicon Catalyst invaded the UK under the guidance of Sean Redmond. Sean and I started in Semiconductors the same year and have run into each other quite a few times, twice during acquisitions. Sean is the Silicon Catalyst Managing Partner for the UK. With the overwhelming success of the first one, Sean is launching the 2^nd Cohort of the ChipStart UK Incubator. In the first cohort, eleven semiconductor startups are now half way through the nine month incubation with great success. They have full access to everything they need to deliver a full tape-out and experienced advisors to get them there safely.

I had a long conversation with Sean last week to get more details on semiconductors in the UK. AI seems to be driving the semiconductor community in the UK, and the rest of the world for that matter. Millions of dollars have already been raised by the first Chip Start program and Sean expects bigger things the second time around. The goal in the UK is to have a herd of semiconductor unicorns and I have no doubt that will be the case since the UK already has the 4^th largest semiconductor based R&D.

Low power AI is a big part of the semiconductor push in the UK as you might suspect. Some of the applicants are spin outs from Universities and have first time senior executives. As part of the program classes are offered on IP strategy, legal protection, all parts of goto market plans, and of course fundraising. Exit strategies are also important as semiconductor start-ups have an average ten year life span so it is a marathon not a sprint.

Here is the related press release

Sean also mentioned that the GSA will return to the UK with an event in London next month in partnership with UK Government’s Department for Science, Innovation & Technology (DSIT) to jointly explore the impact of semiconductor innovation in anticipation to a NetZero economy. You can get details here:

Semiconductor Innovation for NetZero

About Silicon Catalyst

Silicon Catalyst is the world’s only incubator focused exclusively on accelerating semiconductor solutions, built on a comprehensive coalition of in-kind and strategic partners to dramatically reduce the cost and complexity of development. More than 1000 startup companies worldwide have engaged with Silicon Catalyst and the company has admitted over 100 exciting companies. With a world-class network of mentors to advise startups, Silicon Catalyst is helping new semiconductor companies address the challenges in moving from idea to realization. The incubator/accelerator supplies startups with access to design tools, silicon devices, networking, and a path to funding, banking and marketing acumen to successfully launch and grow their companies’ novel technology solutions. Over the past eight years, the Silicon Catalyst model has proven to dramatically accelerate a startup’s trajectory while at the same time de-risking the equation for investors. Silicon Catalyst has been named the Semiconductor Review’s 2021 Top-10 Solutions Company award winner.

The Silicon Catalyst Angels was established in July 2019 as a separate organization to provide access to seed and Series A funding for Silicon Catalyst portfolio companies. SiliconCatalyst.UK. a subsidiary of Silicon Catalyst, was selected by the UK government to manage ChipStart UK, an early-stage semiconductor incubator funded by the UK government.

More information is available at www.siliconcatalyst.uk, www.siliconcatalyst.com and www.siliconcatalystangels.com.

Also Read:

Seven Silicon Catalyst Companies to Exhibit at CES, the Most Powerful Tech Event in the World

Silicon Catalyst Welcomes You to Our “AI Wonderland”

McKinsey & Company Shines a Light on Domain Specific Architectures

February 22, 2024July 18, 2025

Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries

Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries
by Mike Gianfagna on 02-22-2024 at 10:00 am
Categories: AI, IP, Synopsys

The relentless demand for lower power SoCs is evident across many markets. Examples include cutting-edge mobile, IoT, and wearable devices along with the high compute demands for AI and 5G/6G communications. Drivers for low power include battery life, thermal management and, for high compute applications, the overall cost of operation. Several approaches are available to achieve low power. A common thread for many is the need for optimal Foundation IP, that is, embedded memories and logic libraries. This is an area of significant investment and market leadership for Synopsys. Two informative publications are now available to help you understand the options and benefits that are available. It turns out achieving extreme low power with Synopsys Foundation IP memory compilers and logic libraries is within reach.

Let’s look at the information that is available.

Technical Bulletin

I’ll start with Optimizing PPA for HPC & AI Applications with Synopsys Foundation IP, a technical bulletin that focuses on logic libraries. The piece provides details on Synopsys’ tool-aware Foundation IP solution. Topics such as optimized circuitry, broad operating voltage range support and the flexibility to add customer-specific optimizations are discussed. The article also offers a perspective on achieving either maximum possible performance or the best power-performance trade-off. The figure below summarizes the logic library circuits available in the HPC Design Kit.

Synopsys HPC Design Kit components

Details of how power improvements are achieved is provided across many applications and design strategies. Topics that are covered include dynamic voltage scaling across a wide operating voltage range, optimizing AI and application-specific accelerator block PPA, solutions for network on chip, and how the Synopsys HPC Design Kit is co-optimized with Synopsys EDA for efficient SoC Implementation.

This technical bulletin provides a rich set of information and examples. You can access this information here.

White Paper

Also available is a comprehensive white paper entitled, How Low Can You Go? Pushing the Limits of Transistors. This piece digs into both embedded memories and logic libraries. It examines the details behind achieving extreme low power. Several application areas are discussed, including mobile, Bluetooth and IoT, high-performance computing, automotive, and crypto.

For embedded memories, several approaches are discussed, including assist techniques and splitting supply voltages. It is pointed out that careful co-optimization between technology and the design of memory assist circuits is required to deliver dense, low-power memory operation at low voltages. Several enhanced assist techniques are reviewed. Improvements in power range from 10% to 37%.

Reliability of memories is also discussed. The piece explains that as the voltage is reduced, the SRAM cell starts showing degradation. This degradation can cause multiple issues: reads are upset, the bitcell does not flip, SER is pronounced, sensing fails, control signals deviate, and the BL signal weakens. Therefore, assist techniques are needed to support the lower extreme low voltages required by cutting-edge low power applications.

The approaches Synopsys takes here make a significant difference. Strategies to improve reliability and methods to simulate aging are discussed. You should read the details for yourself – a link is coming. The data shows compelling results, with five to ten years of life added.

Logic libraries are also discussed, with strategies to enable deep low voltage operation at 0.4v and below. Architectural optimization is also reviewed. Standard cell architectural techniques can be employed to reduce both dynamic and leakage power. For example, Synopsys uses stack-based versus stage-based architectural techniques for the optimal topology for deep low voltage operation. The strategy behind this approach is presented.

Characterization optimization is also covered. One important piece of characterization is modeling process variation across an SoC, referred to as on chip variation (OCV). Several advanced techniques are employed here, including machine learning to increase accuracy and optimize performance and power.

The white paper concludes with an overview of how to put everything together at the SoC level to achieve deep low voltage operation. Voltage reduction is discussed, along with dynamic voltage and frequency scaling (DVFS) techniques and various shut-down strategies such as light sleep, deep sleep, full shut down and POFF (Periphery OFF) modes.

This white paper covers a number of power optimization topics in excellent detail. I highly recommend it. You can get your copy here. And that’s how achieving extreme low power with Synopsys Foundation IP memory compilers and logic libraries is within reach.

February 22, 2024July 18, 2025

Navigating the 1.6Tbps Era: Electro-Optical Interconnects and 224G Links

Navigating the 1.6Tbps Era: Electro-Optical Interconnects and 224G Links
by Kalar Rajendiran on 02-22-2024 at 6:00 am
Categories: EDA, IP, Synopsys

In the relentless pursuit of ever-increasing data speeds, the 1.6 Terabits per second (Tbps) era looms on the horizon, promising unprecedented levels of connectivity and bandwidth within data centers. As data-intensive applications proliferate and the demand for real-time processing escalates, the need for robust and efficient communication infrastructure becomes paramount. At the heart of this infrastructure lie electro-optical interconnects, poised to revolutionize data transmission with their blend of high-speed, low-latency, and power-efficient capabilities. The adoption of 224G serial links emerges as a critical enabler for achieving end-to-end 1.6Tbps traffic capacity. These high-speed serial links serve as the backbone of data transmission, facilitating seamless communication between various components within the network. Their ability to handle ultra-high data rates and bandwidth demands makes them indispensable for the realization of next-generation communication systems. As with every major technology advancement, there are inherent challenges to be overcome. Both the optical channel and optical engine introduce nonlinear behavior. Traditional simulation-assisted design methods often model optical engines using electrical circuit languages and simulators, assuming linear channels, leading to overly optimistic assessments of interconnect performance.

At the recently held DesignCon 2024 conference, Synopsys presented the results from their electrical-optical co-simulation study using native electrical and optical signal representations. A highlight of this study is that the system design methodology that was utilized accounts for both linear and non-linear impairments, agnostic of technology, data rate, and modulation format. The “System design methodology, simulation and silicon validation of a 224Gbps Serial Link” paper submission received DesignCon 2024 Best Paper Award.

The following are some excerpts from Synopsys’ two paper submissions at DesignCon, namely, “Performance assessment for high-speed 112G/224G SerDes with Direct-Drive Optical Engine” and “System Design Methodology, simulation and silicon validation of a 224Gbps serial link.”

Forward Error Correction in the 1.6T Era

Forward Error Correction (FEC) mechanisms play a pivotal role in enhancing the reliability of data transmission over high-speed links, particularly in the context of 1.6Tbps traffic. While FEC helps combat errors and ensures data integrity, its implementation introduces additional considerations such as power consumption and latency. Striking the right balance between Bit Error Rate (BER), power efficiency, and latency becomes imperative in designing efficient communication systems for the 1.6T era.

The Emergence of Electro-Optical Interfaces

To meet the evolving demands of the 1.6Tbps era, electro-optical interfaces are poised to play a transformative role. These interfaces leverage the advantages of optical technology to deliver high-speed, low-latency, and power-efficient communication solutions. Technologies such as Co-packaged Optics (CPO) and Die-to-Die (D2D) interconnects offer promising avenues for seamlessly integrating optical components into existing data center architectures, ushering in a new era of efficiency and performance.

Navigating Impairments in End-to-End Links

However, the deployment of end-to-end 224G links is not without its challenges. The conventional approach to simulating optical interconnects using electrical circuit languages and simulators, while effective in some cases, comes with several tradeoffs. Impairments such as noise, jitter, distortion, and crosstalk can significantly degrade signal quality and impact overall performance. To address these challenges, meticulous attention must be paid to modeling and mitigating impairments, ensuring the robustness and reliability of communication infrastructure in the face of non-linear effects inherent in optical and electro-optical interfaces.

The Role of Accurate System Modeling

Accurate system modeling is paramount in navigating the complexities of electro-optical interconnects and countering the non-linear effects inherent in optical transmission. By meticulously simulating various components and their interactions, designers can gain invaluable insights into system behavior and identify potential areas for optimization. Furthermore, correlation with silicon implementation ensures that simulation results closely align with real-world performance, enabling informed decision-making and efficient design iterations.

System Simulation to Silicon Correlation Comparison

In Synopsys’ electro-optical co-simulation study, the process of correlating system simulation with silicon involved a detailed setup for performance characterization in the lab. The setup encompassed various components including a BERT, cables, test board daughter card, and the device under test residing in an Ironwood socket. The s-parameters considered in the system model included responses from the Wildriver, the taconic fastrise 12-layer daughter card, and the testchip package. The comparison between silicon results and system simulation outputs showcased the correlation between the two. Overall, the findings from the study underscored the effectiveness of the system simulation model in capturing silicon behavior and provided valuable insights into system performance and optimization.

The below four charts indicate similarities in the PAM4 levels, EYE opening, and BER performance when simulation and silicon were compared.

The impulse response comparison below shows a slight difference in the lock point between simulation and silicon but overall correlation in shape.

The below chart shows the equalization capability of the receiver, with the DSP compensating for ISI and flattening the overall channel response.

The below chart captures the FFE and DFE coefficients from simulation and silicon readings, indicating some differences attributed to variations in the AFE transfer function and CDR lock point.

Summary

As data centers transition into the 1.6Tbps era, the integration of electro-optical interconnects holds the key to unlocking unprecedented levels of connectivity, bandwidth, and efficiency. Through meticulous system modeling, simulation, and correlation with silicon implementation, designers can harness the full potential of these technologies, ushering in a new era of innovation and performance in data center infrastructure. With the convergence of high-speed serial links, advanced FEC mechanisms, and emerging electro-optical interfaces, data centers are poised to meet the escalating demands of modern computing and networking applications, paving the way for a future of unprecedented connectivity and efficiency.

For more details and access to the full papers presented at DesignCon, please contact Synopsys.

For more information about Synopsys High Speed Ethernet solutions, visit www.synopsys.com/ethernet

Also Read:

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Synopsys Geared for Next Era’s Opportunity and Growth

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February 21, 2024September 6, 2024

Arm Neoverse Continues to Claim Territory in Infrastructure

Arm Neoverse Continues to Claim Territory in Infrastructure
by Bernard Murphy on 02-21-2024 at 10:00 am
Categories: 5G, AI, Arm, IP

After owning general purpose compute in cell phones and IoT devices, it wasn’t clear what Arm’s next act might be. Seemingly the x86 giants dominated in datacenters and auguries suggested a bloody war in smaller platforms between Arm and RISC-V. But Arm knew what they were doing all along, growing upwards into infrastructure: cloud compute, wired and wireless communications, out to gateways and even edge devices. At first modestly, recently more aggressively displacing mainstream processors and FPGAs as the front end to AI-centric GPUs, in hyperscaler scale-out and DPUs, in Telcos for gateways and wireless baseband, at the edge in automotive among other applications. To my mind this is an under-appreciated stealth invasion of the fast growing and high value infrastructure underpinning all of our electronic tech.

Consider

Take the Nvidia superchip – the one that propelled the company to a trillion-dollar valuation. This device, called Grace-Hopper, is actually 2 chips. Hopper is the GPU handling all the fancy AI stuff (tensor operations and such) and Grace is a CPU, very tightly coupled to Hopper and designed to handle the bridge to the regular cloud world through I/O and memory management functions. Grace is built on 72 cores of Neoverse V2. As for market value, witness the recent rise in Arm valuation, ascribed to “anything connected to AI”.

Amazon Web Services (AWS) build their power efficient Graviton scale-out servers, most recently their Graviton 4, on Neoverse. Demand for these platforms is high judging by the fact that almost of the AWS EC2 instances are based on Graviton rather than x86 processors. AWS also build their own machine learning platform (Tranium) which Arm cite in their slides, so I’m guessing that has a Neoverse front-end also.

Similarly, Microsoft have announced their Cobalt 100 server chip and their Maia 100 AI chip, both also cited in the Arm Neoverse slides and explicitly said be built on Neoverse. Note that between them AWS and Microsoft Azure own most cloud provider services (CPS) business by a wide margin. Notable also is that other CPS ventures are following similar paths.

Meanwhile, Nvidia have built their Bluefield DPU platform, AWS their Nitro hypervisor system and Microsoft their Azure Boost system, all around Neoverse. Neoverse is appearing all over the place in datacenters. They are already established in Ampere servers and in wireless infrastructure with Nokia, Ericsson and Huawei.

The Engine Driving Neoverse

Arm continues its tempo of new core introductions each year, this year adding V3 in the performance-optimized V-series, N3 in the performance/watt N-series and E3 in the data throughput E-series. Impressively the V2 (previous generation) already benchmarks ahead of X86 processors in SQL database performance, Java and XGBoost (the hot gradient optimizer for machine learning). V3 shows double digit advances over V2 in a range of enterprise-centric benchmarks and a whopping 84% advantage over V2 in AI data analytics. N3 equally shows impressive performance advances over N2 across the board and nearly 200% in AI data analytics.

A recent strategic move builds on Arm’s Compute Subsystem (CSS) cores, announced for the N-series in mid 2023. The previous generation CSS, as Arm describes it, is a customizable compute subsystem, verified, validated, and PPA-optimized by Arm. Think of a multi-core cluster objective for which you don’t just get the Lego pieces (CPU core, coherent interconnect, memory subsystem, etc.) but a complete customizable compute subsystem configured with Neoverse CPU cores, multiple DDR/LPDDR channels, multiple PCIe/CXL PHY/controller. All tuned, verified, validated, and PPA-optimized by Arm to client workloads and a target foundry/process through Arm’s Total Design program.

In this latest announcement, Arm have just announced a new CSS N3 configured to support from 8 to 32 cores per die running at as low as 40W thermal design power for 32 cores. They have also just announced their first V-series CSS, CSS-V3, providing 50% performance boost over CSS-N2. The Microsoft Cobalt chip is built on CSS-N2.

Given fierce competition between CSPs, mobile network operators, and auto OEMS (as an edge example) it seems clear that a diminishing number of product teams will see value in reinventing this CSS wheel themselves. From a CSP perspective, an opportunity to get compute subsystems tuned to their workloads, while saving development cost and time to market, yet preserving differentiated advantage seems like a no-brainer.

What About Software?

Arm is already tied into a well-established ecosystem at all layers of the software stack. For cloud applications it is especially important that Arm be closely tied to cloud-native activities in open-source leadership in languages, tools, Linux distributions, networking, etc., etc. Together with increasingly ubiquitous Arm-based instance, cloud-based software developers see obvious advantages not only to use Arm for development but also to preferentially offer those service on Arm platforms – a virtuous cycle.

To underscore that this strategy is working, Oracle now offer their 19C database platform supporting Arm-based hardware, both in the cloud and on-prem. Similarly, SAP has ported their SAP HANA cloud to AWS Graviton processors. Those are two giant enterprise applications. Given costs and software availability advantages, I am sure more software and SaaS providers will follow.

Very impressive. I don’t know what else to call this other than a stealth invasion into infrastructure. You can read more HERE.

February 21, 2024February 24, 2024

Pinning Down an EUV Resist’s Resolution vs. Throughput

Pinning Down an EUV Resist’s Resolution vs. Throughput
by Fred Chen on 02-21-2024 at 8:00 am
Categories: Lithography
3 Comments

The majority of EUV production is on 5nm and 3nm node, implemented by late 2022. Metal oxide resists have not been brought into volume production yet [1,2], meaning that only organic chemically amplified resists (CARs) have been used instead until now. These resists have a typical absorption coefficient of 5/um [3,4], which means 33% absorption in 80 nm thick resist. This absorption is not that much really, and smaller features require thinner resists in order to maintain a practical aspect ratio of ~2 [5,6]. This, in turn, exacerbates the stochastic effects from the reduced density of photon absorption and subsequent secondary electron generation (Figure 1).

Figure 1. Secondary electrons per nm2 for 50 nm pitch, 3 nm blur, at different absorbed doses and different ratios of peak dose standard deviation to average. Blue: peak dose; orange: edge dose. Red line indicates the printing threshold.

The lower dose leads to a larger variation of secondary electron density, as indicated by standard deviation/average at the peak dose contour (center of bright line) or edge dose contour (half-pitch edge). This is consistent with larger line edge roughness as well as general dose uniformity. The larger variation ultimately comes from standard deviation being equal to the square root of the average; the standard deviation-to-average ratio is inversely proportional to this, which is why it gets higher with lower dose (absorbed photon density).

Smaller pitches at the same dose will also suffer worse stochastic variation. The reason for this is the smaller pitch takes up a smaller area, leading to fewer photons per pitch at a given dose. The standard deviation/average ratio is a fluctuating value even for a fixed dose and pitch. The median for the peak dose contour is plotted in Figure 2, showing similar trends vs. dose for different pitches.

Figure 2. Median standard deviation/average ratio for peak dose contour, as a function of pitch (35-60 nm) and incident dose. The CAR resist thickness is taken to be equal to the pitch; the absorbed dose is determined accordingly. A standard deviation-to-average ratio of 30% is taken to be the acceptance criterion

A standard deviation-to-average ratio of 30% is taken to be the acceptance criterion for the median peak dose variation. For this median value, ratios above 30% are still possible and from Figure 1, these values lead to visibly significant dose non-uniformity extending over 1 nm. Clearly, smaller pitches require significantly higher doses. To keep the productivity dose of 30 mJ/cm2 [7], the pitch is restricted to be 60 nm or larger. However, higher doses will hurt the productivity as the throughput will take a hit (Figure 3) [8].

Figure 3. Throughput vs. dose for a hypothetical 375 W source [8].

For example, a dose of 80 mJ/cm2 with a 375 W source leads to a throughput of 80 WPH, which is not cost-effective compared to DUV multipatterning [9]; ~40 mJ/cm2 is currently targeted to maintain acceptable throughput [10]. Moreover, when doses get too high, the nature of the resist is changed, due to crosslinking [11] or outgassing [12]. Uncleared resist results from dose going too far above the threshold level [11,13]. EUV multipatterning with a wider pitch would be the only way to maintain acceptable doses; this has also been indicated by vendors [14,15].

For the metal oxide resists currently under development [1,2,10,16], the absorption coefficient is increased from 5/um to 20/um [4], giving the trends shown in Figure 4. With the higher absorption, a 35 nm pitch may be achieved with 30-40 mJ/cm2. Larger pitches can use even lower doses, which is better for EUV productivity. However, the sub-25 nm pitches for beyond 3nm node will still require multipatterning [15]. An even higher absorption coefficient would be necessary for the thinner resists that are considered for High-NA EUV lithography [8].

Figure 4. Median standard deviation/average ratio for peak dose contour, as a function of pitch (25-60 nm) and incident dose. The metal oxide resist thickness is taken to be equal to the pitch; the absorbed dose is determined accordingly. A standard deviation-to-average ratio of 30% is taken to be the acceptance criterion.

The above cases only apply to line-space patterns. Contacts and vias are evaluated differently [17] as they are circular shapes. Here, the standard deviation-to-average ratio for the enclosed exposed area is used (Figure 5).

Figure 5. Standard deviation/average ratio for via area as a function of incident dose and pitch. The CAR resist thickness is taken to be equal to the pitch; the absorbed dose is determined accordingly. A Gaussian was fitted to the via half-pitch [17]. The fit lines are for guiding the eye only.

To keep the area 3s/avg below 10%, the dose needs to exceed ~35 mJ/cm2 for the 30 nm via but increases quickly as the via shrinks, with the CAR thickness equal to double the via diameter.

The non-EUV doses in an EUV lithography system [18] have not yet been included in the above estimates, because they have been hard to quantify. Presumably they may help to reduce the standard deviation-to-average ratio, allowing lower dose and therefore higher throughput. However, this comes at the price of reduced image contrast, which will in turn degrade the resolution.

References

[1] https://monoist.itmedia.co.jp/mn/articles/2109/21/news038.html

[2] https://english.etnews.com/20221220200003

[3] W. D. Hinsberg et al., J. Micro/Nanopattern. Mater. Metrol. 014603 (2021).

[4] http://euvlsymposium.lbl.gov/pdf/2015/Posters/P-RE-06_Fallica.pdf

[5] https://web.archive.org/web/20170809103809id_/http://www.sematech.org/meetings/archives/litho/euvl/10157EUVL/pres/Dario%20Goldfarb.pdf

[6] https://www.jstage.jst.go.jp/article/photopolymer/16/3/16_3_369/_pdf

[7] https://www.asml.com/en/products/euv-lithography-systems/twinscan-nxe-3600d

[8] H. J. Levinson, Jpn. J. Appl. Phys. 61 SD0803 (2022).

[9] https://semiengineering.com/euv-reaches-a-crossroads/

[10] I. Seshadri et al., IEDM 2023.

[11] I. Pollentier et al., Proc. SPIE 10957, 109570I (2019).

[12] I. Bespalov et al., ACS Appl. Mat. Interfaces, 12, 9881 (2020).

[13] https://www.euvlitho.com/2016/P79.pdf

[14] https://m.blog.naver.com/PostView.naver?blogId=jkhan012&logNo=222410469787&categoryNo=30&proxyReferer=https:%2F%2Fwww.linkedin.com%2F

[15] A. Raley et al., Proc. SPIE 12056, 120560A (2022).

[16] T. Kohyama et al., Proc. SPIE 12498, 124980A (2023); https://www.semiconkorea.org/ko/node/6866

[17] https://www.youtube.com/watch?v=gkiJBwOE6vM

[18] F. Chen, “Non-EUV Exposures in EUV Lithography Systems Provide the Floor for Stochastic Defects in EUV Lithography,” https://www.linkedin.com/pulse/non-euv-exposures-euv-lithography-systems-provide-floor-chen-jymgc

This article first appeared in LinkedIn Pulse: Pinning Down an EUV Resist’s Resolution vs. Throughput

Also Read:

Application-Specific Lithography: Sense Amplifier and Sub-Wordline Driver Metal Patterning in DRAM

Application-Specific Lithography: Avoiding Stochastic Defects and Image Imbalance in 6-Track Cells

Non-EUV Exposures in EUV Lithography Systems Provide the Floor for Stochastic Defects in EUV Lithography

Continue reading “Pinning Down an EUV Resist’s Resolution vs. Throughput”

February 21, 2024February 25, 2024

Cadence Debuts Celsius Studio for In-Design Thermal Optimization

Cadence Debuts Celsius Studio for In-Design Thermal Optimization
by Bernard Murphy on 02-21-2024 at 6:00 am
Categories: AI, Cadence, Chiplet, EDA

Continuing the multiphysics theme, I talked recently with Melika Roshandell (Product Management Director at Cadence) on the continuing convergence between MCAD and ECAD. You should know first that Melika has a PhD in mechanical engineering and an extensive background in thermal engineering at Broadcom and Qualcomm, all very relevant to this topic. One immediate revelation from this discussion for me was that thermal analysis and optimization for chips and systems is commonly handled by mechanical engineers working cooperatively with the electrical design teams. Makes sense, but that difference in expertise and disciplines can and often does cause significant speed bumps between these elements of design, leading to inefficiencies in execution and optimization. Celsius Studio aims to flatten these speed bumps.

A quick recap on the multiphysics need

There’s an old joke in physics. A dairy farmer asks the local university for help to understand why milk production has dropped at his farm. After hosting a tour of his farm, detailed discussions, and much study back at the university he receives a letter from the theoretical physics department. They tell him that they have found a solution, but it only works for spherical cows in a vacuum. Point being that physicists must greatly simplify a problem, prioritizing just one component to find an analytic solution.

Computer-based numerical analysis doesn’t suffer from that limitation, forgoing exact answers for approximate answers though to whatever precision is needed. It is also not limited to consider only physical effect at a time. Which is just as well because in chip and system design, multiple physical factors are significant at all levels of design and can’t be neatly separated.

Electrical activity unavoidably generates heat (second law of thermodynamics): in a transistor, a block of logic, a chip/chiplet, a package, on a board and in a rack. Heat is generated locally in areas of active usage which can lead to incorrect behavior or physical damage if not effectively dissipated. One way to reduce heating is to lower clock speeds until sufficiently cooled but that reduction also compromises performance. For optimal operation, heat generated by electrical activity (dynamic and leakage) must be dissipated passively (thermal diffusion, radiation, and convection) and/or actively (forced air or liquid cooling). Multiple types of physics must be analyzed together.

Another important consideration is the tendency of structures to warp under heating. Chips/chiplets are fabricated with multiple layers of materials, each with different thermal expansion properties. Chiplets sit on top of interposers and other layers, inside a package sitting on top of a multilayer PCB, and so on – more different materials with different expansion coefficients. When two (or more) connected layers expand under heating, one will expand more than the other. If this differential expansion is big enough the structure will warp. That adds stress to electrical connections between layers which can fracture and disconnect. Problems of this nature do not self-heal after cooling; the only way to fix your phone if connections break is to get a new phone. More multiphysics analysis is needed.

One more wrinkle makes the thermal management problem even more complex. All this analysis must work across a very wide scale range, from tens of microns in the IC design, to tens of centimeters on a board, up to meter ranges in a rack. Heat can be generated at all levels and cooling must be effective at all levels. Multiphysics analysis must also perform at multi-scale.

Celsius Studio targets comprehensive in-design analysis

Celsius Studio integrates together thermal analysis and implementation insights from Innovus for digital circuits, Virtuoso for custom/analog circuits, Integrity for 3D-ICs, AWR for microwave ICs, and Allegro for board design. These insights guide power overall thermal and stress analysis together with heat reduction strategies, placement optimization, and thermal via and temperature sensor placement.

Thermal and stress modeling are accomplished through finite element analysis (FEA), with meshes designed to support necessary accuracies from fine-grained to coarse-grained structures across that wide scale range. Heat dissipation through convection and/or through active cooling (fans, etc.) are modeled in the Cadence Celsius EC Solver.

Obviously, this analysis requires MCAD models which can be created in the tool or can be imported from multiple popular MCAD formats. Sounds easy but historically, according to Melika, difficulties in seamlessly coupling MCAD and ECAD have contributed significantly to those speed bumps. In Celsius Studio, Cadence in-house MCAD and ECAD experts have reduced the import effort from days to negligible impact on the analysis flow. Therefore providing a streamlined path to thermal, stress, and cooling analysis on boards and in-rack.

That streamlined path makes in-design analysis (IDA) a much more realistic proposition. Previous over-the-wall exchanges between engineering and thermal engineering obviously limited opportunities for co-design/optimization, tending to best guess estimates to guide thermal teams followed by a scramble at the end to align against final analytics from the electronics teams. Now with faster turn-times to import mechanical model updates, co-optimization through design becomes feasible, reducing the risk of late scrambles and schedule/BOM changes.

Comprehensive coverage without sweeping parameters

Faster turn-times also allow for AI-enabled analysis. I’m going to go out on a limb here with a little of my own speculation. To analyze/optimize a complex design with many parameters you can sweep those parameters over all possible settings and combinations. However the complexity of sweeping expands exponentially as more parameters are added. There is a concept in Design of Experiments called Covering Arrays which we have written about in an Innovation blog, to massively reduce the number of combinations you must consider while only modestly reducing coverage. There is only one problem – figuring out the right options to pick requires a lot of human ingenuity. Machine learning could be another way to get there, across many more parameters.

I don’t know if this is the method behind Optimality or other tools of this nature, but I do think some related technique may play a role. Especially since this method can be applied to any problem, mechanical or electronic, to select a small and manageable subset from an otherwise impractical sweep range, to achieve near-optimal coverage in analysis 😀

You can read more about Celsius Studio HERE.

February 20, 2024February 20, 2024

Handling Preprocessed Files in a Hardware IDE

Handling Preprocessed Files in a Hardware IDE
by Daniel Nenni on 02-20-2024 at 10:00 am
Categories: AMIQ EDA, EDA

For several years now, I’ve been meeting with AMIQ EDA co-founder Cristian Amitroaie every few months to discuss the state of the industry, key trends in design and verification, and the ways that they help facilitate and accelerate chip development. I noticed an interesting new feature mentioned in their latest press release, so I asked Cristian for more information. This led to a lively and interesting discussion.

Most designers and verification engineers write their code in SystemVerilog these days, but there are exceptions. Some take advantage of high-level synthesis (HLS) tools to design in SystemC or other languages a bit more abstract than SystemVerilog. Others write in their own languages and use custom tools to generate the SystemVerilog files used for simulation, formal verification, synthesis, and other steps in the development process.

Cristian said that they occasionally see a middle ground in which engineers write code that is primarily SystemVerilog but also contains “preprocessor” statements in established languages such as Perl and Python’s Jinja2 library, or in proprietary languages. They use scripts to process these files and generate the pure SystemVerilog files for the rest of the flow. I asked Cristian how the use of preprocessors changes the way that engineers use an integrated development environment (IDE).

I learned that users of the AMIQ EDA Design and Verification Tools (DVT) IDE family want to have access to all their favorite features even when editing files with preprocessor code. The AMIQ EDA team developed clever heuristics to enable full IDE capabilities when editing such files, just as they do with pure SystemVerilog. These features include navigational hyperlinks, autocomplete, on-the-fly error detection, quick fixes, refactoring, and all the advanced functionality DVT IDE users are addicted to.

This was intriguing to me. We are talking about “understanding” mixed-language files, not really something any compiler can easily digest. To make sure I get it right and that this is for real, Cristian invited Zeljko Zurzic, the team lead who coordinated the development of this capability, to explain how it works. He said that all users need do is to inform DVT IDE about the mapping between the files containing preprocessor statements (“p file”) and the generated files (“g file”).

This is done using dedicated compiler directives that support various use cases. For example, there is a way to tell the DVT IDE compiler “go figure out the corresponding p file from the g file header comment.” Once this is done, users just edit their p files as if there is nothing special about them. On-the-fly incremental compilation will flag any SystemVerilog errors as they type, hyperlinks take them around the code, autocomplete and refactoring work just fine, they can request various diagrams, etc.

The sections that contain preprocessor code are marked distinctively so that users know they will be transformed into SystemVerilog code. In DVT Eclipse IDE they can see how code is generated by using the Inspect View; in DVT IDE for VS Code they can “peek” the transformations. DVT IDE can be configured to automatically run the preprocessing script whenever the preprocessor code is changed. Users can easily compare a p file with the corresponding g file if desired.

Zeljko provided three screenshots that show this new capability in action. The first one below shows a file in DVT Eclipse IDE that includes a Jinja2 preprocessor statement. Despite the presence of this non-SystemVerilog code, the user is able to take advantage of the powerful “Show Writers” feature to quickly understand how a variable is driven. Compilation errors and warnings are indicated in the leftmost column of the display.

The screenshot below displays the same file in DVT IDE for VS Code, showing the compiler issues in the left column and enabling the use of autocomplete. This demonstrates how even the most advanced DVT functions are available in code with preprocessor statements.

Zeljko stressed that the IDE checks the generated SystemVerilog code, important because there could be an error in a preprocessor statement or a bug in the preprocessing script. The screenshot below shows just such an example. The generated SystemVerilog code contains a variable that was not defined in the source file. DVT IDE displays the compilation error, the p file, and the generated code in the g file.

Viewing the g files can be helpful in debug, but the bottom line is that users work directly with the p files, analyzing and editing them using a powerful IDE. The g files are tagged as “read only” and users will be warned if they are modified. I was glad to hear this; we all know that it’s a really bad idea to make manual changes to any file that will be overwritten by a code generation process.

Finally, Cristian stressed that the whole point of this new feature is that users can edit code with preprocessor statements just as if it were pure SystemVerilog. Making this possible has been a significant effort driven by a few key customers who rely on preprocessor-based flows. I thanked Zeljko and Cristian for their explanations and their time.

If you’d like to learn more about using preprocessor files or any aspect of the AMIQ EDA solutions, you can visit them in Booth 107 at the Design and Verification Conference and Exhibition (DVCon) United States in San Jose, Calif. on March 5 and March 6.

Also Read:

2024 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA

Using Linting to Write Error-Free Testbench Code

AMIQ: Celebrating 20 Years in Consulting and EDA