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Synopsys at Goldman Sachs Technology Conference

Synopsys at Goldman Sachs Technology Conference
by Paul McLellan on 02-21-2011 at 7:00 pm
Categories: EDA, Synopsys

Aart de Geus was interviewed at the Goldman Sachs Technology Conference last week. Here is some of what he said. Strong Q1, good Q2 outlook, on-track for 2011 guidance. Strong rebound in Far East, Europe mixed, North America good. 80% revenue for year booked by start of year, 90% revenue for a quarter already booked at start of quarter. Predictability has allowed investment.

Five point economic strategy:

[LIST=1]

  • Organic growth in low to mid-single digits
  • Investment in rapid growth adjacencies: systems and IP
  • M&A: 7-8 acquisitions last year
  • Focus on efficiency
  • Maintain flat share count

    20% revenue this year coming from IP products. Second largest IP vendor behind ARM (I’m not sure if he counts Rambus as an IP supplier who were at $323M last year). IP business is changing, no longer make vs buy but differentiated IP the customer wouldn’t be able to design themselves (e.g. USB 3). There used to be 200-300 IP companies 4 years ago, now it is down to a handful since it is so risky to incorporate IP from an unknown supplier. Synopsys is the safe choice since they provide a complete solution.

    Systems: placing a major focus on hardware/software interaction. Acquired3-4 companies around prototyping last year. Bringing technology of VaST and CoWare (and presumably Virtio although he didn’t mention it) together. Decade long process.

    Pricing: industry is very competitive but Synopsys is enforcing pricing discipline. Layering IP on top of big tools deals. Implied competition is doing anything to avoid being designed out at customers.

    • Posted on

    Clock Domain Crossing (CDC) Verification

    Clock Domain Crossing (CDC) Verification
    by Paul McLellan on 02-21-2011 at 6:12 pm
    Categories: EDA

    Multiple, independent clocks are quintessential in SoCs and other complex ASICs today. In some cases, such as in large communications processors, clock domains may number in the hundreds. Clock domain crossings pose a growing challenge to chip designers, and constitute a major source of design errors–errors that can easily slip past conventional verification tools and make their way into silicon.

    When these errors make it into silicon, the costs are high. A single silicon re-spin may cost $10 million and extend time-to-market by months, greatly reducing the chip’s market share and profit potential.

    Therefore, there is a substantial benefit to identifying and correcting CDC problems in the early stages of the design, at the RTL level, when corrections may be made quickly and at minimal cost. Unfortunately, cycle-based simulation, the mainstay of RTL-stage verification, is not well suited to finding and tracing timing-related errors resulting from CDC problems. Static timing analysis tools treat clock domain crossings as exceptions and ignore them. Furthermore, traditional structural CDC analysis tools can help identify clock domain crossings and perform some basic synchronization checking, but none offers the kind of comprehensiveness or precision users require. Such tools tend to simultaneously overlook a number of real design errors and over-report a large numbers of false violations.


    Control signal synchronization


    Data signal synchronization

    When signals cross from one clock domain to another asynchronous domain, several problems can result:

    [LIST=1]

  • Metastability. When a signal from the first clock domain is transitioning just as the second clock domain is clocked, there may be an attempt to clock an invalid logic level into a register. The register may take some time to return to a stable state.
  • Convergence of separately synchronized signals. Since there are times when it is unclear whether a signal will be latched on one clock cycle or the subsequent on, it is possible that two signals changing simultaneously in one clock domain end up a cycle apart in the other domain.
  • Data loss when a signal crosses from a domain with a faster clock to one with a slower clock, for example. More positive synchronization such as handshaking may be necessary

    To detect these problems (and ignore non-problem false errors) a good CDC verification tool must:

    [LIST=1]

  • Identify and display clock domains automatically
  • Identify unsynchronized crossings
  • Screen out false violations
  • Allow users to identify quasi-static signals (e.g. reset signals)
  • Ignore false paths
  • Recognize handshake mechanisms
  • Recognize standard synchronizers, such as 2 flop
  • Allow users to specify non-standard synchronizers
  • Detect problems at synchronized crossings: cross-domain fanouts, cross-domain fanins, reconvergent signals, gray code violations, hold-time violations


    Analysis and display of clock domains

    Images: courtesy Atrenta

    For more details: the Atrenta CDC white-paper


    • Posted on

    Mentor Graphics Should Be Acquired or Sold: Carl Icahn COUNTERPOINT

    Mentor Graphics Should Be Acquired or Sold: Carl Icahn COUNTERPOINT
    by Daniel Nenni on 02-20-2011 at 7:04 pm
    Categories: EDA


    Daniel,

    On Jan 20th, you criticized that the EDA models are all broken and need to change. Ridiculing Synpsys, Cadence, Mentor and Magma for not agreeing to ‘pay for success’ type of model (some form of royalties).

    On Feb 14th, you state thatIcahn doesn’t understand EDA and should stay out. Maybe he is seeing the same issue you have stated. The business models are not correct and do not maximize shareholder returns. Unfortunate for Mentor that over the past x yrs, besides a Cadence hostile takeover attempt, several hedge funds started to become active with Mentor stock. Once this trend started, Mentor became the low hanging fruit with higher visibility and a higher probability for return on their investment. This return might be on short ‘buyouts’ of this funds (pay them to leave) or longer term hostile activities.

    Changing business models is a very tricky issue for public companies. All information needs to be disclosed and this can have dramatic affect on a company’s share price. Over the past 10 years, you can see at least 2 cases for Synopsys and 2+ cases for Cadence. Synopsys over this time period did two incremental jumps to a ratable model (about 50% each time and they are consistently stated 85-90% of sales in a given quarter as ratable). But each time they did this, their stock did go down. It was controlled by limiting to just 50% change. Cadence has done several ‘flips’ on ratable vs non-ratable recognition and also mentioned their ‘token/credit card’ approach. Just as with Synopsys, these events were seen as negative by investors and they predicted a lower EPS. Their stock also dove due to this forecast.

    So public companies that try to change models have external pressure on stock price and lower stock price can enable/cheapen hostile take overs. So actions that affect stock prices are carefully weighed. Companies that are not willing to go this route will use LBOs or Equity groups to purchase the company (with a huge premium paid to sr mgmt along with the equity group) to take a company private. Once private, changing business models and the results from these are not regularly reviewed by the markets (qtrly). Companies that have the cash to work thru these changes can be very successful. They can change business models, strategies, etc. Freescale did this a few years ago and the LBO saddled them with a huge debt to finance. Rich Beyer came in after the LBO was finalized and has done a remarkable job re-aligning the company for targeted markets. Selling off divisions/product lines that do not fit (reducing large expenses with not so large revenue from these groups) as well as trying to retire portions of this large debt. His last tactic/task is the recent announcement of an IPO for $1+B to resolve the final debt. If successful, he will have taken Freescale and remodeled it for a new market….Do a search on various Freescale press releases over the past 3-5 years and you will see the various actions taken.

    There are plenty of other examples of LBOs that have either succeeded or failed. Unsure what % actually are successful with this strategy. This strategy might be as dangerous as remodeling in the public/market eye.

    Concerning Carl or anyone else that is external to a given market, they have a new viewpoint (might be naive or just a different thought process on creating value) that may or may not be valid. Look at all the the changes in the recent 10 years…

    Apple has revolutionized how content is used (iPhone, iPad, iPod, iTunes) and $’s are derived from this content. They alone have probably the largest disruptor in how music, books, TV and movies are acquired and viewed. Kindle/Nook is another form that allows purchasing via WiFi more books that are automatically download to you machine that can hold 1500+ books.

    Twitter, Facebook, LinkedIn are allowing large groups of people to ‘gather’ in areas of common interest (all in parallel….not serial discussions). Facebook is credited (rightfully so) with the recent uprising across the MidEast.

    LED lights are being used in any thing from traffic lights to TVs.

    RFID trackers is another area that some people pushed for specific applications to reduce the cost of manual tracking. Now these are typically in toll tags used to electronically charge/collect tolls from credit card accounts. Removing toll booths that were unsafe (yes, cars had to stop, pay and then remerge with other cars), added time to a driver’s destination, worsened fuel mpg (slowing down, stopping, reaccelerating), and cost more to staff. Lots of people thinking of new ways to apply technology to current issues…

    One negative ‘new’ idea, sub prime loans that made a few people (financial companies and sr mgmt) very rich and undermined the entire economy. Many of these ideas came from established companies wanting to enable/attract a new source of $’s. They also saw the downside and quickly bundled these risky assets into bundles that were sold to other ‘unknowing’ investors. I played golf with one guy that worked at one of these firms. He said it was purchase quickly, re-package and sell fast. Get in, get out and get your commission… we can see where this led the US….

    What is common? Many of these people were not in the same field (including Apple that was tied to computing power….Steve Jobs saw a huge opportunity in content management and changed not only the products but also the business models that many others could not see (that were in the business). Jobs/Apple products and business models aligned with each other.

    These investor events will cause all companies (even Synopsys, Cadence and Magma) to re-evaluate if they should do something different. I do not think that getting kicked out of a comfort zone is bad. It can cause ‘out of the box’ thinking that might be much better than the current situation. Regardless who leads/manages the company. Only time will tell if everyone is in a better place in a few years.

    Complex world out there that behaves more analog than digital.

    (Please keep my identity confidential)

    Posted on

    Mentor Graphics to Participate in SemiWiki.com Social Media Platform

    Mentor Graphics to Participate in SemiWiki.com Social Media Platform
    by admin on 02-17-2011 at 8:16 am
    Categories: EDA, Siemens EDA


    San Jose, Calif., [DATE], 2011 – SemiWiki.com today announced that Mentor Graphics, a world leader in electronic hardware and software design solutions, will participate in the SemiWiki.com global social media platform aimed at facilitating mass communication for electronic design professionals through Web 2.0 technologies.

    The goal of SemiWiki is to bring members of the semiconductor ecosystem together and to foster better collaboration in meeting the challenges of advanced semiconductor design and manufacturing. Mentor, along with other members of the EDA, IP and foundry ecosystem, will contribute meaningful content including company and product wikis, blogs and discussion forums.

    “Mentor’s core value is to enable customer success through collaboration in product design and comprehensive application support,” said Joseph Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “We’re excited about exploring this new way to share our expertise and new product capabilities, and to respond directly to our customers’ questions and needs.”

    The site is now live and may be reached at http://semiwiki.com/. Users can easily set up an account to access information, provide feedback and post content.

    “Our industry needs a site that facilitates real time, vendor neutral discussion among real users,” said Daniel Nenni, internationally recognized industry blogger, and founder of the SemiWiki Project. “SemiWiki.com will provide our registered users with a connected community that promotes the open exchange of ideas, experiences and feedback.”

    About the SemiWiki Project
    The SemiWiki Project provides in-demand content for semiconductor design and manufacturing, facilitating peer-to-peer communications using Web 2.0 technologies. Daniel Nenni will be joined by industry bloggers Paul McLellan, Daniel Payne, Steve Moran, and Eric Esteve at SemiWiki.com.

    Posted on

    Source of IP: Silicon foundries provides 18% of Design IP blocks, IP vendors only 16% to Fabless

    Source of IP: Silicon foundries provides 18% of Design IP blocks, IP vendors only 16% to Fabless
    by Eric Esteve on 02-16-2011 at 12:50 pm
    Categories: Uncategorized
    1 Comment

    Thanks to the Semiconductor Ecosystem Survey from GSA-Wharton and the key indicators of semiconductor companies’ technology strategies related to IP:

    • IP Reuse: On average, a fabless semiconductor company reuses about 63% of design IP in the revision of an existing product design and about 44% in a new product design.
    • Source of IP: Silicon foundries are becoming an important source of design IP for fabless companies in addition to third-party IP firms. On average, 18% of design IP blocks are from the foundry’s portfolio/library, followed by 16% for third-party licensing firms.

    ​

    The other key indicators are about differentiation and time-to-market.Let’s make some comments. First of all, as I am focusing on IP… I am happy, as the report clearly links IP as one of the major source of innovation. But, when I think to my blogger colleagues who’s focus is on EDA (namely, Dan Nenni, Daniel Payne and Paul McLellan), I think they have good reasons to be disappointed, as within the 26 pages you will never found the mention of EDA. The report is dealing about “Innovation”, “partners” and “ecosystem”, referring to the fables companies, so –intentionally or not- deciding to omit EDA companies in the ecosystem looks strange to me… Let’s come back to IP. The number of design IP blocks coming from foundries (18%) is higher than these coming from the IP vendors (16%). Is it a surprise? No, as when looking at the list of IP offered by the major foundries, you realize that this list is pretty long, even if we can qualify these IP as commodities in most of the cases. Yes if you consider the large number of IP vendors (more than 460 listed on D&R). They have to offer differentiated products to compete with their foundry partners! The other figure, 66% of design IP blocks are being internally sourced by the fabless, certainly opens a growth opportunity for the IP “providers” (foundry or IP vendor). We all know that the trend is, and will be, to outsource more design IP blocks, with a limit defined by the fabless themselves: you don’t want to outsource the part of the design on which you build your differentiation. We can guess that these differentiating functions represent a lot less than 66% of the design blocks. The real number is probably in the 20 to 30% range, say 25%, arbitrary. Now, the question is to know how long it will take for the fables to move from 66% down to 25% of internally reused IP blocks: 5 years? 10 years? Let’s look at these two scenarios and forecast the effect on the IP market size growth rate. In one case, the IP market would move from 16% (of design blocks) to 37% in 2015 (assuming the outsourcing is equally shared by the IP vendors and the foundries, which is certainly not right, but the “less wrong” assumption we can make here). If we take into account this outsourcing effect only, this would lead to an IP market CAGR of 18%, and a market size passing from $1 677M in 2010 to $3 850M in 2015.But we know that many other effects can generate the growth: the emergence of new protocols is pushing the fabless or IDM to outsource the function, because it is too complex to design, or require competencies not available within the company. The need to integrate into a SoC the Analog Mixed Signal (AMS) blocks which were previously supported via ASSP. Or new functions issued from innovation, which simply did not exist before, and have to be licensed to the inventors (HDMI is a good example). This to say that the size of the market will be larger than that we have found by only using the growth of outsourcing rate! This 18% CAGR is impressive, especially when you consider the other growth factors for the IP market: · The emergence of new protocols, pushing the fabless or IDM to outsource the function, because it is too complex or too long to design, or require competencies not available within the company.· The need to integrate into a SoC the Analog Mixed Signal (AMS) blocks which were previously supported via ASSP.· Or to integrate new functions issued from innovation, which simply did not exist before, when the shortest path is to licensed it, to the inventors or IP vendors (HDMI is a good example).This to say that the market size should be larger than that we have found by only using the growth of outsourcing rate, so the assumption based on a 5 years period is probably overoptimistic. Let’s rework this evaluation, using a 10 years period instead of 5 for the outsourcing rate to pass from 34% to 75%, the off loading being equally shared by IP vendors and foundries, a questionable assumption (!). The results for 2015 would be:

    If we take into account this outsourcing effect only, this would lead to an IP market CAGR of 12%, and a market size passing from $1 677M in 2010 to almost $3 000M in 2015. Amazingly, this CAGR is similar with the result found by Semico (Semico projects this market to continue to grow, exhibiting a CAGR of 12.6% from 2010 – 2015).

    This is that we could call a “quick and dirty” analysis, which does not take into account all the effects fueling the growth rate of outsourcing IP, and extend to the overall market (IDM and Fabless) the results validated for the Fabless chip makers. The benefit is to show that, opposite to EDA (except if they can change their business model to increase their product value), the IP market will grow and the CAGR (linked to outsourcing only) can be from 12% to 18% depending at what speed the Fabless and IDM will offload the non strategic part of their design.
    Another very interesting point is the fact the foundries are the other beneficiary from outsourcing design IP blocks. This point would request another blog to better understand how the foundries will position this service. Will they act like the FPGA vendors, who have realized for long time now that offering IP is strategic to catch new businesses, and even more to keep their customers captives, but do not necessarily value IP at the right (higher) price? How will the foundries position in respect with the IP vendors, officially their partners? Will they compete with them, considering that IP is a decent source for extra revenue or simply provide IP on a case by case basis? Clearly, they will have to invest even more time to define their IP strategy, and money to develop or acquire the IP function their customer will increasingly need due to outsourcing…

    Eric Esteve (www.ip-nest.com)

    Posted on

    Semiconductor Social Networking Survey Results

    Semiconductor Social Networking Survey Results
    by Daniel Nenni on 02-15-2011 at 9:30 pm
    Categories: Uncategorized
    1 Comment

    The credit here goes to Atrenta for surveying their customer base in an effort to open up new communication channels for in-demand content using Web 2.0 technologies. The results are not surprising to me but they may be to other semiconductor ecosystem executives who do not get Social Media at all!

    I have been using LinkedIn for five+ years and consider it one of the most productive tools for the semiconductor industry on a whole. No matter what your job is, if you are not USING LinkedIn for peer-to-peer communications you are not realizing your full professional potential.

    Blogs are in fact the most effective form of communication for semiconductor professionals today. The analytics behind blogs also provide important trending data to better understand the markets you serve and the people you work with. Blogging is also the most cost effective branding tool available today: company branding, product branding, and people branding. When I started blogging two years ago I was pretty much invisible. Now I’m branded as an “internationally recognized industry blogger”. Go figure.

    I credit Atrenta for promoting blogging in our industry back in July 2009 with a Blogfest at the 46[SUP]th[/SUP] DAC. Here is my blog on it: Blogging From SFO: Beware of Bloggers!A bit dated but still an interesting read. I had just started blogging a couple of months prior. Thank you Mike Gianfagna, Atrenta vice president of marketing, he clearly gets social media. Back when I started, bloggers were not treated as press, and editors did not like us at all. Now bloggers are called NEW MEDIA and treated as well as, if not better than the traditional press. In fact, most of the experienced editors in our industry are now bloggers. Go figure.

    Today everything and everyone is connected and crowdsourced. In fact, all social media, from blogs, to forums and wikis have a profound impact on how people communicate, search for information, and make decisions. Research clearly shows that people who share knowledge and personal experience via blogs, forums, and wikis can influence 40-60% of all visitors to a specific course of action. More and more, people will get product information and direction from independent top influencers rather than getting it from vendor sites, advertisements, or other biased sources.

    For vendors, social media is no longer an experiment or a moonlighting function. Social media is now an integral part of corporate communications. Unfortunately, vendor direct blogging, tweeting, and forums are all sunshine and no rain which limits the credibility. Vendor direct social media is also all talk and no listen (not crowdsourcing). Social media is all about crowdsourcing and that is just not possible on a vendor specific site.

    While Google, Yahoo, Bing, and other search engines will continue to play an important role in social media, peer-to-peer communication sites like the SemiWiki project are the new search. The role of user generated “in-demand” content has changed the way information is exchanged. In contrast to the SALES experience offered by EDA/IP portals, vendor websites, and webinars, SemiWiki brings technology and technologists closer together than ever before, closing the gap between pre-sales expectations and post-sales experience.

    5 things you should know about SemiWiki.com:

    [LIST=1]

  • SemiWiki is global. Your experience here will be from around the world with an incredible amount of information at your fingertips. Make sure you connect and interact, make sure you engage at all levels.
  • Build relationships and network. You can truly connect here with people who you have not met. Make friends and create a support system for your professional life.
  • Take the good and the bad. Distinguish between fact and opinion, objective and subjective. People will either like or dislike your posts and there is something to be learned from both.
  • Don’t be evil. Top influencers will have one thing in common, they use their influence for the greater good.
  • Be yourself.Impersonating others online is a crime so just be yourself. Share your knowledge, share your profession, share your passion, brand yourself. You don’t have to be an expert or industry icon to be a top influencer on SemiWiki.

    The goal of SemiWiki is to bring members of the semiconductor ecosystem together and to foster better collaboration in meeting the challenges of advanced semiconductor design and manufacturing. Members of the EDA, IP and foundry ecosystem will contribute meaningful content including wikis, blogs and discussion forums.

    “Our industry needs a site that facilitates real time, vendor neutral discussion among real users,” said Daniel Nenni, internationally recognized industry blogger and founder of the SemiWiki Project. “SemiWiki.com will provide our members with a connected community that promotes the open exchange of ideas, experiences and feedback.”

    About the SemiWiki Project
    The SemiWiki Project provides in-demand content for semiconductor design and manufacturing, facilitating peer-to-peer communications using Web 2.0 technologies. Daniel Nenni will be joined by industry bloggers Paul McLellan, Daniel Payne, Steve Moran, and Eric Esteve at SemiWiki.com.

    • Posted on

    The Looming IP Explosion

    The Looming IP Explosion
    by Steve Moran on 02-15-2011 at 10:58 am
    Categories: IP, Synopsys

    There has been a lot of talk about the fluid role of IP in semiconductor design. With the Synopsys acquisition of Virage Logic the playing field has tilted substantially in favor of Synopsys… or maybe not!

    At first glance this acquisition appears to be a huge threat to EDA and IP companies allowing Synopsys to “throw in” IP as a value added product/service. But this may be hasty thinking. There are many several reasons to use external IP but at the end of the day it is always an economic decision and that economic decision is made after looking at two sides of a single coin. In absolute terms, is it less expensive to buy rather than build? And which option represents the least amount of risk?

    In many cases the risk side of the coin is more important than cost. It might very well be, that a design team or a design manager comes to the conclusion that they “could” build an element in their design for less money than it would cost to acquire it. They might even conclude they could build a better (faster, smaller) device than the one being purchased. But, if purchasing IP allows them to conserve resources by allocating engineering resources to the secret sauce portions of their design it means they will get a lot more bang for their buck. It also turns the IP company into a financing mechanism, by pushing payment for that portion of the design down the road, in some cases pushing it out until actual production begins.

    In the short run, it might appear that getting your tools and IP from a single vendor reduces cost and risk. This might even be true looking at a single project, but over time and multiple projects the risk factor becomes huge. Going soup to nuts with a single vendor gives control of your whole design to an outside vendor who does not have the same goals you have. Their goal incentive is not to make your chips better or even to make your company more profitable, but rather to keep you as captive as possible. They have very little incentive to innovate and once you are deeply in their web, there is very little incentive to fix problems rapidly; after all where else can you go?

    The solution then becomes multiple IP vendors. It is a healthy long term strategy for both the individual companies and the industry as a whole. It ensures that IP will keep up with technology advancements and negotiation of financial terms on IP will happen on a more or less level playing field. As Eric Esteve and some subsequent posters pointed out in the Semiwiki.com forum discussion The IP Paradox the biggest challenge design managers face is sleuthing out the best IP and the most reliable partner.

    For these reasons I believe that you will see the role of IP to become more significant and why simiwiki will be an important part of that equation.

    Posted on

    Mentor Graphics Should Be Acquired or Sold: Carl Icahn

    Mentor Graphics Should Be Acquired or Sold: Carl Icahn
    by Daniel Nenni on 02-12-2011 at 5:42 pm
    Categories: EDA

    The big EDA news last week of course was the CNBC interview (HERE) with infamous corporate raider Carl Icahn. Carl is not happy with Mentor Executives, nor is Mentor investor Donald Drapkin who said, and I quote, “It’s just a sleepy company run like a country club”. Carl and Donald’s combined MENT investment is 20%+ so expect fireworks at the Mentor Graphics shareholder meeting on May 6[SUP]th[/SUP].

    Mentor Sleepy Company Country Club data points to ponder:

    [LIST=1]

  • G&A is about the same as CDNS’s, apples to apples. Synopsys is more of a pear than an apple.
  • Revenues AND market shares are increasing in a consolidating market.
  • From LinkedIn: Mentor Graphics has 35 new job opportunities!

  • Costs ARE being cut WITHOUT layoffs and other disruptive measures. Wally even flies economy. Seriously, he told me this over drinks. Mentor’s move to the former Avant! building last year both CUT costs and increased space. They even got rid of the creepy bedroom suite with a jacuzzi behind the CEO’s (Gerry Hsu’s) office.

    Here is my message to Carl and his corporate raiding friends:

    What in the hell are you thinking? Do you actually know what EDA is? Our market is shrinking, not growing. Since the beginning of time, inorganic growth (acquisitions) is the only way EDA thrives and even that is now threatened by the overly competitive nature of Synopsys, the lack of investment by the venture capital community, and now FPGA companies are buying EDA start-ups for premium revenue multiples (Xilinx recently bought AutoESL @ 50x revenue?)

    Listen Carl, the semiconductor design and manufacturing ecosystem is just that, an ecosystem. Disrupting Mentor in this fashion could upset the balance of nature and it could all come crashing down. Even if you are successful in the boardroom coup, who is going to buy Mentor Graphics? Even if you carve it up like a turkey.

    There are no competitors strong enough to buy Mentor’s most profitable turkey parts. Synopsys is the only EDA company with a bankroll large enough. Fortunately, Synopsys holds either the #1 or #2 market position in every semiconductor design segment so what is their motivation to buy a Mentor drumstick or wing? Synopsys also has an ego larger than EDA itself and has been competing head-to-head with Mentor since birth. Buying the Calibre franchise would be admitting DRC defeat and that is just not part of the Synopsys ultra competitive culture.

    What about Cadence? There is even worse history there. Remember when Cadence tried to buy Mentor and Mentor returned the favor by trying to buy Cadence? That was Cadence CEO Mike Fister’s Waterloo. Even if Cadence billionaire CEO Lip-Bu Tan could raise the money for Mentor turkey parts, the company integration would be a nightmare. Wrapping the Cadence culture around Mentor would not work.

    One corporate raidering possibility is a foundry buying Mentor parts. TSMC and GlobalFoundries have the money and competitive spirit to do so, but the top fabless semiconductor companies might not care for that at all. Bringing semiconductor design full circle with tools coming directly from the semiconductor manufacturers? Is that really what we want to do here? It is much more likely that GlobalFoundries buys the physical IP division of ARM for $1B+. Now that’s what I call collaboration!

    As a result of all this drama, Mentor has retained Goldman Sachs “to explore the company strategic options”. Hopefully this is just a play to silence Carl and friends, I really do not want Mentor dissected.

    Here is my message toMentor:

    Take over Cadence or Magma already! My Mentor/Cadence/Magma merger BLOG last year was THE most viewed blog of 2010 for a reason, people want it to happen. Synopsys is an EDA/IP MONOPOLY and something must be done! If any of you folks out there do not agree, look up the word delusional.

    REGISTER 4 EDA TECH FORUM HERE!

    • Posted on

    New ERC Tools Catch Design Errors

    New ERC Tools Catch Design Errors
    by glforte on 02-11-2011 at 2:18 pm
    Categories: EDA, Siemens EDA

    388 image001

    A growing number of reports highlight a class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must.By Matthew Hogan

    Today’s IC designs are complex. They contain vast arrays of features and functionality in addition to multiple power domains required to reduce power consumption and improve design efficiency. With so much going on, design verification plays an important role in assuring that your design does what you intended.Often, verification will include simulations (for functional compliance), and extensive physical verification (PV) checks to ensure that the IC has been implemented correctly, including DRC, LVS, DFM and others. A growing number of reports highlight a class of design errors that is difficult to check using more traditional methods, and can potentially affect a wide range of IC designs, especially where high reliability is a must.

    To address these types of design errors, electrical rule checking (ERC) has seen significant growth in recent years. Teams developing submicron, mixed-signal, or low-power devices used in mobile and other applications are particularly concerned about advanced ERC. This concern has lead to investments by circuit designers, CAD engineers, design project managers, verification engineers, and process modeling engineers to increase coverage, and by the EDA tool vendors to enable advanced checks and make describing the rules simpler. The investment has a large ROI because robust ERC reduces the number of die susceptible to catastrophic electrical failures during final testing, as well as premature failures in the field.

    Electrical rules are relatively complex, non-standard, and growing in number and type, creating a need for a highly flexible, user-configurable tool. ERCs are important, but particularly challenging in designs with multiple voltage domains and mixed analog/digital circuits, such as low-power devices targeting mobile and other battery-powered applications.

    Designs that incorporate multiple power domain checks are particularly susceptible to subtle design errors that are difficult to identify in the simulation space or with traditional PV techniques. Often these subtle errors don’t result in immediate part failure, but performance degradation over time. Effects such as Negative Bias Temperature Instability (NBTI) can lead to the threshold voltage of the PMOS transistors increasing over time, resulting in reduced switching speeds for logic gates [1] [2] [3], and Hot Carrier Injection (HCI), which alters the threshold voltage of NMOS devices over time [4]. Soft breakdown (SBD) [4] also contributes as a time-dependent failure mechanism, contributing to the degradation effects of gate oxide breakdown.

    Some electrical rule checks are based on the netlist and include looking for floating devices, nets, or pins, detecting thin gates connected to excessive voltages, checking for violations of the maximum allowed number of series pass gates, and finding issues related to level shifter designs. Other checks are performed using geometric layout information, such as net area ratios for antenna rules, floating wells, and minimum “hot” NWELL width.


    Topological ESD check:Device gates connected to I/O pads should be protected by resistor and turn-off MOS device.

    An important application of ERC is verifying that electrostatic discharge (ESD) protection circuits are in place wherever the device is vulnerable, whether those circuits are included in the schematic and netlist or not. To ensure a robust design, the ERC tool must go beyond simple schematic or netlist-to-layout verification and recognize where ESD protection elements are needed, based on combined information from the netlist and the layout topology.

    In multiple power domains, other precautions have to be considered. For example, IP reuse may require more robust rules to avoid device burnout at the system integration stage. This is particularly the case where an IP block is being re-targeted to a different process node or power domain [1]. The introduction of lower voltage power domains is also an area where IP reuse and the contribution to the overall reliability of the chip must be considered. Often, to attain lower voltage thresholds for lower power circuits, the oxide layer of a transistor is made thinner. While this has significant voltage and power benefits, there are areas of concern. One of these is when thin-oxide gates have paths to specific voltage rails. To avoid long term damage to the gate over a period of time, which results in performance degradation, the voltage rail must be carefully chosen. A previous implementation may have the gate tied at a voltage that is too high for the current use.

    Successful integration of physical IP blocks requires knowledge of the design hierarchy as well as the structure of voltage domains and cell voltage constraints. Design hierarchy also comes into play when one set of rules is applied to upper layer interconnects and pad frames, while different rules are applied between blocks crossing multiple power domains.

    In the figure below, we can see results from a check to verify that a signal net from one power domain does not directly cross into another. In this case, we would probably expect a level shifter or some other protection circuit to allow the safe passage of a signal from one power domain to another.


    Topological ERC example that needs circuit identification programmable entry. Advanced ERC: Serially connected gates cannot be on different supplies or grounds.

    As ERC becomes more critical to producing a reliable product, designers and engineers are constantly discovering new checks that they would like to make during verification. These checks are based on their accumulated knowledge and best practices of design groups; thus, there is no “standard” set of checks. Consequently, it is crucial that an ERC tool be easily programmable, allowing users to adapt it quickly to new checks as they become needed.

    As an example of advanced ERC, the circuit below shows PMOS and NMOS thin-oxide gates with direct and indirect connections to power the domains VDD2 and VSS2. An indirect connection may be through another transistor, diode, resistor, or other circuit elements. These connections often form the basis of “missed” paths that are not readily identified during design reviews. This is particularly true if the indirect path is through a circuit elsewhere in the design hierarchy that is not obvious. The local power connections in the sub-circuit itself (VDD/VSS) are seen in the context of the larger design. The external connections to an otherwise verified IP block must be evaluated.

    To show how designers can use new ERC verification tools we provide an example check based on Mentor Graphics’ Calibre® PERC product, which can be used to find design errors not identified by traditional PV tools. Typically Calibre PERC is used in combination with Calibre nmLVS allowing users to run multiple electrical rule checks independently or together, using either standard rules from the foundry, or their own custom rules. Users can insert electrical rule checks into their design flow with Calibre PERC as part of an integrated Calibre platform for cell, block, and full-chip verification. Combining rules expressed in SVRF and the TCL-based TVF language across all applications provides users with flexibility to meet the specific and evolving needs of their design teams, while ensuring compatibility with all foundries.

    To identify thin-oxide gates at risk, designers could define a check in Calibre PERC expressed in pseudo code here for simplicity:
    1) Identify power domains in the design
    2) Identify which power domains are “not safe” for thin-oxide gates
    3) Identify the specific device types and subtypes that corresponding to thin oxide MOS devices
    4) Check the related “source”, “drain”, or “bulk” pin connection on these thin-oxide MOS devices to power domains
    a) Evaluate both direct and indirect paths
    b) Flag an error for this-oxide MOS connections that are to “not safe” power domains

    In complex systems, it is not uncommon to have multiple power domains, which require complex design rules to determine which domains are safe, and under what conditions.


    Thin-oxide gates with direct and indirect paths to VDD2/VSS2. These connections are made outside the sub-circuit.

    Verification of bulk pin connectivity is particularly import for determining if a circuit is susceptible to these time related reliability issues. As shown below, an incorrect bulk connection may make this PMOS gate vulnerable to NBTI due to a high bulk voltage.



    A Thin-oxide PMOS (Model: mos_lv) with a path to high voltage may lead to NBTI susceptibility

    To learn more about reliability checking, download the white paper “Addressing Reliability and Circuit Verification Challenges with Calibre® PERC“. Also, visit my personal blog at http://blogs.mentor.com/matthew_hogan/.

    References
    [1] Hamed Abrishami, et. al., “NBTI-Aware Flip-Flop Characterization and Design”, GLSVLSI’08, May 4–6, 2008
    [2] B.C. Paul, K. Kang, H. Kuflouglu, M. A. Alam and K. Roy, “Impact of NBTI on the temporal performance degradation of digital circuits,” Electron Device Letter, vol. 26, no. 8, pp. 560-562, Aug. 2005.
    [3] Hong Luo, et. al., “Modeling of PMOS NBTI Effect Considering Temperature Variation”, 8th International Symposium on Quality Electronic Design (ISQED’07)
    [4] Jin Qin, et. al., “SRAM Stability Analysis Considering Gate Oxide SBD, NBTI and HCI”, 2007 IIRW FINAL REPORT

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    EDA and Wall Street

    EDA and Wall Street
    by Paul McLellan on 02-11-2011 at 1:25 pm
    Categories: EDA

    Good news in a way: Merrill Lynch (or Bank of America Merrill Lynch as I suppose we have to get used to calling them) have re-started coverage of EDA with a 20 page report on the industry, much of which is spent on explaining how the industry segments out and who is strong in which segments, stuff that most people reading this site already know.

    Their top attraction is Cadence (buy rating, with a price target of $13), followed by Synopsys (buy rating, with a price target of $35) and then Mentor (neutral, with a price target of $15).

    My comments: Synopsys is clearly the EDA leader but as the largest company it is hard for them to grow faster than the overal EDA market. Cadence is in year 3 of a transition and the interesting thing to watch will be how much business they have in year 3 because historically these transitions risk doing 3 years of business in 2 years leaving thin pickings for the 3rd year (and so a temptation to do some non-ratable business to make the number).

    Mentor, for those of you not following along at home, has Carl Icahn nipping at their heels. He has taken a 15% stake in the company and, last week, on CNBC accused them of being a country-club and that they should be sold or broken up. At the very least it should be a good spectator sport. The Merrill Lynch report doesn’t mention Icahn and the potential upside/risk.

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