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As I have mentioned before, Cliosoft is the biggest little company in EDA with the most talked about products on SemiWiki. At DAC, ClioSoft will introduce integrated SOS design management (DM) solutions providing ...

Just as a disciplined flow is crucial in design – you would not think of starting Place and Route before writing the RTL – a well-defined process is key to successful customer meetings. Have you ever come away from a meeting feeling:

• That your customer was much less enthusiastic than he or she should have been?
• That things did not really move forward?
• That

...

My 8 years as an IC circuit designer were at the transistor-level, so if that interests you as well then consider what there is to see from Cadence at DAC this year. IC design technology is changing quickly, so keeping up to date is important for your job security and continual education goals.



Here's what I would recommend attending at Cadence in Booth #2214: ...

Last week I talked to Eileen You of Samsung-SSI to get a preview on what they will be talking about at Apache's customer theater at DAC. Their presentation is titledThe Life of PI: SoC Power Integrity from Early Estimation to Design Sign-off. The 'PI' stands for Power Integrity.

Samsung-SSI's operations are 5 years old and have grown ...

With DAC approaching, it is a good time for both EDA companies and their customers to take a deeper look at the evaluation process of EDA tools, and how EDA companies position their tools. I hope this is useful for customers and vendors alike.

When it comes to positioning EDA tools in the marketplace there are really only three meaningful measurement ...

Today Cadence announced Tempus, their new timing signoff solution. This has been in development for at least a couple of years and has been built from the ground up to be massively parallelized. Not just that different corners can be run in parallel (which is basically straightforward) but that large designs can be partitioned across multiple servers too. So Tempus is ...

In a complex semiconductor market today, characterized by ever increasing design size and complexity, long design cycle, rapid technological advancement, intense competition, pricing pressure, small window of opportunity, development and cross-functional teams spread across the globe and multiple design partners including several IP vendors for a single SoC, it’s essential for a corporate to identify key strategies for its sustainable competitive advantage. Among ...

It goes without saying that registers play a vital role in designing any ASIC, FPGA, SoC or System. In today’s world, while designing SoC with multiple IPs and functionalities on the same chip, registers stay at the heart of the design right from the architectural level as they are used for key interfaces between hardware, software, firmware and even IPs. Register buses ...

Invarian is an interesting EDA company that sees a niche market opening in the physical verification space. There are a number of converging factors driving this opportunity. Electromigration and voltage-drop for full-chip analysis demands SPICE level accuracy with fast runtimes. Invarian solves that problem with macro modeling and a parallel architecture. Not only are runtimes greatly reduced, but accuracy is improved by incorporating ...