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TSMC Unveils First Ever AMS Reference Flow!

TSMC Unveils First Ever AMS Reference Flow!
by Daniel Nenni on 06-08-2010 at 9:17 pm
Categories: EDA, Foundries, TSMC

As a quick follow-up to my blog TSMC Extends Open Innovation Platform, TSMC today announced the Analog/Mixed Signal Reference Flow 1.0., another key collaborative component of TSMC’s Open Innovation Platform™.

The TSMC AMS Design Flow 1.0’s design package is integrated seamlessly on top of the 28nm interoperable process design kit (iPDK) and OpenAccess database and includes:

  • Industry-first layout-dependent effect (LDE) aware design methodology
  • TSMC-specific LDE engine
  • Complete DFM-aware analog layout guideline and checker utility
  • Advanced analog base cell (ABC) design
  • Comprehensive design configuration management environment
  • A robust front-end design and simulation platform for the analysis of design sensitivity, yield, multi process corners, noise effect, IR drop and electromigration (EM) issues.
  • Constraint-driven analog placement and routing technology for fast layout prototyping, semi-automatic rule-driven layout assistance, and a demonstration of a PLL system design budgeting and loop filter layout synthesis capability.
  • A Physical verification flow that includes accurate 3D field solver based extraction with intelligent RC reduction, and full DRC/LVS sign-off and dummy pattern insertion and extraction.


“TSMC’s Open Innovation Platformdeliverscomprehensive and innovative designtechnology services that remove advanced technology adoption barriers. Ithelpslower design costs andimprovestime-to-market,” said Dr Fu-Chieh Hsu, Vice President of Design Technology Platform and Deputy Head of Research & Development. “TheOpen Innovation Platform willnow beginaddressing system-level design’s cost and complexity and enable packaging of entire electronic systems onto multi-chip packages.”

The TSMC AMS Reference Flow 1.0 is developed and fully validated in collaboration with multiple EDA partners including:

  • Apache Design Solutions
  • Berkeley Design Automation
  • Cadence
  • Ciranova
  • EdXact
  • Mentor Graphics
  • Magma Design Automation, Mentor
  • Pyxis Technology
  • Silicon Frontline
  • SpringSoft
  • Solido Design Automation
  • Synopsys

“The design ecosystem must move beyond its current bounds and embrace the systems- level challenges that are at the heart of every design consideration. The Open Innovation Platformbegan setting the standard for ecosystem collaboration two years ago. TSMCcontinues to answer the market’s calland will build that same collaborative spirit on a system-level basis,” explained S.T. Juang, senior director, Design Infrastructure Marketing at TSMC.

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TSMC Extends Open Innovation Platform

TSMC Extends Open Innovation Platform
by Daniel Nenni on 06-07-2010 at 9:24 pm
Categories: EDA, Foundries, TSMC

TSMC today extended one of the most effective semiconductor design enablement initiatives the semiconductor world has ever seen, the Open Innovation Platform (OIP). Morris Chang coined the term “OIP” himself in 2008, but the effort itself is 10+ years old with a collective cost > .5B$. My other blogs on topic include: TSMC OIP vs CDNS OIP Analysis, TSMC Open Innovation Platform Explained, andTSMC iPDK Debate.

The Open Innovation Platform’s global EcosystemAllianceprograms have grown to include 30 EDA partners, 38 IP partners, 23DesignCenterAlliance(DCA) partners, and 9 Value Chain Aggregator (VCA) partners. All partners participate in one or more of the Open Innovation Platform collaboration programs. TSMC also begins to work collaboratively with industry organizations, such as IPL Alliance and Si2, to promote the interoperability standards based on TSMC interoperable EDA formats.

Impressive! But is TSMC the #1 semiconductor foundry because of their design enablement activities? Or is this design enablement initiative #1 because TSMC is the industry leading foundry?

I like the executive quotes included in the official TSMC press release, they speak volumes:

“The electronic design community is embracing the EDA360 vision to enable fastest approach from concept to consumer and together with IP suppliers, EDA vendors and silicon manufacturers, we have diligently collaborated to build a cohesive path for designers,” said Lip-Bu Tan, president and chief executive officer, Cadence. “TSMC’s Open Innovation Platform is a proven, integral part of this path. TSMC’s Open Innovation Platform will now make significant advancements in low-power, mixed-signal, system-level and 3D-IC design to enable further productivity improvements that our mutual customers need.”


News flash: The semiconductor community has NOT embraced EDA360. Just because you keep saying something over and over does not make it true, especially when it is self serving. I have spoken to dozens of semiconductor industry professionals and the foregone conclusion is that EDA360 is aNothing Burger!


“Going forward,Mentor and TSMC are developing complete solutions for the TSMC design ecosystem, ” said Walden C. Rhines, Chairman and CEO,Mentor Graphics. “The TSMC OIP effort is not just words — theMentor Track in Reference Flow 11.0, and the co-developed iDRC and iLVS languages, are real usable results.”

I like Wally’s style here, say more with less. My lunch with Wally is next week so hopefully I can get him to say more on the subject.

“Collaboration across the entire design eco-system — customers, foundries, IP and EDA suppliers — is critical for lower design risk and cost, better power and performance, and customer differentiation, ” said Aart de Geus, Chairman and CEO, Synopsys. “The new technologies in this phase of TSMC OIP, such as system-level design, analog/mixed-signal (AMS) design and thru-silicon-via, bring key solutions to speed System-to-IC realization.”

Aart is pointing out that the TSMC OIP not only competes directly with the Cadence EDA360 OIP, it plays to the strengths of Synopsys. In fact, the EDA360 Manifesto highlights the strengths of both Mentor and Synopsys: System Realization, SoC Realization, and Silicon Realization. Synopsys and Mentor own EDA360.

The most interesting quote, or lack there of, is from Magma CEO Rajeev Madhaven. Seriously, Magma is an integral part of the TSMC OIP expansion but no quote from Rajeev? I would like to think it is a conspiracy against Magma by the top 3 EDA CEO’s as a result of Magma’s business practices, but I’m sure there is a far less interesting explanation.

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TSMC versus GlobalFoundries: Semiconductor Design Enablement!

TSMC versus GlobalFoundries: Semiconductor Design Enablement!
by Daniel Nenni on 06-01-2010 at 9:00 pm
Categories: EDA, Foundries, GlobalFoundries, IP, TSMC


As mentioned in previous blogs, design enablement is a key enabler to fabless semiconductor design and manufacture, without question. The purpose of this blog (in 500 words) is to compare and contrast two very different design enablement strategies and engage the semiconductor community in a meaningful discussion.

The GlobalFoundry strategy is straight forward so let’s start there. GFI is partnering with leading design enablement companies to advance semiconductor design at the 28nm node. GFI is committed to becoming the FIRST SOURCE for 28nm, competing directly with TSMC, while other foundries have in the past offered “T” like processes for 2[SUP]nd[/SUP] and 3[SUP]rd[/SUP] source manufacturing strategies (UMC, Chartered Semi, SMIC).

GFI is taking the sniper approach to partnerships rather than the traditional foundry business model of working with everybody (EDA, Semi IP, and Fabless ASIC companies). GFI has stated very clearly that they will not compete with partners and will in fact invest financially in the design enablement industry by purchasing products and services from said partners.

On the EDA side it is Synopsys for digital design, Cadence for AMS design, and Mentor for Verification and DFM. IP is ARM, Synopsys, Virage, and a collection of smaller companies. ASIC services is eSilicon, Open-Silicon, and SOCLE. Mask services is DNP, Hoya, and Tappan. I have heard that GFI has already cut millions of dollars of purchase orders with EDA and Semi IP companies. It would not surprise me at all if GFI is now the #1 customer of said partners so look for more GFI specific EDA tools, IP, and services in the coming quarters.

ARM And GLOBALFOUNDRIES Establish A Strategic Partnership To Enable Application-Optimized SOC Products On 28NM Highk Metal Gate (HKMG) Process

GLOBALFOUNDRIES Releases Industry’s First Silicon-Validated Library for Pattern-Based SoC DFM Verification at 28nm and Below

ARM, IBM, Samsung, GLOBALFOUNDRIES and Synopsys Announce Delivery of 32/28nm HKMG Vertically Optimized Design Platform

TSMC on the other hand has, over the last 10 years, implemented the shotgun approach to partnerships (TSMC Open Innovation Platform) which includes a “co-opetition” clause. Shotgun approach means TSMC works with EDA companies big and small, qualifying dozens of EDA tools and hundreds of silicon proven IP. Co-opetition means cooperative competition with partners via TSMC’s internal: IP development, mask services, and ASIC design services (Global Unichip Corp).

Two very different strategies, two very different outcomes?

Will GFI succeed in getting the 28nm 1[SUP]st[/SUP] source business? If 80% of foundry silicon is shipped by the top 20 fabless semiconductor companies is that your target market? Those top 20 companies are experts in semiconductor design enablement and do not need help with off the shelf tools and IP, what value can GFI really add there? And what about the 80% of the companies that ship 20% of the silicon? Can they really be ignored when one of them could easily be the next Cisco or Broadcom? What do you think?

Will TSMC invest more in the design enablement industry and compete less with partners? Can TSMC continue to take on all customers, big profit margin and small? TSMC has spent 100’s of millions of dollars on Semi IP, PDKs, and reference flows. Can that amount of spending continue to be justified? How do you think this will play out?

Answers to these questions will hopefully come in the form of comments so please share your opinions. The foundries and thousands of other people read my blog so lets hear it. In fact, more people read my blog than attended #47DAC!

Next week’s blog “TSMC versus GlobalFoundries: Semiconductor Design Enablement! II” will focus on feedback from TSMC and GFI executives. See you on Monday!

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Semiconductor Capacity Shortages 2010

Semiconductor Capacity Shortages 2010
by Daniel Nenni on 05-31-2010 at 7:25 pm
Categories: Semiconductor Intelligence, Semiconductor Services

In a previous blog, Black Friday and the Predicted Semiconductor Shortages, I reported that total semiconductor manufacturing capacity is shrinking as older fabs close and new ones ramp up even slower than expected, resulting in a record reduction of total wafer capacity and silicon allocation starting in 2010. DRAM shortages and price hikes are already in place and the leading foundries are expecting a 20%+ growth rate and predicting full (95%+) capacity by the end of 2010.

Semiconductor Intelligence did a nice report, based on the Q4 2009 Semiconductor International Capacity Statistics, also predicting semiconductor shortages by the 2[SUP]nd[/SUP] half of 2010. Semiconductor Intelligence is actually a guy named Bill Jewel, a 27 year semiconductor veteran from Texas Instruments. It is always nice to read semiconductor reports from a guy with actual semiconductor experience.

“IC wafer production (or utilized capacity) should outgrow total capacity throughout 2010, with 4Q 2010 production slightly higher than the peak levels in 2008. As a result, utilization will continue to rise, passing 95% by 4Q 2010. Utilization has exceeded 95% only 3 times in the 16 year history of SICAS data: 96.0% in 2[SUP]nd[/SUP] half 1995, 96.4% in 3Q 2000, and 95.4% in 2Q 2004. 95% to 96% appears to be a practical limit indicating the industry is running at full capacity.”

While semiconductor capital spending was at an all time low in 2008 and again in 2009, 2010 looks to break records with both IDMs and Foundries, and of course the IDMs that pretend to be foundries.
Ranking Capital Spending

[LIST=1]

  • Samsung US$6B
  • Intel US$5.3B
  • TSMC US$4.8B
  • GlobalFoundries US$2.5B
  • Hynix US$2B
  • Toshiba US$1.9B
  • Micron US$1.7B
  • UMC US$1.5B
  • Nanya US$1B
  • Elpida US$1B
    Unfortunately placing orders for semiconductor manufacturing equipment and actually taking delivery of said equipment are two very different things. Process ramping problems at 40nm also delayed capacity expansion plans as does me visiting Taiwan (natural disasters).

    The Global Semiconductor Monthly Report by Future Horizons also supports the strong IC recovery mantra that I have been chanting since my blog started early last year. Malcolm Penn, who has 139 years of semiconductor experience (he doesn’t look a day over 90!), has upped his forecast to 30%+ IC revenue growth in 2010 and it could be as much as 40%. If a normally quiet first half is this strong, the 2[SUP]nd[/SUP] half of 2010 could be full of upside surprises.

    In his report Malcolm also agrees with my semiconductor capacity shortage cry illustrated with a myriad of colorful graphs. The majority of the red line 300mm capacity is 65/40nm, which will likely see allocation before the year is out.
    Semiconductor revenue growth projections for 2010:

    • Gartner: 19.9%
    • iSuppli: 21.5%
    • Morris Chang (TSMC) 22%
    • Semico Research: 22.0%
    • Semiconductor Intelligence forecast 25%
    • IC Insights 27.0%
    • Future Horizons 30%

    If Semiconductor capacity does not significantly increase this year and next, demand will clearly outpace supply and we will see manufacturing utilization rates comparable to the boom times of 1995, 2000, and 2004. The supply and demand economic model illustrates that in a competitive market, price will equalize the quantity demanded by consumers, and the quantity supplied by producers, resulting in an economic equilibrium of price and quantity. Driven by the mobile internet market, semiconductors represent an ultra competitive market so expect a significant equilibrium up-shift in regards to pricing.

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TSMC OIP vs CDNS OIP Analysis

TSMC OIP vs CDNS OIP Analysis
by Daniel Nenni on 05-28-2010 at 9:04 pm
Categories: EDA, Foundries, TSMC

Launched in April 2008, the TSMC OIP initiative is a collaborative strategy aimed at breaking down the barriers of semiconductor design enablement in order to reduce waste and increase the profitability of the industry as a whole.

The TSMC Open Innovation Platform promotes timeliness-driven innovation amongst the semiconductor design community, its ecosystem partners and TSMC’s IP, design implementation and DFM capabilities, process technology and backend services. The Open Innovation Platform™ includes a set of ecosystem interfaces and collaborative components initiated and supported by TSMC that efficiently empowers innovation throughout the supply chain and enables the creation and sharing of newly created revenue and profitability.

The TSMC OIP targets include the following areas of inefficiencies:

[LIST=1]

  • PDKs: the iPDK standard is innovation driven versus format driven.
  • EDA Reference Flows and tool qualification, verified design sign-off flows.
  • TSMC IP portal: documenting silicon proven IP from both TSMC and commercial IP vendors such as Virage Logic.
  • TSMC collaborative services.The annual TSMC OIP conferences are stocked with top semiconductor, EDA, and IP executives from around the world. The keynotes, panels, and discussions are highly interactive, the format and content is truly collaborative and exactly what our industry needs to scale and move forward in a profitable manner.

    A new entry to this format is the Cadence Open Integration Platform launched inside the infamous EDA360 Manifesto. As they say, identify theft is the sincerest form of flattery:

    Cadence Design Systems, Inc. (NASDAQ: CDNS), the global leader in EDA360, today announced the Cadence Open Integration Platform, a platform that significantly reduces SoC development costs, improves quality and accelerates production schedules. A key pillar in support of its EDA360 vision for next-generation application-driven development, the Cadence Open Integration Platform comprises integration-optimized IP from the company and its ecosystem participants…

    The goal of both OIP’s is obvious, to reduce waste within the semiconductor design and manufacture process. People in this industry are accustomed to waste, business as usual, so this is a significant challenge! A former co-worker, Jack Harding CEO of eSilicon, estimates a 20% SoC design waste due to inefficiencies including lack of process node design experience. I say it is closer to 30% if you include the SoC mortality rate. 20-30% of the $50-100M SoC “realization” cost is a significant amount, especially if you are borrowing the money from a VC.
    The result of my expert analysis in the case of TSMC OIP versus CDNS OPI is based on the definition of the word:

    col·lab·o·ra·tion    –noun

    1. the act or process of collaborating.

    2. a product resulting from collaboration: This dictionary is a collaboration of many minds.

    TSMC follows the academic definition as the key to the fabless semiconductor design and manufacturing business is collaboration. Transforming a closed (IDM) design and manufacture process into a truly open semiconductor foundry business is an amazing thing and TSMC clearly has earned the title “Global Leader in Fabless Semiconductor Design and Manufacture”.
    CDNS brings a new definition to the word collaboration by alienating (opposite of collaborating) key partners in the ecosystem:

    [LIST=1]

  • Process pioneering foundries and semiconductor manufacturing equipment companies (EDA360 says new process nodes are scary so you should stay at older nodes as long as possible.)
  • EDA and IP Bretheren. (Cadence is the self appointed “Global Leader of EDA360”, which is nothing more than the repackaging of existing technology with a big public relations bow on it.)
  • Customers. ( Is this not deja vu of the arrogant behavior during the Cadence Fister/Intel era? Ditching DAC, cutting partner programs, etc…)
    In the hands of the EDA Consortium (EDAC), EDA360 would be a brilliant blueprint for the EDA industry and could easily replace “Where Electronics Begins”. Unfortunately, in the hands of Cadence it will not. My bet is that CDNS EDA360 will in fact be John Bruggeman’s Waterloo and CDNS OIP will be renamed or will die a silent death. Just my opinion of course, but I am the Global Leader of Independent Semiconductor Bloggers.
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450mm Semiconductor Manufacturing Debate

450mm Semiconductor Manufacturing Debate
by Daniel Nenni on 05-23-2010 at 2:39 pm
Categories: Foundries, TSMC


This blog posting is sponsored by EVA airlines, as I’m in the EVA executive lounge eating free food (I blog for food). “Fly EVA, the lesser of evils for Taiwan air travel!” EVA Air has a perfect safety record in 9 years of operation, China Air on the other hand has the worst safety record in the industry!

This blog was inspired by one of the longest, most spirited discussions I have read on a LinkedIn semiconductor group. A question posted on the Semiconductor Professionals Group five months ago, starting with a simple question, “Any status of 450mm? Who will be adopting first?”. It is followed by 160+ comments from semiconductor experts around the world.

TSMC, Intel, Toshiba, and Samsung all support the transition to 450mm citing both important technological advancements as well as significant capacity increases to meet the needs of future smartphone users around the world. One 450mm wafer should yield more than twice as much compared to today’s 300mm, and well over four times the number from yesterday’s 200mm.

Unfortunately, the semiconductor equipment manufacturers, the enablers of 450mm wafers, lost more than $1B and released 30%-40% of their workforces in 2009. Once scheduled for a 2012 launch, the transition to 450mm wafers has been delayed due to the financial meltdown. But with the current semiconductor industry upswing with foundries like TSMC and UMC operating at maximum capacity, the 450mm debate continues.
The debate about 450mm really boils down to: Will 450mm increase total capacity while reducing manufacturing costs? And is 450mm the best way to accomplish this?

According to Thomas Sonderman, Vice President of manufacturing systems and technology at GlobalFoundries:

“The rush to 450mm suggests a lack of ideas for improving fab productivity. At GlobalFoundries, we see a tremendous amount of headroom left in the 300mm process. We are tapping our expertise in lean manufacturing to extend the lifecycle of the industry’s current 300mm investments, and we are investing more than $4 billion in a new, state-of-the-art 300mm fab in upstate New York because we are confident in our ability to get the most out of this technology generation.”

The key to GLOBALFOUNDRIES “lean manufacturing” is a model based on highly automated decision-making called Automated Precision Manufacturing (APM). APM was a key technology that enabled AMD to compete as an IDM, which GlobalFoundries is now offering to a broader base of customers as a foundry.

According to Jack Sun, Vice President, Research and Development and Chief Technology Officer at TSMC:

“A move to 450mm is important for cost reduction and I believe it’s going to happen. The device manufacturers and governments all have to pitch in and contribute to the effort. People will find a way to invest so that we can deliver 450mm. Before the credit crunch, the target was 2012. It has moved out a couple of years, it has pushed out to the middle of this decade.”
In the early days of semiconductor, the device manufacturers themselves produced the required tools and equipment. That could easily come full circle with 450mm. With a limited amount of potential customers and under staffed and under funded semiconductor manufacturing equipment companies, Intel, Samsung, TSMC, and Toshiba, may be forced to develop 450mm manufacturing tools and machinery. TSMC already has 450nm enabling equipment in-house for R&D, alpha, and beta testing. Intel, Toshiba and Samsung may have internal 450mm development activities as well.

According to Daniel Nenni, famed semiconductor blogger:

“450mm manufacturing capabilities will separate the men from the boys. If Samsung (Korea) is the only memory manufacture with 450mm capabilities, Micron (USA), Toshiba and Elpida (Japan), and Taiwan Memory, will be dog food. If TSMC (Taiwan) is the only foundry with 450mm manufacturing capabilities, TSMC will be the Great Dane of the semiconductor world!”

lang: en_US

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2010 Semiconductor Foundry Update: Consolidation!

2010 Semiconductor Foundry Update: Consolidation!
by Daniel Nenni on 05-16-2010 at 6:46 pm
Categories: Foundries, GlobalFoundries, TSMC

It has been an interesting month in the semiconductor business. Record revenues, profits, aggressive expansion plans, something we have not seen before and may not see again. Let’s start in Taiwan then move to Silicon Valley, Upstate New York, China, and Korea, with a look at: financials, capacity, and consolidation.

TSMC and UMC both posted record sales and profits exceeding even the optimistic. The top semiconductor companies followed suit which prompted the often quoted market researcher iSuppli to predict the chip industry is set for its highest annual growth in a decade: Semiconductor sales will climb to an all-time high of $300 billion in 2010, up from $230 billion last year. The previous sales record was $274 billion in 2007. According to iSupply, the last time semiconductor sales increased at such a rate was in 2000 when sales grew at 36.7%.

Though the semiconductor industry is estimated to grow 30%+ in 2010, TSMC and the foundry business is heading for much higher growth. Both fabless and fabbed semiconductor companies are reserving capacity with TSMC to ensure their SoCs hit the market window, compounding the wafer allocation problem that started earlier this year.

Capacity of course is key to semiconductor riches and will play the most significant role in who will deliver silicon to future generations. During my last visit to Taiwan, friends from TSMC briefed me on the Gigafab concept to which TSMC has publicly committed billions of dollars in capital expenses. A third $3B+ Gigafab will be constructed in the central Taiwanese city of Taichung and is slated to go online by the end of 2011. Nobody brings a new fab online faster and cheaper than TSMC, believe it.

While capitol spending is the key indicator of organic capacity growth, inorganic growth is also high on the foundry agenda: GlobalFoundry’s acquisition of Chartered Semiconductor, UMC’s investment in China’s He Jian, and TSMC’s equity stake in SMIC. GlobalFoundries clearly understands that capacity is everything in the foundry business, also understanding that they are no match for TSMC in a Fab building contest. Look for more inorganic growth for GlobalFoundries.

One of the leading semiconductor crystal ball sites predicted that there will only be three semiconductor manufacturers producing wafers below 20nm. It has been repeated so many times I don’t remember where it came from but now some view it as a truth. Today there are six foundries pushing Gordon Moore’s Empirical Observation: TSMC, UMC, GlobalFoundries, SMIC, Samsung, and IBM. That could certainly consolidate down to three: TSMC, Samsung, and GlobalFoundries.

While capitol spending is the key indicator of organic capacity growth, inorganic growth is also high on the foundry agenda: GlobalFoundry’s acquisition of Chartered Semiconductor, UMC’s investment in China’s He Jian, and TSMC’s equity stake in SMIC. GlobalFoundries clearly understands that capacity is everything in the foundry business, also understanding that they are no match for TSMC in a Fab building contest. Look for more inorganic growth for GlobalFoundries.

One of the leading semiconductor crystal ball sites predicted that there will only be three semiconductor manufacturers producing wafers below 20nm. It has been repeated so many times I don’t remember where it came from but now some view it as a truth. Today there are six foundries pushing Gordon Moore’s Empirical Observation: TSMC, UMC, GlobalFoundries, SMIC, Samsung, and IBM. That could certainly consolidate down to three: TSMC, Samsung, and GlobalFoundries.

lang: en_US

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Cadence EDA360 Redux!

Cadence EDA360 Redux!
by Daniel Nenni on 05-09-2010 at 9:02 pm
Categories: Cadence, EDA

“Cadence Design Systems, Inc. (NASDAQ: CDNS), the global leader in EDA360………”

Of course, why wouldn’t Cadence be the global leader in something they just made up? As a follow-up to my yawningly successful blog Cadence EDA360 Manifesto:

One of the problems I have with EDA360 is the fear, uncertainty, and doubt (FUD) it attempts in the paragraph “from creators to integrators”. It argues that maintaining Moore’s law depends on “a continuing migration to lower process nodes to gain performance, power, and cost advantages”. It further claims that Moore’s law hit a wall due to rising development costs?

Figure 1 shows development costs for advanced process nodes. Look at 32nm: the cost is $100M, looks daunting, but actually 50-60% is software – which is completely not related to a new semiconductor process. The next ingredient: Architecture, design and verification account for another 25-30%. This is again not related to process technology or Moore’s law.

The only part that is influenced by a new process is the implementation and manufacturing which accounts to only about 10-15% of the cost. So given the total cost, it is clear that the process technology’s contribution to the cost increase is minor. So this graph and explanation fail to explain the issue and how it is related to a semiconductor process technology. It is FUD against the foundries and the advantages of moving to new process nodes.

A few large semiconductor companies will continue to followMoore’s Law and design the fastest, most complex, and smallest ICs. These innovators are design creators. While they will provide a crucial role in the industry, only a handful of such companies can exist.

Clearly there must be a way to be successful at lower volumes or with less advanced silicon. Consumer demand is setting the stage for new kinds of connected devices we haven’t even imagined yet. If electronic design is only available to a handful of creators who can only make money by shipping 80 million units, few of these devices will be built and the diversity that consumers want will not materialize.

I absolutely agree with the concept of the increased role of integration, but my conclusion is that there is no reason not to use the latest semiconductor process technology, on the contrary, it can be used to integrate previously separate parts into one chip using the same higher level software, architecture, etc. thereby accomplishing lower cost, lower system footprint, lower power, etc.

This way, fabless semiconductor companies can take advantage of the latest process technology at a relatively low incremental cost, as they don’t need to invest again in developing new architecture, new software etc., and they get to reduce the risk and time to market for this new integrated product.

The role of the EDA industry is semiconductor design enablement through design reuse, automated tools and flows, which includes process migration. If I’m wrong on this please let me know, but my conclusion on this point: Cadence EDA360 not only insults the other EDA companies that lead the market segments mentioned (design, implement, verify), it also alienates the foundries and the push for advanced technologies, in addition to the fabless companies that are today successfully designing to those advanced process nodes.

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Cadence EDA360 Manifesto

Cadence EDA360 Manifesto
by Daniel Nenni on 05-02-2010 at 8:54 pm
Categories: Cadence, EDA

EDA360 is said to be a blueprint or high-level vision for the EDA industry and not a Cadence specific document, based on the challenges that customers are experiencing. What EDA36o really is, is a manifesto, a public declaration of intentions, opinions, objectives, or motives, issued by a specific organization. The question is: EDA360, will it be an industry transformation catalyst or a failed public relations campaign?

Unfortunately the word manifesto will forever be negated by the Unabomber’s (Theodore John Kaczynski) rambling 35,000 word manifesto against modern society “Industrial Society and Its Future”, which brought to conclusion one of the FBI’s most costly investigations. Mr Kaczynski’s brother recognized the writing style and arguments and informed the FBI of Ted’s wilderness whereabouts. It is my hope that John Bruggeman and EDA360 can change the perception of a manifesto and not reinforce it.
To understand a manifesto, first you must research the author. I’m a bit surprised that John Bruggeman has not one but two LinkedIn profiles and neither is even close to being complete, so my research ended there. John Blogs and Twitters but does not do LinkedIn? It is concerning if a Chief Marketing Officer does not really get Social Media. John’s Twitter and Blog started after he joined Cadence so maybe he is still ramping up, I hope he is a quick study. Theodore John Kaczynski doesn’t have a completed LinkedIn profile either but he does have a very detailed Wiki page.

The manifesto itself is 32 pages long and can be found here along with an overview, John Bruggeman intro video, and an EDA360 news aggregator. A Richard Goering EDA360 Q&A is here and the Cadence official EDA360 press release can be found here. The formal Cadence description:
The Cadence EDA360 Vision Paper is a comprehensive call-to-action for the electronics industry to address a disruptive transformation—a shift in focus from design creation to integration. Drawing upon a collaborative ecosystem, EDA360 enables the development of complete hardware/software platforms that are application-ready. While traditional EDA concentrates on silicon design creation, EDA360 responds to the needs of both design creators and integrators. It helps creators close the “productivity gap” through improved approaches to design, verification, and implementation. EDA360 also helps integrators close the “profitability gap” by providing new capabilities for IP creation, selection, and integration, and for system optimization.

The main goal of any manifesto is to elicit discussion and from what I have seen so far there will be plenty of it on EDA360. A Cadence PR person contacted me a couple weeks ago and has scheduled a 30 minute discussion between John Bruggeman and myself for May 10th. Hopefully I can make some sense out of all this and come up with some relevant questions for John by then as to not embarrass myself. Normally I require lunch or some sort of meal to blog, as a qualifier as to how serious they are (I blog for food). On this occasion however, I will give Cadence the benefit of the doubt.

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Moore’s (Empirical Observation) Law!

Moore’s (Empirical Observation) Law!
by Daniel Nenni on 04-18-2010 at 10:49 pm
Categories: EDA, General, Siemens EDA

“What would you like your legacy to the world to be? Anything but Moore’s Law!”

 

Gordon Moore, May 2008.

Moore slightly altered the formulation of the law over time, bolstering the perceived accuracy of Moore’s law in retrospect. Most notably, in 1975, Moore altered his projection to a doubling every two years. Despite popular misconception, he is adamant that he did not predict a doubling “every 18 months”.

So clearly Moore’s law is more of an observation. Wally Rhines, Mentor Graphics CEO and my favorite presenter certainly thinks so. In his presentation to the U2U conference (that I mentioned in my previous blog), Wally feels that Moore’s empirical observation has been a useful approximation for the past 40 years due to a basic law of nature called “The learning curve”.

By definition, a learning curve is a graphical representation of the changing rate of learning for a given activity or process. Typically, the increase in retention of information is sharpest after the initial attempts and then gradually evens out, meaning that less and less new information is retained after each repetition. The learning curve can also represent at a glance the initial difficulty of learning something and, to an extent, how much there is to learn after initial familiarity.

An amazing thing, the presentation is seventy pages long and filled with an incredible amount of data, but you will never see a better data delivery system than Wally Rhines. It would be impossible to do a Wally presentation justice in a 500 word blog but here is what I learned that day:
For perspective there are:

  • 100+ billion galaxies in the night sky
  • 100+ billion stars in the milky way galaxy
  • 100+ billion transistors on a chip by 2025

Delivering 10X and beyond design improvements will require:

  • System Level Design
  • Functional Verification
  • Embedded Software
  • Physical Design and Verification


A new level of abstraction will be required for billions of transistors, 100 millions of gates, millions of lines of RTL, and hundreds of lines of TLM or C-based code. I remember the transition from schematic based design to language based (synthesis), it was a bloody battle for sure. The poor ESL guys never had a chance! Expect nothing less for System Level Design.

Verification is falling further behind and will need exponential growth in speed and capabilities to keep pace. Redundant verification must be eliminated. Emulation with transactional testbenches and mixing dynamic and formal verification will be required. Verification is one of the big challenges I see with the foundries, absolutely.

Physical Design and Verification will continue to see new routing architecture every 2-3 nodes, parallel optimization, and full parallelization of routing. Place and route will be merged with verification to reduce/eliminate ECO routing iterations. This will be a big win for Mentor obviously since they own the verification market and are trying to move up the physical design chain.

Embedded Software is a hot topic for Wally and of course where Mentor has made significant investments. According to Wally most of the escalating SoC design costs can be attributed to software development, which will by far outpace hardware development.

Wally is my favorite EDA CEO. He is humble, brilliant, personable, and a great speaker. No coincidence Mentor Graphics is also my favorite EDA company as it mirrors Wally. Why Dr. Walden C. Rhines does not have his own wiki page I do not know (too humble?). Rumor has it I may get a lunch with Wally sometime soon, which will certainly reinforce the notion that I blog for food.

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