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Transistor-Level Electrical Rule Checking

Transistor-Level Electrical Rule Checking
by Daniel Payne on 04-20-2011 at 11:19 am
Categories: EDA, Siemens EDA

Introduction
Circuit designers work at the transistor level and strive to get the ultimate in performance, layout density or low power by creating crafty circuit topologies in both schematics and layout. Along with this quest comes the daunting task of verifying that all of your rules and best practices about reliability have been followed properly. While at Intel I debugged a DRAM design that had a yield loss issue caused by an electromigration failure, and this was at 6um design rules. We didn’t have any automated tools at that time to pinpoint where current density rules were exceeded. It simply meant that we created silicon, tested it, found reliability issues, fixed the issues, and re-spun another batch of silicon. This cost us valuable time to market delays.Lets take a quick look at several classes of circuits that would benefit from an Electrical Rule Checker (ERC) tool.

ESD Protection
Consider what happens at the inputs and outputs for each pad in your IC design for ESD (Electro Static Discharge) protection.

On the left we have an input pad with clamp cell, and in the middle an output pad with diode protection for overshoot and undershoot. For the input pad layout there are special rules for the current densities allowed in creating the series resistor as shown in the following diagram:

An ERC tool would need to read both the schematic and layout topologies, find the path from input pad to clamp cell, calculate current density along that path, compare current density versus the technology-specific constraints, and finally report any violations.A domain expert in ESD best practices should be able to program an ERC tool in order to automate the verification process.

Calibre PERC
Matthew Hogan is the TME at Mentor for their tool called Calibre PERC (Programmable Electrical Rule Checker) and he gave me an overview and demo last month. This tool automates the verification of transistor-level best practices in order to ensure first silicon success.

Multi-Power Domains
Portable consumer electronics like Smart Phones and Tablets are driving a large part of the semiconductor economy these days so it is import to have long battery life. This challenge is met by using a multi-power domain methodology where high speed sections have a higher power supply value than lower speed sections. Where these two power domains meet you need to insert a level shifter. PERC can verify if level shifters are in place.


Bulk Pin Connection
If your low-voltage PMOS device has the bulk connected to the wrong VCC supply it will function but also cause a reliability issue. With PERC you can write a rule to check for this condition:


Layout Based Verification
Rules can be described to find and report many classes important to reliability: Point to point resistance, current density, matching devices on a net, coupling de-cap placement, and hot gate identification.

Visualization
During the demo I saw the syntax for PERC rules and what happened when these rules were run on a test schematic and layout.

Each violation of a rule is highlighted, when I click a violation then I see both the schematic and layout windows appear and the violation is shown in red.

PDK
I think that the foundries will love this tool and should put in some effort to create and support PERC rules as part of their PDK (Process Design Kits). It’s really in their best interest to ensure first silicon success.

Conclusion
The Calibre PERC tool from Mentor combines ERC for both schematic and layout topologies so that you can enforce your own best practices across an IC design. Circuit designers can now use this methodology to check their designs for many classes (ESD, multi-power domain, AMS, etc.) of their circuits.

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Thanks for the memory

Thanks for the memory
by Paul McLellan on 04-20-2011 at 1:26 am
Categories: Uncategorized
1 Comment

One of the most demanding areas of layout design has always been memories. Whereas digital design often uses somewhat simplified design rules, memories have to be designed pushing every rule to the limit. Obviously even a tiny improvement in the size of a bit cell multiplies up into significant area savings when there are billions of memory cells on a chip. It’s like that 9/10c per gallon at the gas station. It’s just a dime or so to you, but for Exxon it is real money.

Starting from its home base in Taiwan, Laker has been successful at capturing many of the big names in memory design in Asia. Hynix (based in Korea of course), Winbond and Eon (a newly public fabless memory company based in Taiwan) are all customers. Between them they cover DRAM, NAND flash, NOR flash and lots of specialized memory products for graphics and mobile.

But once you get outside the core itself, memory is no longer designed completely by hand, the automation from custom digital routing (driven off the desired connectivity) is an important part of productivity. To be useful in this sort of demanding layout environment it needs to be both gridded and shape-based, tuned for memory-specific routing styles such as main and secondary spine routing and limited routing layers (remember, memories like to keep metal cheap).

So memory layout is one of the most demanding application spaces of all. When I was at VLSI Technology our corporate counsel came from Micron and was amazed at the difference: “we put a design into production about once a year, here you do it about once a day.” Well, the memory market is no longer like that. It may not have quite the churn of new designs that a full-blown ASIC business does, but it is moving in that direction.

More information about Laker’s custom digital router here

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Intel Buys an ARMy. Maybe

Intel Buys an ARMy. Maybe
by Paul McLellan on 04-19-2011 at 5:18 pm
Categories: Arm, Foundries, Intel Foundry, IP

Is Intel in trouble? Since it is the #1 semiconductor company and, shipping 22nm in Q4 this year with 14nm in 2013, it is two process generations ahead of everyone else it is hard to see why it would be. Intel, of course, continues to dominate the market for chips for notebooks, desktops and servers. But therein lies the problem. Pads are killing netbooks and nibbling at notebooks. These are not growing markets and actually are starting to gradually shrink. Instat reckons that in Q1 2011 PC volumes are down 2-3% from Q1 2010, largely due to incursion of iPads.

The growing markets are largely ARM-based: smartphones and iPad type computers. Intel’s approach to these markets has not been a success. First, after its acquisition of (part of) Digital’s semiconductor business it got StrongARM, renamed it Xscale, and invested something like a billion dollars in trying to penetrate the communications business. Eventually it disposed of that business to Marvell in a fire sale. Depending on what residual rights they retained this could turn out to have been an enormous strategic error. They didn’t just give up a ARM manufacturing license, they gave up a do-pretty-much-anything ARM architectural license.

Next up was Atom, a bet that whatever the sub-PC market was going to turn out to be that binary compatibility with Windows and with Microsoft Office would be a key differentiator. Intel even announced a sort-of deal with TSMC to allow people to build Atom-based SoCs but that didn’t seem to go anywhere and seems to have quietly faded away. Of course, iPad came along, closely followed by Android-based competitors. It seems clear now that Windows binary compatibility for this market is not something significant and, as a result, the entire Atom strategy has failed. At CES, the final nail was Microsoft announcing that even they didn’t believe x86 binary compatibility was that important and they would port some version of Windows to ARM (and, of course, WP7 already runs on ARM).

But Intel has a big fab to fill and it wants to grow. It has to compete with TSMC in process and leaders who use the ARM architecture in product. It is pretty clear that the only markets growing fast enough are ARM-based so Intel needs to have an ARM-based business. It doesn’t have time (and its track record doesn’t inspire confidence) to build one itself, so it will have to buy one. They could buy ARM themselves, perhaps, although that doesn’t directly help them fill their fab and has all sorts of antitrust issues I’m sure. Who else? The obvious candidate is TI’s OMAP business. TI are rumored to be shopping their wireless business around in order to focus on analog and DSP, maybe more so after the acquisition of National. The other big wireless businesses are part of Samsung and part of ST (well, actually the ST-Ericsson-NXP JV) but neither are likely to be for sale. And, of course, Qualcomm, but their market cap is already 2/3 of Intel’s and so that won’t fly. On the other hand, Qualcomm would have a hard time competing against an Intel ARM product line with two process generations’ lead.

The only other area of potential interest could be to pick up an FPGA business. It would pretty much have to be Xilinx or Altera to be big enough to help fill the fab. Of course these two approaches aren’t mutually exclusive, a big ARM business and an FPGA business should fill the remaining space in the fab.

TI/OMAP and Altera. Pure speculation, of course. We’ll have to wait and see.

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Semiconductor Virtual Platform Models

Semiconductor Virtual Platform Models
by Paul McLellan on 04-19-2011 at 3:38 pm
Categories: EDA

Virtual platforms have been an area that has some powerful value propositions for both architectural analysis and for software development. But the fundamental weakness has been the modeling problem. People want fast and accurate models but this turns out to be a choice.

The first issue is that there is an unavoidable tradeoff between performance and accuracy; you have to give up one to get the other. But models that are fast enough for software development need to be millions of times faster than RTL and there is simply no way to get that sort of speedup automatically. Just as you cannot get from a Spice model to an RTL model by simply removing unnecessary detail, you can’t get from an RTL model to a virtual platform behavioral model by removing unnecessary detail.

Trying to create a model with both speed and accuracy seems to be the worst of both worlds. The model either has insufficient accuracy to be used for verifying the interaction of low-level software with the chip (in order to get higher performance) or else, if it has that accuracy, it will be too slow for software developers.

A better approach is to accept this and create both a high-speed model, for software development, and a medium-speed cycle-accurate model for hardware and firmware debug.

The medium-speed model can be created from the RTL automatically. Carbon Model Studio takes RTL models, completely accurate by definition, and delivers speedups of 10-100x by throwing away detail to produce a Carbonized cycle-accurate model. This guarantees the fidelity of the medium speed model to the actual chip.

Fast peripheral models, and in this context “peripheral” just means anything other than the processors themselves, are actually pretty simply to create in most circumstances. Often the peripherals have very simple behavior and the complexity in implementation comes from making them run fast in hardware: there’s close similarity between a 1 megabit Ethernet and a 1 gigabit Ethernet (or even 1 terabit) from a model point of view, for the implementation challenge not so much.

Of the solutions out there right now, this combination of a hand-crafted high-performance model (probably in SystemC) and an automatically generated medium-performance model that is guaranteed to match the RTL seems to be the closest that it is possible to get to the sweet spot. Like the old engineering joke about cheap-fast-good, pick any two. For virtual platform models it is fast-accurate pick one.

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Semiconductor Industry Security Threat!

Semiconductor Industry Security Threat!
by Daniel Nenni on 04-17-2011 at 1:12 pm
Categories: General

The IBM X-ForceTrend and Risk Report reveals how 2010 was a pivotal year for internet security as networks faced increasingly sophisticated attacks from malicious sources around the world. The X-Force reportedly monitors 13 billion real-time security events every day (150,000 events per second) and has seen an increase in targeted security threats against both government and civilian organizations.

“The numerous, high-profile targeted attacks in 2010 shed light on a crop of highly sophisticated cyber criminals who may be well-funded and operating with knowledge of security vulnerabilities that no one else has,” said Tom Cross, threat intelligence manager at IBM X-Force. “Staying ahead of these growing threats and designing software and services that are secure from the start has never been more critical.”

Last year Iranian nuclear facilities were targeted. It first emerged in September that Iran was battling a powerful computer worm known as Stuxnet, which has the ability to send centrifuges — used in nuclear fuel production — spinning out of control. Different variants of Stuxnet targeted five Iranian organizations, with the probable target widely suspected to be uranium enrichment infrastructure. Iran confirmed that Stuxnet was found on mobile devices belonging to employees.

“Enemies have attacked industrial infrastructure and undermined industrial production through cyber attacks. This was a hostile action against our country,” Gholam Reza Jalali, head of a military unit in charge of combating sabotage, “If it had not been confronted on time, much material damage and human loss could have been inflicted.”

In its 16[SUP]th[/SUP] annual Internet Security Report, antivirus vendor Symantecdetected more than 286 million malware threats last year, signaling a big jump in the volume of automated cyber threats. Symantec gathers data from 240,000 points on the web in more than 200 countries and it gets intelligence from more than 133 million systems that use its antivirus products.

“We’ve seen seismic shifts in things like the mobile landscape,” said Gerry Egan, director of Symantec Research Labs. “The attacks are more sophisticated. There’s still a lot of education that has to happen to reduce the behavior that cybercriminals exploit.”

Last week WordPress.com revealedthat someone gained low-level (root) access to several of its servers and that source code was accessible and “presumed copied”. WordPress.com currently serves 18 million publishers, including VIPs Ebay, TED, CBS, Yahoo! and is responsible for 10% of all websites in the world. WordPress.com itself sees about 300 million unique visits monthly.

“We presume our source code was exposed and copied,” Mullenweg stated on the company’s blog. “While much of our code is open source, there are sensitive bits of our and our partners’ code. Beyond that, however, it appears information disclosed was limited.” Famous last words 😉

So what does this have to do with the semiconductor industry, an industry that is bound by dozens of EDA software vendors, IP companies, and design activity around the world? EVRYTHING! Think about how many people touch, directly and indirectly, an SoC design before tape-out? Use LinkedIn for example: My connections link me to 8,723,184+ people. The security risk probability for the semiconductor design ecosystem is staggering!

So when I see “security concerns” as the reason why fabless semiconductor companies CHOOSE not to get their designs into the cloud I laugh out loud. My guess is that it will take a catastrophic loss and/or jail time to get the semiconductor executives to protect intellectual property, the true assets of a company. Oh yeah, their financial assets are already safe and sound in the cloud!

Reference: 2011 Semiconductor Forecast: Partly Cloudy!

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2011: A Semiconductor Odyssey!

2011: A Semiconductor Odyssey!
by Daniel Nenni on 04-15-2011 at 10:08 pm
Categories: General

Stanley Kubrick’s 2001: A Space Odyssey showed us a world where machine vision allowed a computer to watch and interact with its human colleagues. Yet after 40 years of incredible progress in semiconductor design, the technology to make computer-based image and video analysis a reality is still not practical.

While working with semiconductor IP companies in Silicon Valley I met Parimics, a very promising start-up focused on making real-time image and video analysis a reality. The company has created a unique architecture to make machine vision orders of magnitude more powerful, reliable and easy to use and deploy.

The key to Parimics’ image and video analysis subsystems is a novel image analysis processor chipset and accompanying software to deploy the technology. Vision systems based on Parimics’ technology are capable of processing image and video data in real time — right when the image and video data is taken. This is a huge advantage compared to current systems that perform analysis offline, i.e. after images have been captured and stored. Applications for the technology include automotive guidance; security and surveillance; medical and biotechnology applications such as f-MRI machines and high-throughput drug screening processes; advanced robotics; and of course generalized machine vision applications. Since these solutions are both deterministic and real-time capable, they can be used in scenarios that demand high reliability.

Image analysis solutions available today don’t have the speed or accuracy needed for complex machine vision applications. Speeds of 20 frames per second (FPS) or less are the rule. The ability to track specific objects is often limited to 3-5 individual items per frame. Filtering out noise and objects that are not relevant to the video analysis is poorly done with today’s systems. Finally, typical probabilistic methods greatly reduce system accuracy and trustworthiness. In some applications, it just cannot be tolerated that results are probabilistic or unreliable, or non-real-time.

In stark contrast, Parimics’ unique and patented architecture supports speeds between 50 to 20,000 FPS, and its results are deterministic and reliable. Even in the cost-optimized version of the processor chipset, Parimics’ solutions can track 160 unique objects per VGA or HD frame. The computational horsepower of the chipset also allows it to filter out noise and objects that are not relevant to the application within a very small number of frames.

Parimics’ architecture is specifically designed for advanced image analysis, much the same way that graphics processors are designed to create graphical images. The video analytics processors take in any type of image at any speed and use a massively parallel architecture to analyze all the objects in the field of view. Parimics’ scalable approach to solving customer problems easily meets the very wide range of their performance and cost requirements.

The company’s technical advisory board includes Stan Mazor, key inventor of Intel’s first microprocessor; John Gustafson, a leading expert in parallel architectures; John Wharton, inventor of the pervasive Intel 8051 microcontroller, and Dr. Gerard Medioni from USC, internationally known for his work on image recognition software.

Parimics’ founders, CEO Royce Johnson, and CTO Axel Kloth, have a combined experience of more than 50 years in chip design and management of cost-effective operations. See their web site at www.parimics.com for more details.

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Chip-Package-System (CPS) Co-design

Chip-Package-System (CPS) Co-design
by Paul McLellan on 04-14-2011 at 5:13 pm
Categories: Ansys, Inc., EDA

I can still remember the time, back in the mid-1980s, when I was at VLSI and we first discovered that we were going to have to worry about package pin inductance. Up until then we had been able to get away with a very simplistic model of the world since the clock rates weren’t high enough to need to worry about the package and PCB as anything other than a simple capacitive load. Put big enough transistors in the output pads and the signal would change acceptably fast. Of course, back then, 10K gates was a large chip so it was a rather simpler and more innocent time than we have today.

Those days are long gone. Now we have to analyze the chip, the package and the PCB as a single system, we can’t just orthogonally worry about the chip separately from the package and then just expect to put that package on any old PCB. In the old days, there was plenty of noise margin, we were less sensitive about trading-off increased power against reliability and there was simply less interaction between signals.

The full low-level details of the entire chip are clearly overkill for CPS analysis. Instead, a model of the die is necessary to model the noise generated by the chip. Chip power models include the die-level parasitics as well as instance switching noise. Since the model will be used for EMI emission analysis, simultaneously switching outputs (SSO) power analysis, noise analysis and more, the model must be accurate across a broad frequency range. Transistor switching noise is modeled by region-based current sources that capture the transient behavior. The power model is reduced to a SPICE format that allows long system simulations to be done using any circuit simulator.

Chip power models represent the switching noise and parasitic network of the die. The next generation of chip power model has recently become available, enabling more advanced CPS analysis methodologies. Designers are now able to probe at lower metal layer nodes in the die, to observe transistor-level noise in CPS simulation. The transient behavior of the die can now capture advanced operational modes, which are of particular interest to system engineers, such as resonance-inducing activity and transitions from low-power to high-power modes. Chip designers can now create user-configurable chip power models that can be programmed to represent different modes, depending on the simulation.

The increasing importance of CPS analysis has led Apache to create a CPS user-group to bring some standardization and interoperability to the area and create a Chip-Power Model reference flow. Besides Apache, the founding members include representatives from the top 10 semiconductor companies.

Matt Elmore’s blog on CPS
CPS user-group created by Apache

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DDR4 Controller IP, Cadence IP strategy… and Synopsys

DDR4 Controller IP, Cadence IP strategy… and Synopsys
by Eric Esteve on 04-14-2011 at 4:17 am
Categories: Uncategorized
4 Comments


I will share with you some strategic information released by Cadence last week about their IP strategy, more specifically about the launch of the DDR4 Controller IP. And try to understand Cadence strategy about Interface IP in general (USB, PCIe, SATA, DDRn, HDMI, MIPI…) and how Cadence is positioned in respect with their closest and more successful competitor in this field, Synopsys.

When Cadence has acquired Denali for $315M, less than one year ago, one of the nuggets was the DDRn controller IP product line built by Denali during the last 10 years. Denali’ DDR controller IP was well known within the industry, doing pretty well with sales in 2009 estimated to be slightly less than $10M (even if Denali was one of the very few companies who constantly report to Gartner DDR Controller IP business results below the reality!). Their product was nice, but still based on a Soft PHY, making life more complicated for the designer having to integrate it. Synopsys DDR Controller IP (coming from the acquisition of MOSAID in 2007) was already based on a hard PHY, as well as Virage’ product (coming from the acquisition of INGOT in 2005). That’s why Denali had to build a partnership with MOSYS (in fact Prism Circuit before to be acquired in 2009) to offer a solution based on a hard PHY (from MOSYS) and their DDR3 Controller. Before the acquisition of Denali by Cadence (and Virage by Synopsys, by the way) in May 2010, the DDR Controller IP market was growing fast, and very promising, as we can see on the two figures.

In fact, if the number of ASIC design start is declining, the proportion of SoC is growing faster, so the net count of ASIC integrating a processor (or Controller, DSP) core is growing. When you integrate a processor, you need to access an external memory (the cost of embedded DRAM being prohibitive) so you need t integrate a DDRn Controller. Considering the ever increasing memory Interface frequency, and the related difficulty to build a DDRn Controller in-house, the make vs buy question leads more frequently to an external solution, or to buy an IP. This is why the forecast for the DDR Controller IP market, even the more conservative, shows a x3 multiplication during the next 3 years. And when we compare the DDR IP market with the other Interface IP market, we expect it to be the faster growing market, as we can see on the first figure.

With this history in mind, you better understand why it was important for Cadence to be the first to launch a DDR4 Controller IP. Proposing a hard PHY option is a way to catch up with Synopsys, who offer hard PHY systematically for the DDR IP product. The lack of such a hard PHY was a weakness of the Denali DDRn IP product line, this explain why Denali had built a partnership with Prism Circuit in April 2009 to offer a complete solution based on a (soft) Controller from Denali and a (hard) PHY from Prism Circuit. Ironically, both companies have been acquired in the meantime…

If we look at the IP market, at least at the Interface IP segments (USB, PCIe, SATA, HDMI, DDRn, MIPI…), we see that the positioning of Cadence is pretty weak, compared with Synopsys. Cadence is supporting DDRn segment, thanks to Denali product line, the PCIe segment (in fact restricted to PCIe Gen-3)… and that’s it. When Synopsys is active in all the above mentioned segments, with a dominant position (more than 50% market share) in USB, SATA, PCIe, DDRn and a decent (but unknown) position in HDMI and MIPI. Moreover, Cadence strategy as presented during IP-SoC 2010 last December in Grenoble, which was to build a complete offer in the Interface IP market through partnership with existing IP vendors (if you prefer, offering a solution coming from 3[SUP]rd[/SUP] party instead of internally developed) has completely vanished. This will certainly leave the door open for Synopsys to consolidate their dominant position, and build a product line of more than $250M on a $500M market (IPnest evaluation of the Interface IP market in 2015). To summarize, Mentor Graphics gave up in 2005 on the IP market, and the last announcement from Cadence means that they will attack 20% only of this market (the DDRn IP) and give up on the remaining 80%, which will represent $400M in 2015.

The study of the Interface IP market: analysis of 2004-2009 results and Forecast for 2010-2015 can be found on:http://www.ip-nest.com/index.php?page=wired

This survey is unique and very complete, looking at each interface (USB1,2, USB3, PCIe, SATA, DDRn, HDMI, MIPI, DisplayPort and more) and proposing a forecast for 2010-2015.
It has been sold to several IP vendors (Cadence (!), Mosys, Cast, Evatronix, HDL DH…) and the KSIA in Corea. Please contacteric.esteve@ip-nest.com if you are interested…

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AMD and GlobalFoundries / TI and UMC

AMD and GlobalFoundries / TI and UMC
by Daniel Nenni on 04-11-2011 at 11:38 am
Categories: Foundries, GlobalFoundries

There have been some significant foundry announcements recently that if collated will give you a glimpse into the future of the semiconductor industry. So let me do that for you here.

First the candid EETimes article about TI dumping Samsung as a foundry:

Taiwan’s UMC will take the ”lead role’’ in making the OMAP 5 device on a foundry basis for TI, said Kevin Ritchie, senior vice president and manager of TI’s technology and manufacturing group.

“We have not been pleased with the results’’ at Samsung, he told EE Times in a telephone interview. Samsung has indeed built and shipped parts for TI. ”I can’t complain about the yields,’’ he said. ”I can complain about everything else.’’

Regarding Samsung’s future as a foundry partner within TI, Ritchie said TI will rely on Samsung to a ”lesser extent’’ at 45-nm. Samsung is ”off our radar at 28-nm,’’ he said.

As I have written before, Samsung is NOT a Foundry! And I absolutely agree with his statement about UMC, a company I have worked with for many years:

”UMC, for us, is everything that Samsung is not,’’ he said. UMC ”does not get enough credit.’’

UMC is by far the most humble foundry and gets much more respect from the top tier semiconductor companies than the traditional press!

UMC (NYSE: UMC, TWSE: 2303) is a leading global semiconductor foundry that provides advanced technology and manufacturing services for applications spanning every major sector of the IC industry. UMC’s customer-driven foundry solutions allow chip designers to leverage the strength of the company’s leading-edge processes……

Foundry 2010 Revenue:
(1) TSMC $13B
(2) UMC $4B
(3) GFI $3.5B
(4) SMIC $1.5B


DanielNenni
#UMC buys equipment for 3D IC manufacturing http://tinyurl.com/3ext569
#UMC gearing up for 12-inch capacity expansion http://tinyurl.com/3jq99xw
#UMC Financials Q2 2011 +5.25% Y/Y http://tinyurl.com/3htnpv2

Second is the announcement about AMD and GlobalFoundries changing their manufacturing contract. The revised pricing model is a short-term measure to address AMD’s financial needs in 2011 as they aggressively ramp up and deliver 32nm technology to the marketplace. The intention is to return to a cost-plus model in 2012.

The agreement also provides an increased upside opportunity for GFI in securing a larger proportion of future chipset and GPU business from AMD. Why is this important to the foundry business? Because this absolutely supports the collaborative partnership model that GlobalFoundries has been pushing since day one. The question I have is: When will AMD and GFI announce a joint ARM based mobile strategy? The insider talk was that AMD CEO Dirk Meyer was forced to resign due to the lack of a feasible mobile strategy so a quick ARM based strategy would make complete sense.

The other significant GlobalFoundries news is the partnership with IMEC on sub-22nm CMOS scaling and GaN-on-Si technology. IMEC, a long time TSMC partner, is one of the largest semiconductor consortia in the world. IC manufacturers, fabless companies, equipment and material suppliers, foundries, and integrated device manufacturers (IDMs), collaborate on the continued CMOS scaling into the sub-22nm node. Today GFI relies on IBM process technology which is limiting to say the least. IBM can’t even spell collaborate.

All in all a great week for the semiconductor industry! GlobalFoundries is definitely in for the long term and UMC finally gets credit where credit is due!

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Who Needs a 3D Field Solver for IC Design?

Who Needs a 3D Field Solver for IC Design?
by Daniel Payne on 04-07-2011 at 4:53 pm
Categories: EDA, Siemens EDA

Inroduction
In the early days we made paper plots of an IC layout then measured the width and length of interconnect segments with a ruler to add up all of the squares, then multiplied by the resistance per square. It was tedious, error prone and took way too much time, but we were rewarded with accurate parasitic values for our SPICE circuit simulations.

Today we have many automated technologies to choose from when it comes to extracting parasitic values for an IC layout. These parasitic values ensure that what we simulate in SPICE is accurately providing the right timing value, can detect glitches and measure the effects of cross-talk.

Accuracy vs Speed


The first automated parasitic extraction tools used rules about each interconnect layer for resistance and capacitance as a function of width, length and proximity to other layers. These tools are fast and reasonable accurate for nodes that have wide interconnect with little height. As the height of interconnect have grown then the accuracy of these rules diminishes because of the complex 3D nature of nearby layers.

3D field solvers have been around for over a decade and have also offered the ultimate in accuracy with the major downside being slow run times. The chart above places 3D field solvers in the upper left hand corner, high accuracy and low performance.

Here’s a quick comparison of four different approaches to extracting IC parasitics:

[TABLE] class=”cms_table_grid”
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | Approach
| class=”cms_table_grid_td” | Plus
| class=”cms_table_grid_td” | Minus
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | Rule-based/Pattern Matching
| class=”cms_table_grid_td” | Status quo
Familiar
Full-chip
| class=”cms_table_grid_td” | Unsuitable for complex structures
Unable to reach within 5% of reference
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | Traditional Field Solver
| class=”cms_table_grid_td” | Reference Accuracy
| class=”cms_table_grid_td” | Long run times
Limited to devices
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | Random-Walk Field Solver
| class=”cms_table_grid_td” | Improved Integration
| class=”cms_table_grid_td” | 3 to 4X slower than Deterministic
|- class=”cms_table_grid_tr”
| class=”cms_table_grid_td” | Deterministic Field Solver
| class=”cms_table_grid_td” | Reference-Like Accuracy
Fast as Rule-based
| class=”cms_table_grid_td” | Multi-cpu required (4 – 8)
|-

What if you could find a tool that was in the upper right hand corner, offering high accuracy and fast run times?

That corner is the goal of a new breed of 3D field solvers where highest accuracy and fast run times co-exist.

Mentor’s 3D Field Solver
I learned more about 3D field solvers from Claudia Relyea, TME at Mentor for the Calibre xACT 3D tool, when we met last month in Wilsonville, Oregon. The xACT 3D tool is a deterministic 3D field solver where multiple CPUs are used to achieve faster run times. A white paper is available for download here.

Q: Why shouldn’t I try a 3D field solver with a random-walk approach?

A: Well, your results with a random-walk tool will have a higher error level. Let’s say that you have 1 million nets in your design, then with a sigma of 1% you will see 3,000 nets where the accuracy is >3% different from a reference result. For sensitive analog circuits and data converters that level of inaccuracy will make your chip fail.

Q: What is the speed difference between xACT 3D and random walk tools?

A: We see xACT 3D running about 4X faster.

Q: What kind of run times can I expect with your 3D field solver?

A: About 120K nets/hour when using 32 cpus, and 65K nets/hour with 16 cpus.

Q: How is the accuracy of your tool compared to something like Raphael?

A: On a 28nm NAND chip we saw xACT 3D numbers that were between 1.5% and -2.9% of Raphael results.

Q: Which customers are using xACT 3D?

A: Over a dozen, the one’s that we can mention are: STARC, eSlicon and UMC.

Q: For a device level example, how do you compare to a reference field solver?

A: xACT 3D ran in 9 seconds versus 4.5 hours, and the error versus reference was between 4.5% and -3.8%.

Q: What kind of accuracy would I expect on an SRAM cell?

A: We ran an SRAM design and found xACT 3D was within 2.07% of reference results.

Q: How does the run time scale with the transistor count?

A: Calibre xACT 3D has linear run time performance with transistor count. Traditional field solvers have an exponential run time with transistor count making them useful for only small cells.

Q: What is the performance on a large design?

A: A memory array with 2 million nets runs in just 28 hours when using 16 cpus.

Q: Can your tool extract inductors?

A: Yes, it’s just an option you can choose.

Q: How would xACT 3D work in a Cadence IC tool flow?

Q: Can I cross-probe parasitics in Cadence Virtuoso?

A: Yes, that uses Calibre RVE.

Q: Where would I use this tool in my flow?

A: Every place that you need the highest accuracy: device, cell and chip levels.

Summary
3D field solvers are not just for device level IC parasitics, in fact they can be used on cell and chip level as well when using multiple CPUs. The deterministic approach by Mentor gives me a safer feeling than the random-walk method because I don’t need to worry about accuracy.

I’ve organized a panel discussion at DAC on the topic of 3D field solvers, so hope to see you in San Diego this June.