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DAC: Chevy Volt Teardown

DAC: Chevy Volt Teardown
by Paul McLellan on 05-10-2012 at 7:03 pm
Categories: EDA, Events

One DAC panel session that I am looking forward to attending is the Chevy Volt Teardown. This takes place at 1.30-2.30pm on Tuesday June 5th at the DAC pavilion (aka booth 310). Al Speier will be talking about a teardown that they did at Munro Associates where he is a senior associate. Unfortunately they won’t actually be tearing down a Chevy Volt on the show floor. That would be a clever trick in an hour for a start. But you can see Al do it in just 4 minutes on a time-lapse video.

The battery is huge, 435lbs, shaped in a big T under the rear seat and under the tunnel between the front seats (who knew a front-wheel drive car would have a tunnel for the non-existent prop-shaft!). It has its own cooling system. I have read that it produces 360V and has a capacity of 16kWhr (although it only has 10kWhr available for use since it never completely discharges or completely charges the battery). A horse-power is roughly a kW (actually 1HP=0.75kW) this means around 20 horse-power for an hour. But a normal car’s petrol engine has around 80-250 horsepower, admittedly at the tacho redline. According to Wikipediathe peak power of the electrical motor is 111kW, which is in that range, at which rate it would exhaust the battery in less than 10 minutes. Hmm. I guess when just cruising along the power demands must be an order of magnitude less. The all electric range is apparently 25-50 miles so less than an hour at freeway speeds which would fit. For reference, a gallon of gas contains around 36kWhr so three times the usable capacity of the battery. Gas really is incredibly energy-dense.

Apparently 40% of the value of the vehicle is in electronics with over 100 electronic control units (ECUs) of one sort or another. That’s a lot of compute power.

The Volt charges the battery like any hybrid through regenerative braking. And, as you probably know, it can be charged from a 110V outlet or a special 220V charging station. Plus, it has a regular gasoline engine that also can charge the battery. Unlike a hybrid, only the electric motors drive the wheels, the gasoline engine only drives a generator to drive the wheels and recharge the battery.

Munro’s website is here.

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RTDA at DAC: Scale to Millions of Jobs

RTDA at DAC: Scale to Millions of Jobs
by Paul McLellan on 05-10-2012 at 7:00 pm
Categories: EDA

RTDA is all about enterprise level scalability. Their three main products all scale to be able to handle the most demanding needs of large companies with large farms of servers. Of course there are some new refinements too.

LicenseMonitor can scale to 70,000 simultaneous checkouts with 1 billion checkout records in the database. There are new reports and support for postgres.

NetworkComputer scales to millions of jobs in the queue, thousands of cores being managed, hundreds of license features. Come and find out about license overbooking. Many jobs, such as simulation, don’t use their licenses 100% of the time. Just as statistical multiplexing means that, say, 20 phone calls can fit in 18 channels (there is always someone not talking), NetworkComputer can start additional jobs that statistically will be able to get licenses most of the time when they need them (otherwise they have to wait). And so 20 simulation jobs can run with only 18 licenses.

FlowTracer can scale to hundreds of thousands of files and jobs with speed improvements in some cases of over 10X compared to the alternatives. There are improved interfaces to makeFiles.

So if you have demanding needs for keeping all those EDA licenses and all those servers humming along and working on the right stuff with the right priorities, then come by the RunTime Design Automation booth. Hey, you could win a Kindle Fire too.

RTDA is at booth 1508. To schedule a demo send email to info@rtda.com.

And talking of NetworkComputer, over here on LinkedIn there is an interesting discussion comparing NetworkComputer to IBM’s LSF product, the “500 pound gorilla” in the space. I don’t know how representative the people replying to the thread are, but the general consensus seems to be the NetworkComputer works better than LSF (increased license utilization), is cheaper than LSF (which is 3 times the price), and RTDA’s support is exemplary. If you are a NetworkComputer user who also has LSF experience then go and add your 2¢.

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Only slight growth in 2012 semiconductor market

Only slight growth in 2012 semiconductor market
by Bill Jewell on 05-09-2012 at 11:24 pm
Categories: Semiconductor Intelligence, Semiconductor Services
1 Comment

The world semiconductor market declined 2.2% in 1Q 2012 from 4Q 2011, according to WSTS. The market ended 2011 on a down slide, with 4Q 2011 down 7.7% from 3Q 2011. The year 2011 semiconductor market was up only 0.4%.

Three major events contributed to the weakness in 2011:

[LIST=1]

  • March 2011 earthquake and tsunami in Japan disrupted electronics and semiconductor production.
  • Floods in Thailand in 3Q and 4Q 2011 severely impacted electronics production, especially hard disk drives (HDD).
  • The European financial crisis resulted in weak demand in 4Q 2011.

    2012 will not likely see significantly different growth than 2011. Of the three major crises in 2011, Japan and Thailand have mostly recovered. However the European financial crisis continues. The affected nations have adopted a plan to overcome debt problems, but the austerity measures put in place will result in weakness in the European economy through at least 2012.

    The table below shows the available revenue guidance from the top semiconductor suppliers for 2Q 2012 versus 1Q 2012. The guidance is generally strong, with the top end of guidance for Intel, TI, ST and Broadcom around 10%. Qualcomm expects a decline, in line with its typical seasonal trends. Samsung expects a recovery in PC DRAM and increased demand for embedded flash memory. Our forecast at Semiconductor Intelligence is for 2Q 2012 semiconductor market growth of 6% over 1Q 2012.

    Semiconductor Intelligence’s forecast for the year 2012 is2% growth. Our prior forecast in February was a 1% decline, however 1Q 2012 was not as weak as we expected. Growth of 6% in 2Q 2012 followed by growth averaging6% in 3Q and 4Q drives the 2% forecast for the year. The chart below shows forecasts from the last two months. Most industry analyst firms see growth in the 4% to 7% range. Mike Cowan’s model based on historical WSTS data predicts a1.7% decline.

    Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers,foundries, suppliers, users or investors. Please contact me if you would like further information.

    Sincerely,

    Bill Jewell
    Semiconductor Intelligence, LLC
    billjewell@semiconductorintelligence.com

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    Apple Games Qualcomm’s 28nm Supply for Labor Day iPhone 5 Launch

    Apple Games Qualcomm’s 28nm Supply for Labor Day iPhone 5 Launch
    by Ed McKernan on 05-09-2012 at 11:17 pm
    Categories: Foundries, General

    You can see a lot just by looking – as Yogi Berra was quoted as saying. The past two weeks we have seen quite a bit that adds intrigue to the true nature of Qualcomm’s 28nm product shortage and how the effects will ripple through the mobile industry for the second half of 2012. Samsung’s bold announcement of their Galaxy S III smartphones was a message to the world that they intended to leap frog Apple in terms of products so they could attain market domination later this year. However, when one maps the delivery of the 4G LTE Galaxy (which is said to be July in the US) against Qualcomm’s ramp of 28nm products and the likely rollout of Apple’s product line, you will get the sense that Apple has an upper hand in the battle for dominance. Make no mistake, Qualcomm is sitting in a very strong position vis-à-vis other ARM vendors, however Apple has a call on most of its output into Q4 2012.

    When Qualcomm held its last quarterly earnings call, it revealed to analysts that it faced a severe shortage of 28nm supply for the next two quarters and into the December quarter, the height of the Smartphone selling season. As analyst peeled away the mystery with question after question, Qualcomm admitted the shortfall in this quarter was minor and that they would exit the September Quarter with 1/3 of their volume based on 28nm. There are two key products that Qualcomm is building for the mobile market. One of them is a 4G LTE baseband chip (MDM9615) and the other is the highly integrated Snapdragon S4 that includes a dual core ARM with graphics and 4G LTE baseband. Qualcomm stated they would need to bring on additional capacity at other foundries, which involve tapeouts. Apple is believed to be building its iPhone 5 with its own ARM (presumably A6) processor and the MDM9615. Samsung and it turns out HTC is signed up to use the Snapdragon S4. And this is where it gets interesting.

    Prior to Samsung’s Galaxy SIII announcement, they introduced their newest, low power quad core 32nm ARM chip for mobiles. It is slated for all of the Galaxy models but the one coming to the US. In other words to get 4G LTE, Qualcomm made them take the Snapdragon part. The assumption here was that the decision was made in March for a July launch, which impacted the 28nm supply situation.

    When Qualcomm announced their 28nm shortage, most analysts and myself included believed it was across the board and would as a result delay Apple’s iPhone 5 launch well into October and as a result effect Apple’s revenue in September and December quarters. The stock took an immediate hit. With the Samsung and HTC announcements, I am now more convinced that what happened is much more complex and reveals an underlying Apple strategy.

    The announcement of the new iPAD in early March with 4G LTE sent a signal that the entire Apple product line was going to include 4G LTE over the course of this year. So we should expect a June launch of Mac Books and Mac Airs with 4G LTE in at least the high end SKUs in combination with Intel’s Ivy Bridge ULV processor. I believe part of the reason for Intel’s delayed launch of the ULV version of Ivy Bridge was to get the marketing bang of the combination of 4G LTE with Ivy Bridge and no AMD or nVidia in sight. Be sure that Intel has communicated to Dell, HP and Lenovo that they need to upgrade their Ultrabooks with 4G LTE as well. So the frantic phone calls to Qualcomm for supply have been made. The line just grew.

    The biggest mistake that Tim Cook has made as a CEO occurred just two months into his reign when the launch of the iPhone 4S was pushed into early October. Because the event is tracked very closely and Wall St spies comb the supplier networks daily it is hard to keep the launch secret in the weeks leading up to it. Word spreads to the general public and customers hold off buying. And so the September 2011 quarter sales came in lighter than expected. Fear spread through Wall St. and Apple was in the dog house until the January blow out earnings.

    This year will be different. The iPhone 5 launch will occur right after Labor Day (September 3[SUP]rd[/SUP]) so that Apple can capture iPhone 5 revenue for the last 3 weeks of the quarter and smooth the revenue ramp between September and December quarters. Looking back, it was estimated that if Apple had pulled in their iPhone 4S ramp by two weeks last year they would have well exceeded analyst expectations for both September and December quarters.

    What does this have to do with Apple gaming Qualcomm. Apple’s product roadmaps are set at least a year ahead of time. I believe that they communicated their production ramp with Qualcomm in time for them to get enough wafers in the line to support the MacBook, MacAir and iPhone 5 ramps. Remember Qualcomm exits the September quarter with 1/3 of their units based on 28nm. That says the iPhone 5 phones are streaming out of the Apple stores in September in time for parents to outfit their kids headed off to school (it’s another form of the no child left behind program).

    In every supplier agreement, there are upside clauses or call options. They can be very dramatic to the point it could be 50% more volume in a matter of a few weeks times. I believe Apple got wind of Samsung and HTC’s 4G LTE launch plans for July and decided to exercise the call option for more product sometime in March or early April. This would mean Qualcomm diverted TSMC 28nm wafers to the production of MDM9615 baseband chips and not the S4 Snapdragon that is slated for Samsung and HTC. This meant that Qualcomm had to seek additional capacity outside of TSMC.

    If Apple dominates the 4G LTE markets for Smartphones, Tablets and mobile PCs then the playing field gets dramatically reduced going into Q1 2013. Qualcomm is a winner but they would rather have more customers in order to gain leverage in their long term pricing and supply model. For the rest of the mobile ARM camp, its going to be a long rest of 2012.

    FULL DISCLOSURE: I am long INTC, AAPL, QCOM, ALTR

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    Atrenta at DAC: Fast Lint, IP Kit and More

    Atrenta at DAC: Fast Lint, IP Kit and More
    by Paul McLellan on 05-09-2012 at 7:03 pm
    Categories: EDA

    Atrenta will have a new look this year at DAC. I’m not quite sure what that means but we’ll all just have to go along and find out.

    They have three users talking about their use of Atrenta’s tools. All 3 of these presentations are in the user-track poster session on Tuesday June 5th 12.30-1.30pm in room 105 (which is on the exhibit floor).

    • Udupi Harisharan of Cisco will talk about SoC power budgeting and optimization using RTL-spreadsheet power estimation of ASICs.
    • Cyril Vartanian of STMicroelectronics will talk about RTL restructuring with Atrenta Gensys.
    • Ramesh Rejogopalan of Cisco will talk about Prevention of data loss in physical implementation of FIFOs and datapath synchronizers.

    Atrenta’s CEO, Ajoy Bose, will discuss trade-offs and choices for emerging SoCs at the DAC management day. Tuesday June 5th from 2-4pm in room 309.

    Atrenta Fellow Ravi Varadarajan will participate in a discussion on standards for the 3D world during the Si2 Roundup. Monday June 4th 3.15-4.30pm in room 301.

    Of course Atrenta will be presenting their own tools in their booth, 2230. For details and to register go here.

    Finally, come and celebrate with Atrenta and TSMC on Monday evening from 6-7pm in room 303 in the Moscone Center and on the outdoor terrace. The TSMC Soft-IP Alliance has already certified IP from ten providers as SpyGlass Clean. So grab a clean non-Spy glass and fill it with beer or wine.

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    Customers Talk About Reliability, Low-Power and 3D

    Customers Talk About Reliability, Low-Power and 3D
    by Paul McLellan on 05-09-2012 at 1:13 pm
    Categories: Ansys, Inc., EDA

    At DAC in San Francisco this year, Apache once again have a mixture of presentations by customers on their use of Apache tools and presentations by Apache themselves on their products. Most of the customer presentations are given just once, but the product presentations are given multiple times over the three days.

    I think one of the hot topics at DAC this year will be 3D-ICs (TSVs etc). One on of the first places that 3D chips are being used is building stacks of memory die, so the Samsung experience looks especially interesting.

    Here is a list of all the customer presentations. The product presentations are interspersed between the customer presentations.

    • Samsung-DRAM: System-level Power Noise Analysis and Optimization with Measurement Correlation Results for Multiple DRAMs with TSV
    • UC San Diego: Considerations for Designing and Simulating Memory Interfaces for 3D/Stacked-die Designs
    • Renasas: Enabling Accurate and Efficient RTL Power Analysis and Optimization Methodology for Low Power Designs
    • LSI: Power Noise and Other Simulation Considerations for Energy-efficient SoCs
    • Samsung-SSI: A Chip-Package Simulation Methodology for Ultra-Large Low-Power Mobile ICs
    • Ciena: Power Noise Analysis with Silicon Correlation Results for Complex 32nm ASIC Designs
    • NXP: Full-chip Substrate Noise Coupling Analysis and Noise Isolation Structure Design Experiments
    • Aptina: Evaluating Design Options and Trade-offs through Full-chip Substrate and Metal Layer Noise Analysis for a Commercial Image Sensor Chip
    • AMD: Electrostatic Discharge (ESD) Simulation and Sign-off Considerations for Complex GPU and APU Designs
    • nVidia: A Dynamic Simulation Methodology for Diagnosis and Predictive Simulation of HBM/CDM Events
    • ST-Ericsson: Simultaneous SI and PI Analysis for High-speed IO Designs for Mobile Applications

    Full details, including the presentations times and a short summary of each presentation are here. If you are interested, then you can register to attend on the same page.

    One other event is at the pavilion panel (booth 310) at 10.30 on Monday where Aveek Sarkar of Apache is one of the panelists on a panel called Power to the People, along with Clive Bittlestone of TI and Robert Patti of Terrazon Semiconductor.

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    Sagantec Update: More EDA Consolidation!

    Sagantec Update: More EDA Consolidation!
    by Daniel Nenni on 05-08-2012 at 7:00 pm
    Categories: Uncategorized

    Adding sophisticated 2D dynamic compaction technology to address 20nm and 14nm challenges. Santa Clara, California – May 3 ,2012 – Sagantec today announced that it has acquired Dutch startup NP-Komplete Technologies BV (Eindhoven, The Netherlands) for its physical design compaction and migration solutions based on a sophisticated 2D dynamic compaction technology. NP-Komplete Technologies (NPKT) is a provider of innovative DFM solutions, and physical design optimization engines. Terms of the acquisition are confidential.

    Having worked with Sagantec over the years, I can tell you a little more of what is going on here. Sagantec has been leading the process migration march since ~1996. That was some 16 years and 10 semiconductor process nodes ago. During that time Sagantec introduced the industry’s first hierarchical compaction/migration tool, they added Cadence Virtuoso, OpenAccess, and Pcell support, they added analog design constraints, etc… Sagantec actually coined the term “process migration” and made it a viable EDA market segment.

    The Sagantec engineering team in the Netherlands is now fully integrated with the NPKT team with the combined team working together on enhancing the tools and addressing future technology challenges.Following the acquisition, NPKT is now a wholly-owned subsidiary of Sagantec and continues to develop and provide advanced layout compaction and DFM solutions.

    The Eindhoven guys wrote the original Sagantec compactor then re-wrote it for Takumi’s DFM products and later spun out to re-write it again for NKP. This perpetual march down the shrinking geometry path has epitomized our industry since Moore “enacted” his law (observation) in 1965, and this trend is not going to go away anytime soon. However, as dimensions shrink further and deeper, each new technology transition seems to be a little more disruptive than the previous ones, presenting new concepts and more difficult challenges for design rule compliance and layout migration. The current 28nm design rules and evolving 20nm technologies are really complex and hard to manage, so adding some innovation and refreshing the compaction engine will help to solve the 20nm puzzles.

    The NPKT migration technology is an automated layout optimization technology, and was designed from the ground up to address the latest challenges of 20nm design rules. Since most of the new rules are enforced to overcome manufacturability-related challenges that impact yield, it takes a sophisticated 2D compaction technology to make necessary modifications to create a DRC clean layout. The NPKT technology has already been proven with DRC clean results at several tier-1 semiconductor companies, and used on multiple 28nm and 20nm technologies of leading-edge foundries. The addition of this new technology and expertise enables Sagantec to better address the new challenges and overcome technology discontinuities that result from the introduction of new layers and new types of design rules associated with the 20nm process node while producing best possible quality results.

    Sagantec will have this and other innovative technologies at the Design Automation Conference in San Francisco next month. Even more importantly, Sagantec will have me in their booth talking about the challenges of 20nm and how the fabless semiconductor ecosystem will continue to thrive in the coming process nodes. See you there!


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    San Francisco Bars

    San Francisco Bars
    by Paul McLellan on 05-08-2012 at 6:00 pm
    Categories: EDA, Events

    If you are visiting DAC and want a drink in the evening then you are in an interesting city and you don’t have to go to a bar just like the ones in the city where you live. Here are a few unique places but take note, most of these places don’t serve any food, they are all about the drinks:

    Bourbon and Branch. It is an old speakeasy. You have to make a reservation on their website and they will tell you where the bar is and what the password is. You then have to ring the bell at an unmarked door and give the password. OK, a bit hokey, but they have incredible cocktails. In fact, the real old speakeasy with secret exit tunnels is downstairs (they might take you on a tour if you ask). It’s actually on the corner of O’Farrell and Jones. There’s a bar next door called the Library where you don’t need a reservation (and you can exit through it via a secret bookcase from B&B itself). No food.

    Smugglers Cove. 650 Gough Street. Over 300 rums and the best rum cocktails around in a fantastic tiki-type atmosphere. Make sure you take the address, they don’t really have a sign outside and it is just a regular store-front, so it is hard to find the first time. Look for a red and a green navigation light. #19 on Drinks International 50 best bars in the world 2011. TheJet Pilot is my favorite drink. No food but there are lots of places if you walk down the hill. Open until 2am.

    Tommy’s. 5929 Geary (near 23[SUP]rd[/SUP] Avenue, so yes, a long way from downtown on the 38 bus). OK, if rum is not your thing but tequila is then you’ll love Tommy’s. A carefully chosen selection of tequila. The tequila menu is here. Ignore the restaurant and head for the bar. Julio (Tommy’s son) will give you a tequila education. They were the first bar to switch to 100% agave Tequila…35 years ago. They have some Cuervo Gold but won’t sell it to you, they just have it for educational reasons to show you why you shouldn’t drink it! #30 on Drinks International 50 best bars in the world 2011. They also make the classic Tommy’s margarita. Mexican food. Closes on Tuesdays and at 11pm on other days.

    Toronado. 547 Haight Street. Beer lover’s paradise with about 60 beers on tap including many rare ones. The up-to-date list is here. They have some seats but you probably won’t get one. Cash only, but you won’t need much, the prices are low. No food, but you can order sausages in the store next door and they’ll bang on the wall when they are ready, or lots of other choices on Haight Street. Open until 2am.

    Black Horse London Pub. 1514 Union Street. The opposite of Toronado, no draft beer at all. Microbrews served out of a tub of ice. The smallest bar west of the Mississippi apparently. Only fits about a dozen people. Go early or you will be lucky to get in. It’s cosy but everyone is really friendly when I’ve been there. No food, obviously (no room for a kitchen) but lots further along Union Street. Open until midnight.

    Zeitgeist. Corner of Duboce and Valencia. About 50 different beers on tap. Huge beer garden out the back where there are lots of people smoking. And I don’t mean cigarettes. Many cyclists and bike messengers go here, they have a huge bike-rack in the beer garden. They have really good hamburgers and sausages and sometimes the Tamale Lady is around. Cash only. Open until 2am. They get incredibly busy on sunny weekend afternoons.

    Also see the bars near Moscone (after the restaurants).

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    Is PHY IP really strategic? Just take a look at the various legal offensives running these days…

    Is PHY IP really strategic? Just take a look at the various legal offensives running these days…
    by Eric Esteve on 05-07-2012 at 12:02 pm
    Categories: IP

    Last week, at the same time I was writing a blog about PHY IP market, claiming that this market was shaken, several events happened – not on the pure business side, but on the legal side. This means that I will have to carefully check before using each word of this blog!

    If you remember, the blog conclusion was focusing on V Semiconductor, a start-up created in 2008, founded by former Snowbush’ employees, who decided to leave the company short after acquisition by Gennum. In the meantime, V Semi has launched a revolutionary SerDes, revolutionary because it is based on a digital PLL and not on oscillator PLL or even on LC tank PLL, and the technology has been implemented on Intel 28nm technology to support multi-standard protocol PHY, to be used by FPGA start-up, and probably acquired by customers developing 10G Ethernet PHY. This technology looks so attractive that V Semi was about to be acquired; by which company? Considering the on-going legal battle, I am sure you will forgive me to stay quiet about this… and call it “Company A”. But, if you want to know more about the, now previously, expected buyer, you can go on Law360 website, and try to figure out which company it could be. So we are now at late 2011, V Semi founders are finalizing the discussions with “Company A”, a letter of intent is written for an acquisition to be closed on February the 14[SUP]th[/SUP] of 2012. At the same time, Semtech, a fabless company, is also finalizing the discussion with Gennum, in order to acquire the company…

    So far, these were usual moves happening in the Semiconductor and design IP industry, merger and acquisition (M&A) are pretty frequent on this fast moving market. The surprise comes when Gennum decides to sue V Semi, filling a Canadian lawsuit on February 3, 2012, against V Semi. As we did not have a chance to read this lawsuit, we prefer not to comment it! But the immediate result is that the company being engaged in the process of buying V Semi has decided to pull its offer.

    It seems that the legal battle field can also be an extension of the more classical competition, where companies are fighting for market share by using marketing and sales forces. Can we say that this Semtech vs V Semi case is such an example? It’s probably too early to know the reality behind this legal battle. Nevertheless, V Semi management has reacted like if the initial (legal) attack from Semtech was just a way to keep away the industry of using V Semi revolutionary SerDes, as they have, on April 26 filled a $150 million lawsuitagainst Semtech, the former Gennum CEO, as well as a person who was in charge of due diligence about V Semi, when working for another company (Company B in V Semi case) when this “Company B” was thinking about buying V Semi technology!

    I remember when I was far younger, watching “Dallas” serial at TV. Looking at what is happening today in the SC and IP industry make you feel that Dallas is a fairy tale for five years old kids, when comparing!

    That’s all for today…but I will stay tuned, as I guess that this is not the end of the PHY IP real saga!

    By Eric Esteve from IPnest

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    Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ Verification IP

    Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ Verification IP
    by Eric Esteve on 05-07-2012 at 3:17 am
    Categories: IP, Synopsys

    Synopsys is consolidating the company positioning on Verification IP. We have announced the launch of Discovery VIP in Semiwiki, in February this year, and we have commented about the acquisition of nSys and ExpertIO in January. This webinar, “Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ Verification IP”, to be held on May, 8 at 10am PDT, will allow the audience to better understand Cache coherency management problematic. Traditionally, cache coherency management has largely been performed in software, adding to software complexity and development time. With AMBA 4 ACE, system level coherency is performed in hardware, providing better performance and power efficiency for complex SoC designs. However, this shifts much of the complexity of verify cache coherency to functional verification.

    This webinar begins with a short overview of the challenges of verifying a coherent design and goes on to show how the features and architecture of Synopsys’ new Discovery Verification IP helps overcome these challenges to simplify the verification of ACE designs.

    The ever growing design time spent in verification, we have recently read figures of 70% of the overall hardware design effort being associated with the verification, is creating a demand for most efficient EDA tools, and accurate Verification IP (dedicated to a specific protocol).

    The next picture is useful to understand the cost breakdown associated with Verification. If you look at the middle left box, you see a 3X cost (or license count, or resources) increase for almost every task (except “Tool, Support and Service” with 20% only). So, offering a 3 to 6X run time improvement is welcome, to keep the design schedule and consequently the time to market within reasonable limits.

    You can log to this webinar here

    From Eric Esteve from IPnest