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Semiconductor Expert Forum

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TSMC Open Innovation Platform Explained

TSMC Open Innovation Platform Explained
by Daniel Nenni on 11-09-2009 at 10:56 pm
Categories: Foundries, TSMC

Launched in April 2008, the TSMC Open Innovation Platform initiative is a collaborative strategy aimed at breaking the bottlenecks of semiconductor design enablement in order to promote growth for the industry as a whole. The TSMC iPDK Debate: Lets Play Monopoly! blog I did provides more technical detail.

While Wafer count is climbing, an estimated 20M in 2009 to 30M in 2013, semiconductor design enablement (includes Electronic Design Automation-EDA, Semiconductor Intellectual Property-IP, and Design Services-DS) will continue to stagnate and consolidate.

The main reason for the disjointed wafer count increase and design enablement revenue stalling is FPGAs. As programmable devices advance in speed and density, medium-to-small volume projects and emerging technology companies will continue to leverage the low barrier to entry of FPGAs. Wafer count climbs from FPGA vendors such as Xilinx, Altera, and Actel, while ASIC design starts decline.
Other reasons for the ASIC design start decline include:

  • High cost, it takes $50-70M to get an ASIC to market.
  • Increased SOC design density and complexity, the chips are bigger so there are less of them and require many more resources to complete.
  • High mortality rate, an estimated 50% of the ASIC design starts do not make it into production.
  • Less ASIC design starts equals less design experience, less design experience equals higher ASIC mortality rate.


The TSMC Open Innovation Platform promotes timeliness-driven innovation amongst the semiconductor design community, its ecosystem partners and TSMC’s IP, design implementation and DFM capabilities, process technology and backend services. The Open Innovation Platform™ includes a set of ecosystem interfaces and collaborative components initiated and supported by TSMC that efficiently empowers innovation throughout the supply chain and enables the creation and sharing of newly created revenue and profitability. TSMC’s AAA initiative is a critical part of the Open Innovation Platform™, providing the accuracy and quality required by ecosystem interfaces and collaborative components.

The financial goal of OIP is obvious, to reduce waste in the semiconductor design enablement supply chain. People in this industry are accustomed to waste, business as usual, so this is a significant challenge! Jack Harding of eSilicon estimates a 20% waste due to inefficiencies and lack of experience. I say it is closer to 30% if you include the ASIC mortality rate. 20-30% of $50-70M is a significant amount, especially if you are asking a VC for it.

The TSMC OIP targets include the following areas of inefficiencies:

  • PDKs, the iPDK standard is innovation driven versus format driven, which reduces foundry and customer support costs.
  • EDA Reference Flows and tool qualification, verified design sign-off flows reduce both costs and customer learning curves.
  • TSMC IP portal, documenting silicon proven IP from both TSMC and commercial IP vendors such as Virage Logic. Cross distribution deals are also possible.
  • TSMC collaborated services, such as Tela Innovations Power and Area Trim.


The bottom line is that to increase ASIC design starts we must decrease the barrier to entry, we must reduce risk, we must all focus on success based business models:

  • TSMC is certainly success based with wafer pricing but must look at reducing NRE (mask costs) which are in the millions of dollars.
  • IP companies are success based capable with foundry sponsored IP (free to customers), and royalty based IP, but there are still significant up-front licensing fees for leading edge products.
  • Design Services (eSilicon) are definitely success based with per chip pricing for working silicon.
  • EDA is still in the dark ages with yearly subscriptions or all-you-can eat product dump pricing where you pay whether you use it or not, whether you are successful or not.

This was the second OIP conference, it was stocked with executives from TSMC and the design enablement food chain. The keynotes, panels, and discussions were highly interactive, the format and content is exactly what our industry needs to scale and move forward in a profitable manner.

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TSMC versus SMIC

TSMC versus SMIC
by Daniel Nenni on 09-29-2009 at 12:24 am
Categories: Foundries, TSMC

This blog is about the legal battle between TSMC and SMIC which is currently playing in the California court system. Taiwan Semiconductor Manufacturing Corporation (TSMC) and Semiconductor Manufacturing International Corporation (SMIC) do what their names suggest – the manufacturing of semiconductors for an international roster of clients. TSMC touts itself as the first chip foundry, SMIC touts itself as the first China-based chip foundry. TSMC is ranked #1 , SMIC is #4, see my blog TSMC vs Global Foundries for more details on capacity and revenues.

The starting point is illustrated above, where SMIC went from equipment being installed in August of 2001, to qualified production in December 2001. As a point of proof, TSMC referred to the Fab of the Year Award that SMIC received from Semiconductor International in 2003, highlighting the fact that just four months after installing equipment in its fab, SMIC had four processes up and running, manufacturing 18 different products. Adding to that suspicion was the claim that SMIC hired away 100+ TSMC employees that had access to the sensitive process data required to bring a fab to production. To begin the legal discovery process, TSMC analyzed SMIC .18m silicon from a Broadcom product and documented stark similarities to the identical product silicon from TSMC. With discovery came incriminating emails which are a centerpiece of the case.

December 2003, TSMC filed suit alleging systematic intellectual-property (IP) theft and patent infringement by SMIC. Witness testimony indicated:

  • An estimated 90% of SMIC’s 180nm logic process was copied from TSMC
  • SMIC attempted to disguise the origin of the information by internally referring to TSMC and its technology by the code name ‘BKM1′, referring to ‘Best Known Method 1
  • SMIC’s use of TSMC technologies was ‘no secret’ and was openly discussed by SMIC engineers

Email supporting this testimony included exchanges between SMIC COO Marco Mora (a fromer TSMC employee) and then TSMC employee, Katy Liu, asking that she transfer TSMC’s process recipe documents and technical training manuals to SMIC. Proving once again, even very smart people can do very stupid things.

Not surprisingly, SMIC agreed to settle the case in February of 2005. Under terms of the settlement, SMIC is to pay TSMC $175 million over 6 years and the companies have agreed to cross license 180nm patent portfolios through December 2010.

In August 2006 TSMC filed a new lawsuit for more than $130 million alleging breach of the 2005 agreement. TSMC claims: SMIC continued copying TSMC manufacturing technology for newer (130nm) manufacturing processes in SMIC’s fabs, it also developed the advanced 90nm process using TSMC’s know-how.

“SMIC has carried out massive corporate espionage directed by certain [of] SMIC’s top operating officers,” the 31-page complaint said. “SMIC lavishly copied the information it stole from TSMC, word for word, line for line, diagram for diagram, and even typographical error for typographical error.”

In November 2006the High Court in Beijing accepted SMIC’s filing in which it claimed TSMC had intentionally disseminated untrue and misleading statements to damage SMIC’s reputation and goodwill.

TSMC “rather than competing fairly in the marketplace, have undertaken a concerted effort to infringe SMIC’s legal rights unfairly,”

TSMC filed in California for a reason, California has significant case law in regards to protecting intellectual property. SMIC filed in Bejing for a reason, China has scant case law in regards to intellectual property. It will be interesting how the Bejing and the California court proceedings compare. The California trial, which began this month, is expected to last 50-60 days, and is being broadcast by the Courtroom View Network. Trial updates will be available via my Twitter: DanielNenni

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TSMC Versus Global Foundries

TSMC Versus Global Foundries
by Daniel Nenni on 09-13-2009 at 11:46 am
Categories: Foundries, GlobalFoundries, TSMC

The big news last week was Global Foundries’ (GFI) agreement to acquire Chartered Semiconductor (CHRT) for $3.9B, but what does it really mean to the semiconductor world in total?

CurrentlyTSMC has 11 fabs producing wafers, 8 in Taiwan, 1 in Shanghai, 1 in Singapore, and 1 in Washington State. After the acquisition, Global Foundries will have Chartered’s 6 fabs in Singapore, AMD’s fab in Dresden with 1 more fab under construction in Dresden and another under construction in upstate New York, so 9 fabs in total.UMC has 10 fabs, 8 in Taiwan, 1 in Japan, and 1 in Singapore, and SMIC has control of 11 fabs in China. The ranking numbers above are clearly disjointed, UMC is #2 with 10 fabs, while SMIC is #4 with 11 fabs?

Unfortunately capacity does not guarantee economies of scale: TSMC owns 50% of the foundry market revenue and 80% of the profits, UMC is second with 12%, GFI, SMIC, and CHRT have yet to show a profit. Why are these numbers disjointed you ask? Wafer yield (good die per wafer) is important of course, yield is secret however, but from personal experience, TSMC is the top yielding foundry and these numbers support that.

Just as important is foundry wafer pricing, which, interestingly enough, is determined by the customer, more often than not. TSMC is considered a first source for semiconductor manufacture, UMC, CHRT, and SMIC are considered second sources, meaning that leading fabless semiconductor companies work with TSMC first, then replicate manufacturing at the other foundries. TSMC has the most advanced process technologies and the most skilled people so they are an easy first choice, reducing the risk of introducing a new product, and getting it to market as early as possible. Once the product is ramped on a TSMC process, wafer price becomes the central issue and the cutthroat negotiation with other fabs begin. Second and third sourcing also has fault tolerance built in, just in case Taiwan has a natural or unnatural disaster.

The foundry business challenge is to make their manufacturing processes sticky, focusing on customer retention, enabling a premium pricing strategy. Believe me, this is a key part of TSMC’s overall corporate strategy, a very deep customer loyalty program. Examples include:

  • Semiconductor design enablement programs, TSMC spends millions of dollars every year ensuring Semiconductor Design and Manufacture Predictability.
  • TSMC has a closely coupled services group in Global Unichip Corporation, which competes with the fabless ASIC companies mention in my blog: EDA is Dead.

Can GFI compete head-to-head with TSMC? Not now, and probably not ever. GFI’s United Arab Emirates based financial backing is a key selling point, deja vu of SMIC which is backed by the Chinese government but has yet to show a profit. GFI’s competitive advantage today is that they are not TSMC, for those who fear a foundry monopoly. Who knows what tomorrow will bring but based on my knowledge of the GFI executive staff, expect an innovative and sticky approach to the foundry business.

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Semiconductor Wafer Allocation and Design Migration

Semiconductor Wafer Allocation and Design Migration
by Daniel Nenni on 08-12-2009 at 8:00 pm
Categories: EDA

In the name of blogging and increased transparency lets talk about wafer allocation, because it’s coming, believe it. There is already a significant delta between wafer demand and manufacture due to record low inventory levels and the exploding semiconductor demand in China. Both TSMC and UMC posted good July sales numbers: TSMC realized a 17.9% jump from June, UMC a 6.97% jump. In difficult economic times the strong get stronger, as TSMC definitely has, as the 2009 market share data will definitely show.

Instead of favoring large customers at the expense of smaller ones, foundries will look at a customers’ forecast accuracy as a basis to judge which could most likely afford less wafers. So an allocation will run across most semiconductor market segments around the world.

This of course spells opportunity for second source foundries (UMC, SMIC, Chartered Semi, Global Foundries), but the key questions are: Where will customers get the already thin engineering talent to migrate design layout to a second source? Will second source foundries offer migration services? Will the customers do it in-house? And unless it is a highly automated process, will the actual migration take longer than the allocation?
Several of the top semiconductor companies already use second, and even third source manufacturing due to the massive volumes required. Most companies use home-made scripts that manipulate layout then use brute force layout design work to cleanup the remaining mess. With new process nodes however (65nm & 45nm), these methods break as the process rules are much more complicated. Commercial tools for the “automated layout modification” required for second sourcing semiconductor designs can yield a 5-10X productivity increase, saving both time and precious engineering resources.

Michael Reinhardt literally wrote the book on this and pioneered the design migration market with his company RubiCAD. Unfortunately RubiCAD’s erratic business practices were not scalable, forcing the company to fold in 2004 after a debatable patent challenge by an unknown company. The dominant player in this market is Sagantec, which I worked for back in the late 1990’s, so I know this business the hard way.

Sagantec, known for giving away nice shirts at trade shows, is a true EDA survivor. Originally a European based research and development operation, Sagantec emerged as a commercial EDA company backed by Isreali venture funds, now with headquarters in Silicon Valley, development in the Netherlands, and sales/support offices in Japan, Taiwan, Korea, and India. Once valued at $50M+, Sagantec got trampled during the DFM gold rush and was forced to clean house in 2008. Now completely remodeled and refocused on the mixed signal / custom IP migration market, Sagantec is profitable, has a healthy backlog, and counts top fabless semiconductor companies and IDMs asactive customers. Case in point from the Sagantec #46DAC demo:

Unfortunately, moving a mixed signal design or custom IP to different foundry process nodes is not, and will never be a trivial matter. This is an extremely difficult job that will require a broad range of experience in design, migration, as well as process technologies. In fact, 80% of the challenge is the technology set-up file, the rest is push-button iteration, improving quality of results. If you think about it, which I have, the mixed software licensing and services model is key here, as well as a gain-sharing business model.
Contact Sagantec for more details and a nice shirt!

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Semiconductor IP Companies Still in Play

Semiconductor IP Companies Still in Play
by Daniel Nenni on 07-03-2009 at 12:05 am
Categories: IP

A recent EETimes article about memory IP vendors reminded me to follow up on my blogs about IP companies, which I believe are the best investments in semiconductor design today. It is a fluff piece, Mark LaPedus briefly mentions ARM, Synopsys, Virage Logic, and Denali, but his analysis is right on the mark. There is definitely money to be made in the semiconductor design enablement market, on companies with scalable (gain share) business models of course.

ARM has alienated the semiconductor foundries due to aggressive and sometimes questionable business practices. If and when there is a comparable product available, ARM will lose out, due to their arrogance more often than not. Intel is aggressively targeting the embedded processor business so I’m long term short on ARM. As I mentioned in “Wall Street Hates EDA” Synopsys is giving away IP, stifling innovation, and is treating the Semi IP market like a cat does a sandbox.

Memory interface innovation is driven by Virage Logic, Virage pioneered it and continues to do so. Denali’s strength is memory modeling, marketing and business relationships. Who here hasn’t been hung-over after the annual Denali DAC party at least once?

In additional to memory interfaces, Virage now offers connectivity interfaces such as DDR (acquired via Ingot), PCIe, HDMI, MIPI, with others to follow no doubt. Licensed from AMD and silicon proven at TSMC by the ATI graphics group, Virage will technically dominate the interface IP market at 40nm and below. With cash in the bank, a relentless executive staff, and a new hybrid direct/indirect sales strategy, Virage is poised for stellar growth when 40nm hits full production and will continue at 28nm and below. The gaping hole in the Virage strategy is Verification IP (VIP), the software used to validate not only the IP but the successful integration of that IP into a design. Both Denali and Synopsys have VIP, as does Cadence and Perfectus, but only Denali and Synopsys can do the total IP sell today.

Denali founded commercial memory modeling in 1996 and has evolved as one of the most successful privately held Semi IP companies of our time. The gaping hole in the Denali strategy is physical IP, SRAM, Logic, and IOs, the building blocks of modern semiconductor design. Foundries work closely with the physical IP companies on emerging nodes and silicon validation. This type of trusted partnership can be leveraged into the top semiconductor companies around the world, Virage Logic is TSMC’s 40nm early development partner. At a minimum Denali should aggressively OEM the TSMC physical IP to stay foundry close. Denali is also direct sales centric which will limit the active customer base and is not scalable in this ultra competitive market. A little inorganic growth wouldn’t hurt either, maybe pick up a fabless ASIC vendor? There are plenty of those around.

Semiconductor IP is being outsourced at an alarming rate and everybody is or has been a Virage Logic customer by some degree. Virage is currently trading under $5 per share, has a market cap of $100M, and has $2.432 total cash per share. Watch for a good quarter, a good advisory, and the upgrades will fly, believe it. This is easily a $10 stock after the economic recovery.

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EDA is DEAD

EDA is DEAD
by Daniel Nenni on 05-23-2009 at 12:12 am
Categories: EDA

Years ago I bought my ancestral home, the house where my beloved grandparents lived, the place in which I grew up. It was more an emotional investment than a financial one, much more. After completely renovating it with my keyboard hardened hands, reliving much of my childhood, I joined the ranks of the slum lords and rented the house out to complete strangers. Thanks to ungrateful renters, inconsiderate neighbors, and a vindictive housing inspector, there are no thrills left whatsoever, just tedium and frustration. Blogging about EDA is much the same, the roller coaster excitement is pretty much over, now it is more of a carousel ride, so yes the EDA I once knew is dead.

EDA really came into its own with the advent of the fabless semiconductor manufacturing model pioneered by companies like VLSI Technology and LSI Logic. Using excess Japanese manufacturing capacity and building its own fabs locally, they built Application Specific Integrated Circuits (ASICs) and offered ASIC services for emerging fables semiconductor companies. A few years later TSMC introduced the pure-play foundry model promoting manufacturing efficiencies and commercially available EDA software. At that time semiconductor manufacturing processes were very different and could be exploited for competitive gains, re-usable Semiconductor IP was in its infancy, so the value proposition of EDA software was clear and present. Today, unfortunately, that is no longer the case. Commercial Semiconductor IP dominates the area of an ASIC and designs can be moved to second and third source foundry partners with little or no change. The biggest design challenge now is adapting to the new process geometries which requires hands-on experience.

The fabless ASIC Services business re-emerged in the year 2000 starting with eSilicon, followed by VeriSilicon, Alchip, Open-Silicon and a whole host of others. It has been a long, hard road with fierce competition (even coming from the foundries themselves with Global Unichip and Faraday). Honestly I did not see the long term value proposition back in 2000 but clearly it is here today. ASIC services can cut total costs by one third and significantly reduce the internal risk of designing to a new geometry. You can also minimize front end expense (IP/NRE) and back load the cost on a per packaged chip pricing agreement.

So where does that leave EDA? Venture Capital has left the semiconductor, IP, and EDA market segments so budgets are a fraction of what they once were. ASIC design starts are rapidly declining, EDA innovation is stalled, and ASIC Services companies are multiplying like rabbits. What else are unemployed ASIC designers going to do, work at Starbucks? Not to mention a smattering of foundry created EDA tools now hitting designer’s desks, which is understandable. As manufacturing processes become commodity, foundries will use proprietary EDA software and design enablement services to support their wafer value proposition. Bottom line: the ASIC Services market is $1B+ today and projected to exceed $10B by 2015, EDA on the other hand is a flat $4B industry that is still living in the house it grew up in.

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Jim Cramer’s CNBC Mad Money on Cadence!

Jim Cramer’s CNBC Mad Money on Cadence!
by Daniel Nenni on 05-15-2009 at 6:10 pm
Categories: Cadence, EDA

For those of you who follow the market and play EDA stocks this will be a shocker! Jim Cramer, former Hedge Fund Manager, co-founder of TheStreet.com, and host of the CNBC’s Mad Money did a piece last week on Cadence. Apparently he did NOT read my piece on EDA being DEAD:


Cramer’s Wednesday “Tech Spec” pickswas Cadence Design Systems(CDNS Quote), which he said could follow Taiwan Semiconductor’s(TSM Quote) 27% rise since he’d last recommended that stock.

Cramer led off his show with stocks that have been“busted down to private, dishonorably discharged, beaten down stocks from some of the most tarnished companies”.

CADENCE!

Cramer said“Cadence doesn’t have much competition in its business of making tools that help create smaller, faster microchips.”

CADENCE?

Oh Jim, and you started off so well! EDA is one of the most competitive, cut throat industries known to man. In fact it’s a flat $4B market due to just that. Magma’s proverbial pricing pants are still around their ankles.

Cramer says” its management made big mistakes in 2008, but that’s all in the past, and the company has a new chairman and CFO who’s been buying shares.”

FISTER!

How about mistakes made 2004 through 2008! Good at collecting shoes, bad at running an EDA company, Michael J. Fister.

If you looked at the company’s 2008 performance. The exhaustive list of what went wrong would have been enough to scare off even the most daring of stock speculators. Investors would have seen tons of risk and virtually no chance for reward.

CADENCE!

Also, “companies tend to renew contracts with their EDA client of choice 99.9% of the time, so Cadence rarely has to worry about losing clients.”

CADENCE?

According to Synopsys and Mentor sales insiders they are picking off Cadence customers like Somalia pirates in a life boat! (Too soon for that?)

What about the bad stuff? Here’s one point: This is a $5 stock, and share prices don’t drop that low for no reason. Cadence fell from about $17 in early 2008 to $3.66 by year’s end. In between, the company’s 30.5% 2007 operating margins dropped to –3%, management was fired, the Nasdaq threatened a delisting for failure to file a 10-Q for the September quarter, and an accounting probe caused a delay in SEC filings. Worst of all, Cadence changed some of its own accounting procedures, and that made revenues look lower than they actually were.

CADENCE!

The next logical question then is, why on earth would anyone want to buy this stock? Well, because Cramer sees the beginnings of a turn. Cadence beat Street earnings estimates when it reported on April 29. And while the company is still losing money, execution improvements seem to indicate that next quarter’s revenue and operating margins will be up.

CADENCE?

Clearly Jim Cramer does not understand the EDA market but his short term financial analysis is fair at face value. I’m bullish on Cadence but for different reasons. For me there are (5) data points why Cadence will regain its value in the long term:

(1) Lip-Bu Tan, knows finance and EDA, has the golden touch, so confident that he bought CDN stock to augment his options for a total of 551k shares.
(2) Charlie Huang is definitely one of the top 10 executives this industry has ever seen. Charlie also bought CDN shares in December, his total is 344k.
(3) Chi-Ping Hsu , a pioneer of IC physical design (implementation) and customer relationships. Implementation has always been the jewel in the crown of EDA and the primary driver of semiconductor design methodologies.
(4) Jim Hogan, the God Father of EDA, rumor has it Jim Hogan will re-join Cadence. If so, look for some aggressive M&A activities in the near future, offers they can’t refuse.
(5) Cadence holds $2.20 of cash and equivalents per share so they have a decent bank roll to work with.

My personal opinion is that Jim Cramer is in fact an “infotainer” and prone to pump and dump groupies, in regards to CDN however he got lucky, for a long term play.