What I’m really describing here is an over-simplified backend flow for physical design of low power ICs with multiple voltage domains. If you haven’t ventured into this territory yet, this will hopefully give you some food for thought. Here are the basic steps:
Step 0 Commitment – Are you really sure you want to MV? Are you positive that multi-Vt & clock gating would not help with your power budgets? Proceed to step1 with caution only if you really must.
Step 1 Architecture Selection – Ensure that the architecture is frozen and capture all the power constraints required for the chosen MV style in the UPF file. As most of you are aware this can also be done using the other power format but we will stick to UPF as it simplifies interoperability.
Step 2 RTL Synthesis – Using the UPF file, complete RTL synthesis and derive the gate-level netlist. Ensure that the simulation & verification runs are complete and validated.
Step 3 Data Import – Import LEF, lib, SDC, Verilog, and DEF. Properties that are relevant to the multi-voltage design flow are:
• Special cells in Library (always_on, is_isolation_cell, is_isolation_enable, is_level_shifter)
• Corner & modes – Define appropriate modes and corners for the different domains. Ensure that the worst case timing and power corners are setup correctly to concurrently optimize for power & timing.
Step 4 Power Domain setup – Read the power domain definition by sourcing or loading the golden UPF file (same that was used for RTL synthesis). After reading the UPF file, the following items will be defined:
• Domains with default power and ground nets
• Power state table to define all possible power state combinations
• Level shifter and isolation rules for the different voltage domains
Step 5 Floorplanning – Create physical domains and the corresponding power structures for each individual supply net defined in the UPF. Define domain-specific hierarchy mapping and library association based on the architecture. Insert power switches for domains that are shut down (either VDD or VSS gated).
Step 6 Power Domain Verification – Perform design checks for general design and UPF setup, verification of level shifters and isolation cells, and analysis of always-on connections. The intent here is to help you find any missing UPF or power domain setup data that could lead to potential misery.
Step 7 Pre-CTS Opt – During the Pre-CTS flow, ensure that no port punching occurs on power domain interfaces. The optimization engine should use the power state table (PST) when buffering nets in a multi-voltage design to automatically choose always-on-buffers or otherwise. Nothing much you can do since you are the mercy of the tool.
Step 8 CTS – During CTS, ensure that no port punching occurs on the power domains interfaces. Like the optimizer, the CTS engine should also use the PST-based buffering solution to determine the type of buffers to use while expanding the clock tree network. Some clock tree synthesis flows require special clock gate classes to be recognized in order to restrict sizing operations during CTS to equivalent class types. Have you been nice to your R&D lately?
Step 9 Routing – Ensure that the routing engine honors the domain boundaries and contains the routes within them. Secondary power pin connections for special cells such as always-on buffers and level shifters should also be handled using special properties set on the power pins. Many design flows also require double vias and non-default width wires for routing of the secondary power connections. Top level nets that span across domains can be handled using gas stations to help optimize timing and area. Hail Mary…
Step 10 Hope and Pray – This step is optional. If your chip is DOA start from step 0 and repeat until you either have a working part or are unemployed.
–Arvind Narayanan, Product Marketing Manager, Place and Route Product LineShare this post via: