I was at the first half of Magma’s Silicon One event yesterday. The first keynote was by Rajeev about the environment for SoC designs, especially fabless startups, and Magma’s role going forward. More about that later. The other keynote was Jack Harding, CEO of eSilicon. As usual Jack did his presentation without any powerpoint slides, something I find very difficult to do without losing my thread.
Jack started off with some statistics about eSilicon. They have been in existence for just over 10 years now and have done over 200 parts. A 3rd party audited them for a customer and decided that they had a 98% first time hit rate. For those who don’t know eSilicon, their business model is to be an ASIC company although they don’t have a fab. But they are more than a design house. They deliver tested, packaged parts just like an ASIC company with a fab, except that they let you put your own logo on the parts. At VLSI, for example, we always put ours on (look at any pictures of motherboards of early Macs).
The big change that Jack wanted to talk about was the consumerization of SoCs, and the effect that this is having on the design chain. Design used to be “all” digital, with a smart group of slightly eccentric designers down the hall (or in a separate company) who used spice and a layout editor and their bare hands to wrestle analog to the ground. Analog was something nobody worried about.
In the 90s, the strategy was to make it a separate chip. That way it could be done in an older process. So a system might be 4 digital chips and an analog chip that was either a standard product or designed and manufactured in a separate process.
But now all that is condensed into a single SoC with all the digital, and lots of it, and all the analog, and lots of it, on a single chip. This is a problem and an opportunity. eSilicon has historically, for business reasons, been more focused on networking than consumer and over half their chips had a serdes on. Today virtually every chip they do has hundreds of lanes of serdes. There are now so many variables to make the analog work that it is incomprehensibly by a human. So it is going to have to get more automated whether the designers like it or not, just like when place and route first arrived and designers figured they could do better. For a few gates, yes, but for thousands it is just impossible.
Even picking the IP is an intractable task. TSMC has 12 flavors of 28nm process and 40 different commercial lilbraries available (from them and 3rd parties) so that’s 480 combinations just there.
Jack was asked in the questions what EDA companies don’t design the chips for at least some of their customers. He thought that this made a lot of sense but there are big problems with the way Wall Street values EDA companies (many types of companies with mixed product lines, such as HP, have this problem too). To combine an eSilicon type business with Cadence type business (and remember Jack was CEO of Cadence too) would mean going for 95% software margins to 45-50% semiconductor margins and nobody knows how to value a company that mixes those two business (one reason VLSI spun out Compass when I was there was for that Wall Street got confused at companies with mixed product lines like that). So right now it is good business for eSilicon but clearly a potential slot for EDA to step up and provide themselves. But of course that would mean they only get paid of the tools work…
Which leads to the next question: why is EDA just a $4B business? Jack’s view is that it is a flaw in the EDA business model whereby EDA charges for a capability regardless of success. Everyone else is at risk. If a chip doesn’t go to production, no wafers are bought, no parts are packaged, nothing is tested and nobody makes any money. Except EDA. But the quid pro quo is that if EDA is not going to take that risk then it capped at $4B (in fact, excluding IP, it is probably shrinking). In the early days, EDA had a hardware business model (Calma, Applicon etc) and this model made sense. The software was thought of almost as an add-on to sell the hardware. But 15-20 years ago that stopped making sense. Jack’s estimate is that if EDA had switched to take risks on a variable basis then it would be a $40B business. More chips could be made, probably with a higher percentage failure rate (as business lines, not necessarily technical) but much more volume in total.
But he wouldn’t want to be the first CEO to make the switch. Wall Street would punish you for 2-4 years until the first designs in a new process node went from EDA software development through design to volume production. The challenge is how to find a way to switch without blowing up the existing business model completely. Jack said that they have done a few small deals where eSilicon + EDA company + customer on basis of long-term royalty. Possibly a good candidate to grow.
So the takeaway is that things need to be looked at differently before. The only way to get these designs done is to be very silicon aware, work with EDA partners, silicon partners, test and assembly and so on. This is leading to re-aggregation of supply chains since someone needs to take responsibility for everything. After all, if a package is broken then the foundry isn’t getting any wafer orders even though it isn’t their fault and vice versa. For the designs they do, eSilicon takes that responsibility and they invest a lot in communication and staffing for process people, manufacturing people, test people, package experts and so on.Share this post via: