MIPI Alliance introduces C-PHY, Synopsys launch C-PHY VIP

The set of MIPI PHY specifications has enlarged during last night, as theMIPI Alliance has introduced the new C-PHY spec on September 17th, a physical layer interface for camera and display applications. “The MIPI C-PHY specification was developed to reduce the interface signaling rate to enable a wide range of high-performance and cost-optimized applications, such as very low-cost, low-resolution image sensors; sensors offering up to 60 megapixels; and even 4K display panels,” said Rick Wietfeldt, chair of the MIPI Alliance Technical Steering Group.

The next day, Synopsys has released a new Native SystemVerilog-based MIPI C-PHY Verification IP to help enable engineers to verify interfaces such as MIPI CSI-2 v1.3, which includes the MIPI C-PHY. The MIPI MIPI C-PHY™ specification uses three-phase digital coding techniques. This means that a chip integrating MIPI C-PHY will use 3 pins to form 1 unidirectional lane (in fact a trio), the clock being embedded. Thus we don’t speak any more about Gb/s (Giga bit per second) but Gsym/s (Giga symbol per second), the symbol being formed by the lane trio. When a differential signaling technique (like for MIPI M-PHY) uses two wires to carry one symbol equal to one bit (minus the encoding, for example with 8b/10b, only 0.8 bit), the MIPI C-PHY will use three wires to carry one symbol equal to 2.28 bits. The benefit is that you reach (about) the same bandwidth with a MIPI C-PHY running at 2.5 Gsym/s on 3 wires than with a MIPI M-PHY running at 5.8 Gb/s on 2 wires. Designing at lower frequency (in this range) is probably easier, and the 2.5 GHz lane should generate less perturbation than the 5.8 GHz… don’t forget that the first application is mobile phone, thus avoiding to perturb RF signals can only be good!

Synopsys providing the MIPI C-PHY Verification IP the same day the specification is introduced is already great news. But another PR was launched the same day: Synopsys has released the MIPI D-PHY v1.2, running up to 2.5 Gbps per lane, or an aggregated data throughput of up to 20 Gbps for high-resolution imaging applications. According with Synopsys, this new “MIPI D-PHY is 50 percent lower in area and power compared to competitive solutions, reducing silicon cost and extending battery life”. There is also an interesting quote from Sean Mitchell, senior vice president and COO at Movidius, saying that “The DesignWare MIPI D-PHY offered low power consumption, high performance and configurability options that were critical to the success of our Myriad 2 Vision Processing Unit”. If you take a look at Movidius web site, the Myriad 2 Vision Processing Unit targets the following applications:

• Smartphone / tablet cameras
• Wearables, action cameras, and electronic eyewear
• Embedded devices (home automation, industrial, and robotics)

If using MIPI D-PHY for Smartphone and Media Tablet looks pretty obvious, listing other applications like wearable and embedded devices is very interesting: MIPI technology is going outside of the mobile phone (or tablet) industry! In fact, we expect such information to become more common in the future. The benefits coming with MIPI technology usage like better power/bit efficiency, interoperability or availability of Off-The-Shelf ASSP running in 100’s million units in production (with a positive impact on price) should make MIPI powered IC a very attractive solution for wearable, IoT and embedded devices!

I was about to miss the latest, but not least, MIPI related PR released the same day by Synopsys: “Leadcore Achieves First-Pass Silicon Success with DesignWare MIPI IP in Smartphone Application Processor SoC”. In fact Leadcore is a chinese Application Processor SoC maker, targeting a market which is probably the most competitive on a world-wide basis today, the Chinese mobile market.

“With the tight time-to-market windows in the mobile market, we needed an established IP supplier that would provide high-quality and reliable solutions,” said Dijun Liu, vice president, Leadcore Technology. “We successfully integrated the DesignWare MIPI IP into our design within two weeks, letting us focus our efforts on the differentiating portions of our design. The DesignWare IP helped us meet our project schedule and improved our product’s time-to-market. We fulfilled our customer’s requirements by using DesignWare IP from Synopsys.”

The MIPI specification integrated into Leadcore INNOPOWER LC810 is DesignWare MIPI D-PHY, compliant to the MIPI D-PHY interface specification v1.1, supports up to 1.5 Gbps and is configurable for host or device applications. So, if we summarize, Synopsys has launched Verification IP for MIPI C-PHY, compliant with MIPI CSI-2 v1.3, released the MIPI D-PHY v1.2, running up to 2.5 Gbps per lane, or an aggregated data throughput of up to 20 Gbps, and shared a customer success story, the Leadcore LC810 integrating MIPI D-PHY v1.1… We understand this quote from Joel huloux, chairman of the board of MIPI Alliance, “Over the last 10 years, Synopsys has played an active role in MIPI Alliance working groups, contributing to the development and proliferation of MIPI Alliance technology,” as Synopsys investment into MIPI technology is clearly strong.

Eric Esteve – See “MIPI IP Survey & Forecast” from IPNEST