Power-Aware Verification in Mixed-Signal Simulation

Power-Aware Verification in Mixed-Signal Simulation
by Daniel Payne on 11-10-2014 at 7:00 am

My Samsung Galaxy Note 2 phone lasts about 1.5 days on a single battery charge, thanks in part to the clever power conservation approaches like when the screen is automatically dimmed then turned off after no activity. Mobile phones and many other battery-powered devices used today all need power-saving designs, which then means… Read More


Full-Chip Electromigration Analysis

Full-Chip Electromigration Analysis
by Daniel Payne on 10-10-2014 at 7:00 am

I’ll never forget debugging my first DRAM chip at Intel, peering into a microscope and watching the aluminum interconnect actually bubble and dissolve as the voltage was increased, revealing the destructive effects of Electromigration (EM) failure. That was back in 1980 using 6 um, single level metal technology, so imagine… Read More


Xilinx picks another winner…

Xilinx picks another winner…
by Luke Miller on 07-31-2013 at 7:00 pm

Just as important as block RAMs, IO and DSP48’s is what interconnect or fabric is going to be used when considering SoC FPGA designs. I think Xilinx has found the winning combination. What is paramount to the new SoC FPGA methodologies is not only the challenge of moving huge amounts of data around; we are now to consider data… Read More


High Frequency Analysis of IC Layouts

High Frequency Analysis of IC Layouts
by Daniel Payne on 10-03-2012 at 12:26 pm

IC designers of passive devices often use empirical approaches to perform High Frequency Analysis (HFA), however there is at least one new approach being offered by Mentor Graphics using a tool flow of:

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