High-End Interconnect IP Forecast 2022 to 2026

High-End Interconnect IP Forecast 2022 to 2026
by Eric Esteve on 12-04-2022 at 10:00 am

TSMC Revenue by Platform 1Q22 1

The Interface IP market has grown with 21% CAGR from 2017 to 2021 and we review the part of this market restricted to the high-end of PCIe, DDR, Ethernet and D2D IP made of PHY and controller targeting the most advanced technology nodes and latest protocol release. We will show that an IP vendor focusing investment on the high-end interconnect… Read More


Samsung Versus TSMC Update 2022

Samsung Versus TSMC Update 2022
by Daniel Nenni on 12-02-2022 at 6:00 am

TSMC Versus Samsung

After attending the TSMC and Samsung foundry conferences I wanted to share some quick opinions about the foundry business. Nothing earth shattering but interesting just the same. Both conferences were well attended. If we are not back to the pre pandemic numbers we are very close to it.

TSMC and Samsung both acknowledged that there… Read More


AMAT and Semitool Deja Vu all over again

AMAT and Semitool Deja Vu all over again
by Robert Maire on 11-24-2022 at 6:00 am

Lam SemiWiki SemiSysco

-Lam/Semisysco is a repeat of AMAT/Semitool
-Adds wet processing that larger companies lack
-Semisysco tools amazingly similar to those made by Semitool
-Lightning strikes twice for Ray Thompson

Deja Vu all over again

In a clear example of history repeating itself, Lam Research bought Semisysco, a company founded by Ray Thompson,… Read More


A Perspective on Semiconductor Manufacturing Initiatives & Strategies

A Perspective on Semiconductor Manufacturing Initiatives & Strategies
by Sagar Pushpala on 10-17-2022 at 10:00 am

A Perspective on Semiconductor Manufacturing Initiatives

My name is Sagar, and I’ve been a long-time executive in the semiconductor manufacturing world — holding key positions at large multi-nationals, a leading semiconductor foundry, and partnering with many of the top-tier foundries and OSATs. Since “retiring”, I’ve also spent time advising and investing in start-ups through Read More


Chip Train Wreck Worsens

Chip Train Wreck Worsens
by Robert Maire on 10-16-2022 at 4:00 pm

Train Wreck Semiconductors 2022

-Semi Equip go from bad to worse as TSMC cuts capex
-Numbers will be slashed for December quarter
-So far just a handful of exceptions to blockade but temporary
-China’s response could be very ugly

Fast motion train wreck

Just when some people thought that Fridays department of commerce announcement couldn’t get worse,… Read More


TSMC 2022 Open Innovation Platform Ecosystem Forum Preview

TSMC 2022 Open Innovation Platform Ecosystem Forum Preview
by Daniel Nenni on 10-14-2022 at 6:00 am

image002 2

One of my favorite events is just around the corner and that is the TSMC OIP Ecosystem Forum and it’s at my favorite Silicon Valley venue the Santa Clara Convention Center. Nobody knows more about the inner workings of the ecosystem than TSMC so this is the premier semiconductor collaboration event, absolutely.

In my 40 years as a … Read More


Micron and Memory – Slamming on brakes after going off the cliff without skidmarks

Micron and Memory – Slamming on brakes after going off the cliff without skidmarks
by Robert Maire on 10-03-2022 at 10:00 am

Wiley Coyote Semiconductor Crash 2022 1

-Micron slams on the brakes of capacity & capex-
-But memory market is already over the cliff without skid marks
-It will likely take at least a year to sop up excess capacity
-Collateral impact on Samsung & others even more important

Micron hitting the brakes after memory market already impacts

Micron capped off an otherwise… Read More


Ansys’ Emergence as a Tier 1 EDA Player— and What That Means for 3D-IC

Ansys’ Emergence as a Tier 1 EDA Player— and What That Means for 3D-IC
by Daniel Nenni on 09-20-2022 at 10:00 am

Ansys chip package board

Over its 40+ year history, electronic design automation (EDA) has seen many companies rise, fall, and merge. In the beginning, in the 1980s, the industry was dominated by what came to be known as the big three — Daisy Systems, Mentor Graphics, and Valid Logic (the infamous “DMV”). The Big 3 has morphed over the years, eventually settling… Read More


Application-Specific Lithography: 5nm Node Gate Patterning

Application-Specific Lithography: 5nm Node Gate Patterning
by Fred Chen on 09-08-2022 at 6:00 am

Blur Limitations for EUV Exposure

It has recently been revealed that the N5 node from TSMC has a minimum gate pitch of 51 nm [1,2] with a channel length as small as 6 nm [2]. Such a tight channel length entails tight CD control in the patterning process, well under 0.5 nm. What are the possible lithography scenarios?

Blur Limitations for EUV Exposure

A state-of-the-art

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Does SMIC have 7nm and if so, what does it mean

Does SMIC have 7nm and if so, what does it mean
by Scotten Jones on 09-07-2022 at 10:00 am

SMIC 7nm

Recently TechInsights analyzed a Bitcoin Miner chip fabbed at SMIC and declared SMIC has a 7nm process. There has been some debate as to whether the SMIC process is really 7nm and what it means if it is 7nm. I wanted to discuss the case for and against the process being 7nm, and what I think it means.

First off, I want to say I am not going … Read More