Layout-aware Diagnosis

Layout-aware Diagnosis
by Paul McLellan on 08-08-2014 at 8:01 am

Traditional test methodologies have been based on the functional model, that is to say the netlist. The most well-known is probably the stuck-at model which grades a sequence of test vectors by whether they would have managed to notice the difference between a fully functional design and one where one of the signals was permanently… Read More


Taming The Challenges of SoC Testability

Taming The Challenges of SoC Testability
by Pawan Fangaria on 05-12-2014 at 10:00 pm

With the advent of large SoCs in semiconductor design space, verification of SoCs has become extremely challenging; no single approach works. And when the size of an SoC can grow to billions of gates, the traditional methods of testability of chips may no longer remain viable considering the needs of large ATPG, memory footprint,… Read More


Dinner with Dr. Walden C. Rhines!

Dinner with Dr. Walden C. Rhines!
by Daniel Nenni on 04-06-2014 at 7:00 am

You are cordially invited to have dinner with my favorite EDA CEO, Dr. Walden C. Rhines (the C stands for Clark by the way). Wally will be the dinner keynote speaker at the Electronic Design Process Symposium on April 17[SUP]th[/SUP] at the Yacht Club in Monterey. When registering use Promo Code: SemiWikiGofor $50 off. Such a deal!… Read More


New Frontiers in Scan Diagnosis

New Frontiers in Scan Diagnosis
by Paul McLellan on 01-03-2014 at 8:10 pm

As we move down into more and more advanced process nodes, the rules of how we test designs are having to change. One big challenge is the requirement to zoom in and fix problems by doing root cause analysis on test data alone, along with the rest of the design data such as detailed layout, optical proximity correction and so on. But without… Read More


Highest Test Quality in Shortest Time – It’s Possible!

Highest Test Quality in Shortest Time – It’s Possible!
by Pawan Fangaria on 12-26-2013 at 10:30 am

Traditionally ATPG (Automatic Test Pattern Generation) and BIST (Built-In-Self-Test) are the two approaches for testing the whole semiconductor design squeezed on an IC; ATPG requires external test equipment and test vectors to test targeted faults, BIST circuit is implemented on chip along with the functional logic of IC.… Read More


What Mentor Said at ITC

What Mentor Said at ITC
by Beth Martin on 09-26-2013 at 4:47 pm

At the ITC test conference in early September, Mentor made three announcements. ITC is a big event for Mentor’s test group, and where they usually roll out their new tools and capabilities. The indefatigable Steve Pateras was captured on film describing them.

I’ve summarize Mentor’s three announcements and added… Read More


Scan the horizon, P1687 takes us higher

Scan the horizon, P1687 takes us higher
by Don Dingee on 07-31-2013 at 6:00 pm

The tech standards cycle almost always goes like this: Problems or limits develop with the existing way of doing things. Innovators attempt to engineer solutions, usually many of them. Chaos ensues when customers figure out nothing new works with anything else. Competitors sit down and agree on a specification where things work… Read More


Test and Diagnosis at ISTFA

Test and Diagnosis at ISTFA
by Beth Martin on 11-15-2012 at 7:10 pm

Finding and debugging failures on integrated circuits has become increasingly difficult. Two sessions at ISTFA (International Symposium for Testing and Failure Analysis) on Thursday address the current best practices and research directions of diagnosis.

The first was a tutorial this morning by Mentor Graphics luminary… Read More


IJTAG, Testing Large SoCs

IJTAG, Testing Large SoCs
by Paul McLellan on 11-08-2012 at 5:57 pm

Test is the Rodney Dangerfield of EDA, it doesn’t get any respect. All designs need to be tested but somehow synthesis, routing, analog layout and the rest are the sexy areas. In my spoof all purpose EDA keynote address I even dissed it:You are short on time so slip in a quick mention of manufacturing test. Who knows anything … Read More


Testing ARM Cores – Mentor and ARM Lunch Seminar

Testing ARM Cores – Mentor and ARM Lunch Seminar
by Beth Martin on 07-08-2012 at 8:29 pm

If you are involved in testing memory or logic of ARM-based designs, you’ll want to attend this free seminar on July 17, 2012 in Santa Clara. Mentor Graphics and ARM have a long standing partnership, and have optimized the Mentor test products (a.k.a Tessent) for the ARM processors and memory IP.

The lunch seminar runs from 10:30-1:00… Read More