Analog Panel Discussion at DesignCon

Analog Panel Discussion at DesignCon
by Daniel Payne on 01-20-2012 at 7:59 pm

DesignCon is coming up and the panel discussions look very interesting this year. The one panel session that I recommend most is called, “Analog and Mixed-Signal Design and Verification” which is moderated by Brian Bailey, one of my former Mentor Graphics buddies and fellow Oregonian.… Read More


Low-power IC design in Switzerland

Low-power IC design in Switzerland
by Daniel Payne on 01-18-2012 at 7:17 pm

My wife and I have traveled to Switzerland on vacation and marveled at the natural beauty of the mountains, efficient train system, tasty chocolate, and wonderful foods. I only wished that our American dollar bought more in Swiss currency than it did. Recently I discovered a high-tech IC design company called Microdul that designs… Read More


MEMS layout and automation

MEMS layout and automation
by Daniel Payne on 12-14-2011 at 11:12 am

At a webinar today I listened and learned about how a tool called L-Edit can be used to layout MEMS designs plus automate the task to be more productive. I can see how the history of IC layout editing is now being repeated with MEMS because in the earliest IC layout tools we could only do manual entry of polygons, then gradually we got cells… Read More


Learning About MEMS

Learning About MEMS
by Daniel Payne on 12-12-2011 at 6:34 pm

My automobile has an air bag system that uses a MEMS (Micro Electro Mechanical System) sensor to tell it when to deploy, and I’ve read headlines talking about MEMS over the years so I decided it was about time to learn more by attending a Webinar on Wednesday, December 14th at 8AM Pacific Time.

The EDA company hosting the Webinar… Read More


A Review of an Analog Layout Tool called HiPer DevGen

A Review of an Analog Layout Tool called HiPer DevGen
by Daniel Payne on 11-28-2011 at 1:11 pm

My last IC design at Intel was a Graphics Chip and I developed a layout generator for Programmable Logic Arrays (PLA) that automated the task, so I’ve always been interested in how to make IC layout more push-button and less polygon pushing. Today I watched a video about HiPer DevGen from Tanner EDA and wanted to share what I … Read More


AMS Design using Dongbu HiTek foundry and Tanner EDA Tools

AMS Design using Dongbu HiTek foundry and Tanner EDA Tools
by Daniel Payne on 10-27-2011 at 12:00 pm

Every analog designer needs a foundry PDK (Process Design Kits) and EDA tools to design, layout and verify their AMS chip or IP. This week I had a chance to conduct an email interview with Taek-Soo Kim, VP of Technical Engineering at Dongbu HiTek in Korea. This specialty foundry supplies analog silicon worldwide.

Interview
Q: Tell… Read More


AMS Design at AnSem

AMS Design at AnSem
by Daniel Payne on 10-19-2011 at 3:40 pm

AnSem has been in the AMS design business since 1998 and uses a variety of commercial EDA tools along with internally developed tools and scripts to automate the process of analog design and technology porting. Their IC designers have completed some 40 AMS projects in diverse areas like:

  • RF CMOS
    • LNA, VCO, Mixers
    • Synthesizers
    • Low-IF/Zero-IF
Read More

Tanner EDA Newsletter – Fall 2011

Tanner EDA Newsletter – Fall 2011
by Daniel Payne on 09-15-2011 at 10:47 am

logo top

From the President: Another Great YearThanks to innovative, cost-effective technology and excellence in customer support, we’ve just ended fiscal year 2011 (on May 31st) with solid growth. Revenue was up 8%, we added 139 new customers, and we’re continuing to reach out to technology partners for MEMS and for the analog and mixed-signalRead More


Another Up Year in a Down Economy for Tanner EDA

Another Up Year in a Down Economy for Tanner EDA
by Daniel Payne on 09-13-2011 at 11:00 am

Almost every week I read about a slowing world economy, yet in EDA we have some bright spots to talk about, like Tanner EDA finishing its 24th year with an 8% increase in revenue. More details are in the press release from today.

I spoke with Greg Lebsack, President of Tanner EDA on Monday to ask about how they are growing. Greg has been… Read More


An Affordable 3D Field Solver at DAC

An Affordable 3D Field Solver at DAC
by Daniel Payne on 06-17-2011 at 6:35 pm

Intro
Massimo Sivilotti, Ph.D of Tanner EDA showed me their 3D field solver in the HiPer PX extraction tool at DAC last week.

Notes

Tool Suites – schematics, layout, SPICE simulation, DRC/LVS
– HiPer PX: 3D Field solvero Layers, dielectrics,
o Finite element analysis
o Boundary element methods
o 2D mode for pattern matching… Read More