Help, my IP has fallen and can’t get up

Help, my IP has fallen and can’t get up
by Don Dingee on 02-03-2013 at 8:10 pm

We’ve been talking about the different technologies for FPGA-based SoC prototyping a lot here in SemiWiki. On the surface, the recent stories all start off pretty much the same: big box, Xilinx Virtex-7, wanna go fast and see more of what’s going on in the design. This is not another one of those stories. I recently sat down with Mick… Read More


Common Platform Technology Forum February 5th 2013 Live or Online!

Common Platform Technology Forum February 5th 2013 Live or Online!
by Daniel Nenni on 02-03-2013 at 8:00 am

Can’t make it to Santa Clara? Join us online!

The detailed 2013 CPTF agenda is now up in preparation for the February 5th event at the Santa Clara Convention Center. This is one of the rare times that you can get a free lunch! Watch this quick video to see what is in store for us this year. Dr. Paul McLellan and I will be there so please… Read More


Improving Methodology the NVIDIA Way

Improving Methodology the NVIDIA Way
by Paul McLellan on 01-29-2013 at 2:57 pm

I was at DesignCon in Santa Clara today and listened to Jonah Alben of NVIDIA’s keynote on what their approach is to improving design methodology. He started by pointing out that most companies underinvest in EDA (and he includes NVIDIA in this). Partially it is complaceny: that last chip taped out so we know we can do it again.… Read More


Cadence, Synopsys, and Mentor on FinFETs

Cadence, Synopsys, and Mentor on FinFETs
by Daniel Nenni on 01-27-2013 at 7:00 pm

In my opinion, FinFETs will be the most significant piece of technology we, as semiconductor ecosystem people, will experience this decade. Seriously this is exciting stuff and one of the top search terms on SemiWiki for 6 months running. Here is a quick peek at what the top EDA companies will be talking about at the Common PlatformRead More


Verdi: No Requiem for Openness

Verdi: No Requiem for Openness
by Paul McLellan on 01-22-2013 at 8:10 pm

I sat down last week for lunch with Michael Sanie. Mike and I go back a long way, working together at VLSI Technology (where his first job out of school was to take over the circuit extractor that I’d originally written) and then in strategic marketing at Cadence. Now Mike has marketing for (almost?) all of Synopsys’s … Read More


New PCI Express 3.0 Equalization Requirements

New PCI Express 3.0 Equalization Requirements
by Eric Esteve on 01-22-2013 at 9:18 am

PCI Express 3.0 increased the supported data rate to 8 Gbps, which effectively doubles the data rate supported by PCI Express 2.0. While the data rate was increased, no improvement was made to the channels. As such, an 8 Gbps channel in PCIe 3.0 experiences significantly more loss than one implemented in PCIe 2.0. To compensate for… Read More


Double Patterning for IC Design, Extraction and Signoff

Double Patterning for IC Design, Extraction and Signoff
by Daniel Payne on 01-21-2013 at 3:27 pm

TSMC and Synopsys hosted a webinar in December on this topic of double patterning and how it impacts the IC extraction flow. The 20nm process node has IC layout geometries so closely spaced that the traditional optical-based lithography cannot be used, instead lower layers like Poly and Metal 1 require a new approach of using two… Read More


Yawn… New EDA Leader Results Are Coming

Yawn… New EDA Leader Results Are Coming
by Randy Smith on 01-18-2013 at 4:00 pm

We will soon start to see the quarterly financial reporting installments of the “Big 3” public EDA companies. I predict they will be as boring as usual. I am not sure if I would want it any differently though.

Back in the 90s there were times when it was truly interesting to wait to see what Cadence, Mentor, or later Synopsys, might announce.… Read More


IP vendors enable SuperSpeed USB IP take off in 2012

IP vendors enable SuperSpeed USB IP take off in 2012
by Eric Esteve on 01-15-2013 at 5:09 am

SuperSpeed USB has been clearly ranked in the Interface protocols winner list, see this previous post. It could be interesting to dig into this IP market segment, determine in which applications USB 3.0 has been successfully deployed and who are the IP vendors serving this market, enabling SuperSpeed USB to take off.

SuperSpeed… Read More


A Brief History of Synopsys DesignWare ® IP

A Brief History of Synopsys DesignWare ® IP
by Daniel Nenni on 01-11-2013 at 9:00 am

Let’s play word association. I say “EDA”, you immediately think “Synopsys”. I say “IP” and although 15 years ago you may not, today, you think “Synopsys”. For nearly two decades, Synopsys has grown its IP business through both organic development and acquisition, with a clear focus on enabling designers to meet their time-to-market… Read More