Design Rule Checking (DRC) Meets New Challenges

Design Rule Checking (DRC) Meets New Challenges
by Daniel Payne on 12-02-2014 at 7:00 am

The traditional batch-oriented DRC process run as a final check to ensure compliance with foundry yield goals is quickly moving toward a concurrent DRC process performed early and often throughout design, especially at the 28 nm and smaller process nodes. What are the technology factors causing this change?

  • Increasing number
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Using HAPS-DX for system-level deep trace debug

Using HAPS-DX for system-level deep trace debug
by Don Dingee on 11-20-2014 at 4:00 pm

Debugging an ASIC design in an FPGA-based prototyping system can be a lot like disciplining a puppy. If you happen to be there at the exact moment the transgression occurs and understand what led up to that moment, administering an effective correction might be possible.

Catching RTL in the act requires the right tools. Faults in… Read More


Semiconductor IP Make the World Go Round!

Semiconductor IP Make the World Go Round!
by Daniel Nenni on 11-16-2014 at 3:00 pm

Semiconductor IP really does make the life of a semiconductor professional much easier which is why Google brings us so much IP traffic. If you look at the SemiWiki analytics, IP has always been a top draw. In comparison to standard EDA traffic, IP gets about 25% more views per blog on average. Synopsys is not only the leading EDA company… Read More


What Presentations to Attend During IP-SoC 2014 ?

What Presentations to Attend During IP-SoC 2014 ?
by Eric Esteve on 11-01-2014 at 11:00 am

Will you go to Grenoble next week to attend to IP-SoC? I will do it and will certainly listen to these Keynote Talks:

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Two New Announcements at ITC from Synopsys

Two New Announcements at ITC from Synopsys
by Daniel Payne on 10-22-2014 at 4:00 pm

Each year at the International Test Conference(ITC) we hear about the latest advances from the testability side of both EDA vendors and academics. This year Aart de Geus, Chairman and Co-CEO of Synopsys delivered a keynote speech titled, “Testing Positive, for Complexity“. Yesterday I spoke with Robert Ruiz and… Read More


Linux and the ARC of the Coherent

Linux and the ARC of the Coherent
by Don Dingee on 10-18-2014 at 7:00 am

Remember that thing called “real-time Linux”? Yeah, nobody else does either. As builds became configurable and clock speeds increased, embedded Linux manifested itself as fast enough for many applications – if a few other SoC details are addressed.

Most obvious for SoCs to run Linux is the need for a fully integrated MMU implementation.… Read More


Mentor Wins v Synopsys

Mentor Wins v Synopsys
by Paul McLellan on 10-15-2014 at 10:00 am

Just a couple of days ago I read a curious press release.Mentor Graphics Corp. (NASDAQ: MENT), today announced that a Portland, Oregon jury delivered a verdict in favor of Mentor in a trial in which Mentor asserted infringement of one of its patents against Emulation and Verification Engineering S.A. (EVE) and Synopsys, Inc. (Nasdaq:Read More


Designing SmartCar ICs

Designing SmartCar ICs
by Daniel Payne on 09-30-2014 at 7:00 am

When I upgraded cars from a 1988 to 1998 Acura it seemed like my car had become much smarter with a security chip in the key, security codes in the radio and a connector for computer diagnosis, however in today’s modern auto there’s a lot more mixed-signal design content. Micronasand Synopsysgot together and hosted … Read More


Explaining HAPS-DX in an elevator

Explaining HAPS-DX in an elevator
by Don Dingee on 09-24-2014 at 7:00 am

Every development team has been through this challenge: finding a tool that looks fantastic, then heading off to the manager one or two levels up who has enough signature authority for the purchase order. Signatures for amounts reading more than a couple of trailing zeros on POs are rarely free, or painless. … Read More


AMD Design IP Deal with Virage Logic… Oops… Synopsys

AMD Design IP Deal with Virage Logic… Oops… Synopsys
by Eric Esteve on 09-23-2014 at 9:59 am

Whoever has said that history never repeats itself should read this recent PR from AMD! The news can be summarized in three points:

  • Multi-year agreement gives AMD access to a range of Synopsys design IP including interface, memory compiler, logic library and analog IP for advanced FinFET process nodes
  • Synopsys acquires rights
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