Are Your Transistor Models Good Enough?

Are Your Transistor Models Good Enough?
by Daniel Payne on 08-16-2016 at 12:00 pm

SoC designers can now capture their design ideas with high-level languages like C and SystemC, then synthesize those abstractions down into RTL code or gates, however in the end the physical IC is implemented using cell libraries made up of transistors. Circuit designers use simulation tools like SPICE on these transistor-level… Read More


It’s Time to Put Your Spice Netlists on a Diet

It’s Time to Put Your Spice Netlists on a Diet
by Tom Dillinger on 06-28-2016 at 7:00 am

Spice circuit simulation remains the backbone of IC design validation. Digital cell library developers rely upon Spice for circuit characterization, to provide the data for Liberty models. Memory IP designers utilize additional Spice features to perform statistical sampling. Analog and I/O interface designers extend these… Read More


The Emerging Importance of Parallel SPICE

The Emerging Importance of Parallel SPICE
by Tom Dillinger on 05-15-2016 at 7:00 am

SPICE simulation is the workhorse tool for custom circuit timing validation and electrical analysis. As the complexity of blocks and macros has increased in advanced process nodes — especially with post-layout extraction parasitic elements annotated to the circuit netlist — the model size and simulation throughput… Read More


Process Development, CAD and Circuit Design

Process Development, CAD and Circuit Design
by Daniel Payne on 04-29-2016 at 7:00 am

Working at Intel as a circuit designer I clearly remember how there were three distinct groups: Process Development, CAD and Circuit Design. Each of the groups sat in a different part of the building in Aloha Oregon, we had different job titles, different degrees, spoke with different acronyms and yet we all had to work together … Read More


Webinar: A Tool for Process and Device Evaluation

Webinar: A Tool for Process and Device Evaluation
by Tom Simon on 03-24-2016 at 12:00 pm

Not only are foundries continuing to introduce processes at new advanced nodes, they are frequently updating or adding processes at existing nodes. There are many examples that illustrate this well. TSMC now has 16FF, 16FF+ and now 16FFC. They are also announcing 10nm and 7nm processes. In addition, they are going back to older… Read More


Multi-Level Debugging Made Easy for SoC Development

Multi-Level Debugging Made Easy for SoC Development
by Pawan Fangaria on 03-01-2016 at 7:00 am

An SoC can have a collection of multiple blocks and IPs from different sources integrated together along with several other analog and digital components within a native environment. The IPs can be at different levels of abstractions; their RTL descriptions can be in different languages such as Verilog, VHDL, or SystemVerilog.… Read More


Synopsys’ New Circuit Simulation Environment Improves Productivity — for Free

Synopsys’ New Circuit Simulation Environment Improves Productivity — for Free
by Pawan Fangaria on 02-07-2016 at 12:00 pm

When technology advances, complexities increase and data size becomes unmanageable. Fresh thinking and a new environment for automation are needed to provide the required increase in productivity. Specifically in case of circuit simulation of advanced-node analog designs, where precision is paramount and a large number… Read More


How 16nm and 14nm FinFETs Require New SPICE Simulators

How 16nm and 14nm FinFETs Require New SPICE Simulators
by Daniel Payne on 02-07-2016 at 7:00 am

About 35 years ago the first commercial SPICE circuit simulators emerged and they were quickly put to work helping circuit designers predict the timing and power of 6um NMOS designs. Then we had to limit our circuit simulations to just hundreds of transistors and interconnect elements to fit into the RAM and complete simulation… Read More


Mass customization coming to MEMS?

Mass customization coming to MEMS?
by Don Dingee on 12-18-2015 at 10:00 am

With the industry abuzz about the Apple purchase of a Maxim Integrated fab as a potential R&D facility for MEMS design, it begs the question: is creating a MEMS device that easy?

MEMS technology is approaching the same fork in the road where digital design encountered LSI four decades earlier. … Read More


All Models Are Wrong, Some Are Useful

All Models Are Wrong, Some Are Useful
by Paul McLellan on 09-15-2015 at 7:00 am

“All models are wrong, some are useful.” This remark is attributed to the statistician George Box who used it as the section heading in a paper published in 1976.

Just for fun I looked up a few semiconductor statistics from 1976. Total capital spending was $238M in Japan and $306M in US and…that’s it, there was nobody else back then … Read More