IEDM 2018 Trip Report!

IEDM 2018 Trip Report!
by Daniel Nenni on 12-10-2018 at 7:00 am

Hello, my name is Daniel Nenni and I am a semiconductor conference addict. I just can’t seem to get enough. The semiconductor ecosystem is very wide now and moves so quickly it is nearly impossible to keep up without constant conference attendance. As a SemiWiki contributor not only do I get free conference passes, I get access to … Read More


Improving Library Characterization with Machine Learning!

Improving Library Characterization with Machine Learning!
by Daniel Nenni on 12-04-2018 at 7:00 am

For SOC designers that are waiting for library models the saying “give me liberty or give me death” is especially apropos. Without libraries to support the timing flow, SOC design progress can grind to a halt. As is often the case, more than just a few PVT corners are needed. Years ago, corners were what the term sounded like – the 4 corners… Read More


AMAT and the Jinhua Jinx!

AMAT and the Jinhua Jinx!
by Robert Maire on 11-18-2018 at 7:00 am

Applied Materials reported a just “in line” quarter but guidance was well below street expectation. AMAT reported EPS of $0.97 and revenues of $4.01B versus street of $0.97 and $4B. Guidance missed the mark by a wide margin with revs of $3.56 to $3.86 and EPS of $0.75 to $0.83 versus already reduced street expectations… Read More


Eliminate PCB Re Spins using an Integrated Multi Dimensional Verification Platform

Eliminate PCB Re Spins using an Integrated Multi Dimensional Verification Platform
by Daniel Nenni on 11-15-2018 at 12:00 pm

The rapidly increasing complexity of today’s designs, combined with schedule pressure to deliver innovative products to market as quickly as possible, strains engineering resources to the limit, often to the point of breaking. As a result, 17% of all projects get canceled, and another 28% miss their target release date (Source:… Read More


DAC 2019 to Host the Second System Design Contest!

DAC 2019 to Host the Second System Design Contest!
by Daniel Nenni on 11-13-2018 at 7:00 am

Interested in showing off your talent in developing deep learning algorithms on embedded hardware platforms for solving real-world problems? Join the second System Design Contest (SDC) at the 56[SUP]th[/SUP] Design Automation Conference in 2019!… Read More


Intel Diversity Semiconductors

Intel Diversity Semiconductors
by Daniel Nenni on 11-12-2018 at 7:00 am

Growing up in a military family, mostly in California, I would consider my cultural diversity life experience to be more than most. I remember in the 1960s some older folks were chattering about a colored family moving into our neighborhood and they had a son my age. Imagine my excitement as a child in having a multicolored friend!… Read More


Is ARM TechCon Really Worth it?

Is ARM TechCon Really Worth it?
by Daniel Nenni on 11-05-2018 at 6:00 am

The ARM TechCon organizers are asking me what I thought of this year’s conference so here it goes. As you know I am a big fan of ARM TechCon and feel it is one of the better conferences for SoC design. This year however I noticed a big change in demographics. Maybe the location change had something to do with it but I definitely saw different… Read More


Playing the Long Game with 56G SerDes

Playing the Long Game with 56G SerDes
by Daniel Nenni on 11-02-2018 at 12:00 pm

IP has always been a hot topic on SemiWiki with quite a bit of our readers doing the “make versus buy” analysis. SerDes is one of the more difficult “makes” so it is mostly a “buy” analysis made by networking class ASIC architects and a handful of other applications that demand high performance and throughput. Based on the recent traffic… Read More


AI and the Domain Specific Architecture

AI and the Domain Specific Architecture
by Daniel Nenni on 10-03-2018 at 7:00 am

Last month I attended the 2018 U.S. Executive Forum where Wally Rhines was one of the keynotes. I was also lucky enough to have lunch with Wally afterwards and talk about his presentation in more detail and he sent me his slides which are attached to the end of this blog.

The nice thing about Wally’s presentations is that they are not … Read More


Crossfire Baseline Checks for Clean IP at TSMC OIP

Crossfire Baseline Checks for Clean IP at TSMC OIP
by Daniel Nenni on 09-26-2018 at 12:00 pm

IP must be properly qualified before attempting to use them in any IC design flow. One cannot wait to catch issues further down the chip design cycle. Waiting for issues to appear during design verification poses extremely high risks, including schedule slippage. For example, connection errors in transistor bulk terminals where… Read More