While the debate rages on about 28nm yield at foundry juggernaut TSMC, on Monday I attended a webinar on 20nm IC design hosted by TSMC and Synopsys. Double Patterning Technology (DPT) becomes a requirement for several layers of your 20nm IC design which then impact many of your EDA tools and methodology.… Read More
And no red and green glasses required.
I remember the first time I heard about a Through Silicon Via (TSV), punching a hole through the entire wafer to make an electrical connection at the back, like we do all the time in printed circuit boards with through plated holes. I thought someone was trying one on and trying to make me look a fool.… Read More
I love to read good news about growth in EDA especially when our industry has seen single-digit growth for several years now. What I read on March 8th from ClioSoft stated a 53% increase in bookings for 2011, now that’s what I call growth.
ClioSoft provides Hardware Configuration Management (HCM) software to EDA users typically… Read More
Continued from < Part 1 <… Read More
HSPICE users gathered in January 2012 at the HSPICE SIG(Special Interest Group) to talk about their experiences using this circuit simulator for a variety of IC and signal integrity issues. I wasn’t able to attend in person however I did watch the video and wanted to summarize what I heard:… Read More
I’ve often wanted to publish a book with nothing but photos of police cars, so that people wouldn’t have to slow down and gawk at them when they have someone pulled over on the side of the freeway. Intel roadmaps seem to have the same effect on people. No matter what is on them, even if there’s nothing really new, they… Read More
DVCon is next week, which I’m sure you know already if you are in verification. Of course Synopsys has a rich product portfolio in verification and verification IP (VIP) so is pretty visible at the show.
On Wednesday they are sponsoring lunch. Several Synopsys customers will talk about their view of how the verification landscape… Read More
Atrenta will be on a panel session at VLSI 2012 next week in Hyderabad in the center of India. Since I had a development group there over a decade ago this is actually one of the few cities in India that I have visited. Beautiful but very hot at the time I was there.
Atrenta will be represented by Sathyam Pattanam the director of engineering… Read More
America has received a gift whose consequence and magnitude is just now unfolding before our eyes. Taken to its limits, it may in the course of the next decade finally free us from many of our foreign entanglements while lifting the economic burdens from the working majority that has seen their wages stagnate for the past 40 years.… Read More
My automobile has an air bag system that uses a MEMS (Micro Electro Mechanical System) sensor to tell it when to deploy, and I’ve read headlines talking about MEMS over the years so I decided it was about time to learn more by attending a Webinar on Wednesday, December 14th at 8AM Pacific Time.
The EDA company hosting the Webinar… Read More
