Forte Rises

Forte Rises
by Randy Smith on 04-23-2013 at 3:00 am

Over the past few months there has been a bit of back-and-forth concerning the 2012 market data indicating that Forte Designs Systems had taken over the top spot (by revenue) in the high-level synthesis (HLS) market (see stories hereand here). Having worked in this segment for Synfora as VP of Marketing, and as a consultant to AutoESL,… Read More


FinFET Day Presentations at EDPS Monterey!

FinFET Day Presentations at EDPS Monterey!
by Daniel Nenni on 04-22-2013 at 10:00 am

If you are ever asked to organize a conference session do not hesitate, accept immediately and jump right in. When John Swan, EDPS General Chair, asked me to organize a day I hesitated. Fortunately he is not one to take no for an answer. It was an unforgettable experience on many levels and I hope to be involved with EDPS again next year.… Read More


ISCUG – Excellent Indian Conference, needs to grow

ISCUG – Excellent Indian Conference, needs to grow
by Pawan Fangaria on 04-21-2013 at 8:05 pm

Promoted by Accellera, SystemC User Groups are in work worldwide; NASCUGin North America, ESCUGin Europe and ISCUG in India. While I was shuffling between my day-to-day work and strategy management course/exams, I received an invitation from my long time colleague, President and CEO of Circuitsutra Technologies, Mr. UmeshRead More


FPGAS – The New Single Board Computers?

FPGAS – The New Single Board Computers?
by Luke Miller on 04-16-2013 at 10:00 pm

I have always felt that FPGAs have been the red haired step child of Silicon Valley. Software weenies have hated them, they are mysterious and take too long to route. Even though they can be massively parallel and the most deterministic piece of silicon you can buy besides a million dollar ASIC, the GPU steals their glory, for now. … Read More


Two New TSMC-Cadence Webinars for Advanced Node Design

Two New TSMC-Cadence Webinars for Advanced Node Design
by Daniel Payne on 04-15-2013 at 3:43 pm

Foundries and EDA vendors are cooperating at increasing levels of technical intimacy as we head to the 20nm and lower nodes. Cadence has a strong position in the EDA tools used for IC design and layout of custom and AMS (Analog Mixed-Signal) designs. They have created a series of webinars to highlight the design challenges and new… Read More


Intelligent tools for complex low power verification

Intelligent tools for complex low power verification
by Pawan Fangaria on 04-02-2013 at 8:05 pm

The burgeoning need of high density of electronic content on a single chip, thereby necessitating critical PPA (Power, Performance, Area) optimization, has pushed the technology node below 0.1 micron where static power becomes equally relevant as dynamic power. Moreover, multiple power rails run through the circuit at different… Read More


Tackling Circuit Level EM Analysis for RF, MMW and High Speed Analog Designs

Tackling Circuit Level EM Analysis for RF, MMW and High Speed Analog Designs
by Daniel Nenni on 03-31-2013 at 8:07 pm

Accuracy, ease of use and performance have always been paramount for electromagnetic analysis software. Historically, it has been hard to find all three of these qualities in one tool. The result is that many high speed analog and RF designers resort to using multiple, often overlapping, tools to get the job done.

Lorentz Solution… Read More


View from the top: Brad Quinton

View from the top: Brad Quinton
by Daniel Payne on 03-20-2013 at 3:53 pm

Many engineers dream about starting their own company some day, and today I talked with an engineer that has gone beyond the dreaming stage to actually start an EDA company and then get that company acquired. His name is Brad Quinton and the start-up was called Veridae Systems, now part of Tektronix.


Brad QuintonRead More


Interconnect Optimization of an SoC Architecture

Interconnect Optimization of an SoC Architecture
by Daniel Payne on 03-20-2013 at 11:41 am

My last chip design at Intel was a GPU called the 82786and the architects of the chip wrote a virtual prototype using the MAINSAIL language. By using a virtual prototype they were able to:

  • Simulate bus traffic, video display and video RAM
  • Determine throughput
  • Measure latency
  • Verify that bus priorities were working
  • Optimize the
Read More