Cadence at Semicon West Next Week: 2.5D and 3D

Cadence at Semicon West Next Week: 2.5D and 3D
by Paul McLellan on 07-05-2012 at 5:32 pm

Next week it is Semicon West in the Moscone Center from Tuesday to Thursday, July 10-12th. Cadence will be on a panel session during a session entitled The 2.5D and 3D packaging landscape for 2015 and beyond. This starts with 3 short keynotes:

  • 1.10pm to 1.25pm: Dr John Xie of Altera on Interposer integration through chip on wafer on
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Minitel Shuts Down

Minitel Shuts Down
by Paul McLellan on 07-05-2012 at 5:02 pm

When I first came to the US, one project that we had going on at VLSI Technology was an ASIC design being done by a French company called Telic. The chip would go into something called “Minitel” which the France Telecom (actually still the PTT since post and telecomunications had not yet been separated) planned to supply… Read More


IC Design at Novocell Semiconductor

IC Design at Novocell Semiconductor
by Daniel Payne on 07-05-2012 at 12:09 pm

In my circuit design past I did DRAM work at Intel, so I was interested in learning more about Novocell Semiconductor and their design of One Time Programmable (OTP) IP. Walter Novosell is the President/CTO of Novocell and talked with me by phone on Thursday.… Read More


Crushed Blackberry

Crushed Blackberry
by Paul McLellan on 07-02-2012 at 12:00 am

I wasn’t going to write about the cell phone business again for some time. After all, this is a site about semiconductor and EDA primarily. But the cell-phone business in all its facets is a huge semiconductor consumer and continues to grow fast (despite my morbid focus on those companies that do anything but).

But Research… Read More


The Scariest Graph I’ve Seen Recently

The Scariest Graph I’ve Seen Recently
by Paul McLellan on 07-01-2012 at 4:00 pm

Everyone knows Moore’s Law: the number of transistors on a chip doubles every couple of years. We can take the process roadmap for Intel, TSMC or GF and pretty much see what the densities we will get will be when 20/22nm, 14nm and 10nm arrive. Yes the numbers are on track.

But I have always pointed out that this is not what drives… Read More


Chip Synthesis at DAC

Chip Synthesis at DAC
by Paul McLellan on 06-27-2012 at 8:30 pm

I visited Oasys Design Systems and talked to Craig Robbins, their VP sales. For the first time this year, Oasys has a theater presentations and demos of RealTime Designer which are open to anyone attending the show. In previous years, they have had suite demos for appropriately qualified potential customers but outside they have… Read More


TSMC Threater Presentation: Lorentz Solution!

TSMC Threater Presentation: Lorentz Solution!
by Daniel Nenni on 06-26-2012 at 8:30 pm

Lorentz Solution presented at TSMC’s DAC 2012 Open Innovation Platform Theater. The presenter was Lorentz Sales Director, Tom Simon. He presented what Lorentz calls its Electromagnetic Design and Analysis Platform. One of the main points of the talk was the cooperative work that Lorentz does with TSMC.

TSMC and Lorentz work … Read More


Microsoft Messes Up Mobile Even More…and Already Went Thermonuclear

Microsoft Messes Up Mobile Even More…and Already Went Thermonuclear
by Paul McLellan on 06-25-2012 at 11:01 pm

Ed wrote recently about Microsoft going thermonuclear. I think that they already did. Ed wrote about Microsoft’s tablet announcement. The second announcement is a sort of follow up to my blog on what will happen to Nokia.

Two big announcements, the first one is that Microsoft is going to produce its own tablet computers (MiPads … Read More


AMS Simulation Update from Mentor Graphics at DAC

AMS Simulation Update from Mentor Graphics at DAC
by Daniel Payne on 06-25-2012 at 12:36 pm

I met with Jay Madiraju of Mentor Graphics on Wednesday at DAC to get an update on their AMS simulation products. We worked together at Mentor back when Mach TA was being developed as a Fast SPICE circuit simulator.… Read More