As your SoC design can contain hundreds of IP blocks, how do you verify that all of the IP blocks will still work together correctly once assembled? Well, you could run lots of functional verification at the full-chip level and hope for the best in terms of code coverage and expected behavior. You could buy an expensive emulator to … Read More
Tag: semiconductor
2014 Semiconductor Growth Could be 2X 2013 Rate
The fourth quarter 2013 semiconductor market declined 0.8% from the third quarter, according to World Semiconductor Trade Statistics (WSTS). Full year 2013 growth was 4.8%. Our most recent 2013 forecast at Semiconductor Intelligence was 6% in November 2013, based on expectations of positive growth in 4Q 2013. Who had the most… Read More
Mounir Hahad Rejoins Silvaco
Mounir Hahad just joined Silvaco as VP engineering. And when I say joined I really mean rejoined. I had a call with him to find out how that happened.
Mounir studied in France for a PhD in computer science on numerical computing. In 1995 the then-director of TCAD at Silvaco called him up having read some of his published papers. Silvaco… Read More
Before SPICE Circuit Simulation Comes TCAD Tools
I’ve run SPICE circuit simulators since the 1970’s and they use transistor models where the device parameters are provided by the foundry. These transistor and interconnect parameters come from an engineer at the foundry who has characterized silicon with actual measurements or by running a TCAD (Technology CAD)… Read More
ISSCC: Analog-Digital Converter in FD-SOI
The International Solid-State Circuits Conference (ISSCC) was last week in San Francisco. Stéphane Le Tual, Pratap Narayan Singh, Christophe Curis, Pierre Dautriche, all from STMicroelectronics presented a paper on A 20GHz-BW 6b 10GS/s 32mW Time-Interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI Technology… Read More
Synopsys Acquires Coverity
Synopsys announced this afternoon that they are acquiring Coverity for $375M subject to all the usual reviews.
There are a couple of other big EDA connections. Aki Fujimora, who was CTO of Cadence, is on the board. And Adreas Kuehlmann is the VP of R&D. He used to run Cadence Berkeley Laboratories before moving to the other end… Read More
Brian Krzanich Does Reddit AMA
Do you know what an AMA is on Reddit? It stands for “ask me anything”. A person, often a famous person like Bill Gates (last week) but sometimes just someone who does an interesting job (like astronaut) or was in an interesting situation (like the hijack from Ethiopia last week).
Today, it is someone who argualble is all… Read More
Verifying DRC Decks and Design Rule Specifications
DRVerify is part of the iDRM design rule compiler platform from Sage DA, something that I have been personally involved with for the past three years. DRVerify is mainly used to verify third party design rule check (DRC) decks and ensure that they correctly, completely and accurately represent the design rule specification. In… Read More
Verification of Power Delivery Networks
Power delivery networks (PDN) are the metal structures on a chip that delivers the power. In a high-end desktop SoC this might be delivering as much as 150W, and with voltages around 1V that means over 150 amps of current. Clearly getting the PDN correct is critical for a correctly functioning chip. One of the challenges to verifying… Read More
Power Control Moving into Hardware
Sonics have been building networks-on-chips (NoCs) for a long time and have amassed a rich patent portfolio. So being granted a new one isn’t usually deemed press-release-worthy. However, their latest patent on power management is pretty significant. It is patent 8,601,288 titled “Intelligent Power Controller”.
Historically… Read More