The Electronic Design Process Symposium is an annual workshop run by the IEEE Computer Society of Silicon Valley and the IEEE Council on Electronic Design Automation. I presented there because it’s devoid of product marketing pitches, and is two days of discussion on technical and process issues in SoC design. My slides are here:… Read More
Tag: semiconductor ip
Webinar: Making Design Reuse Work
Please join me for an IP conversation in collaboration with ClioSoft on Wednesday, April 30th, 2014 @ 11:00 AM PST. At the EDPS Workshop IP day there were two interesting presentations on IP reuse. The first one was by Warren Savage of IPextreme: Top Ten Reasons Why Internal IP Reuse Fails. The second was by Ranjit Adhikary of ClioSoft:… Read More
Shorten Time to Market for NVM Express Based Storage Solution
A number of technical and business trends are converging to create a booming market for solid state drives (SSDs), with gigabytes of flash memory capacity along with the related control electronics packaged in the form factor of a 1.8”‐, 2.5”‐ or 3.5”. storage device. The first is the emergence of tablets and pervasiveness of smart… Read More
ARM Results, Strong Biceps
ARM announced their Q1 results yesterday. Having just written that Intel lost $1B in mobile, I guess I could have used the title “ARM didn’t lose $1B in mobile.” They made $100M (on revenues of $300M). So let’s start off with what their results actually were and then look at what other things of interest … Read More
IP the eSilicon Way
Pop quiz: eSilicon has a big IP development group in what Asian country? If you didn’t know and you guessed, you probably got it wrong with China or India. It is Vietnam. In fact they have two sites. One in Ho Chi Minh City (that used to be called Saigon) and one in Da Nang.
At Electronic Design Process Symposium (EDPS) held last … Read More
On-chip Firewall
We have had the Snowden revelations that the NSA has gone rogue, Target lost a zillion credit cards, the Heartbleed bug meaning that main security protocol of the internet had been coded up wrong for a couple of years, theft of records from RSA and more. One result is that people do not completely trust a security system that depends… Read More
Sonics Performance Monitor and Hardware Trace
As SoCs have got more complex, and with a larger and larger software content, it is no longer good enough to just monitor how the design behaves using simulation and then completely forget about it once the design is complete. What is required is the capability to monitor the design in real time (in silicon or FPGA) to see how it is behaving.… Read More
eSilicon on Semiconductor IP Challenges
On April 18, 2014 in Monterey California there will be a series of discussions on the challenges of IP reuse. These discussions are part of the 2014 Electronic Design Process Symposium (EDPS). Representatives from IP, ASIC, foundry and EDA will weigh in the challenges and issues. Here is a preview of one of the presentations from… Read More
IP Challenges, FinFET, 3D-IC, and FD-SOI Updates
Semiwiki is proud to be a sponsor of EDPS 2014:
April 17 & 18, 2014
Monterey Beach Hotel, Monterey, CA
Sponsored by:
IEEE Computer Society of Silicon Valley (CS-SCV)
IEEE Computer Society
Design Automation Technical Committee (DATC)
Council on Electronic Design Automation (CEDA)
The Electronic Design Processes Symposium… Read More
DAC: Automotive, IP and Security
DAC is in the first week of June in San Francisco as I’m sure you already know if you are reading this. Historically DAC has focused on electronic design automation (EDA) and embedded software and systems (ESS). This year there are three new areas: automotive, Intellectual Property (IP) and security.
Automotive
Ever increasing… Read More